JPS601719B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic bubble memory and a charge coupled device (CCD).
Regarding the control method of a shift register-like memory such as a memory, in detail, a normal loop of the shift register-like memory,
The present invention relates to a method for selectively using defective loops.

Conventionally, mechanical rotating memory devices such as magnetic drum memory devices and magnetic disk memory devices have been used as file memories in information processing devices.

However, with recent advances in semiconductor technology, solid-state file memory devices such as magnetic bubble memory devices and charge-coupled devices have appeared, and some have even been put into practical use. Since this solid-state file memory element does not involve mechanical rotation, it has many advantages over conventional filer memories, but it cannot be said that it is necessarily advantageous at present in terms of economy. Therefore, in order to improve economic efficiency, current devices use elements that have partially defective parts to increase the reliability of the elements and reduce the overall cost of the device. Below, a conventional defective loop selection control method and its problems will be explained using a magnetic bubble memory device as an example.

Figure 1 shows a memory unit consisting of eight magnetic bubble chips, where 1 is a minor loop group that stores and transfers information, and 2 is a major loop that transfers bubbles for reading or writing information. , 5 is a detector for reading information, and 4 is a generator for storing information.

When a rotating magnetic field is applied to the chip, the information of the minor loop 1 and the major loop 2 performs synchronous rotation in the direction of the arrow in the figure. For example, when information at point A in the figure is read out, the information at point A moves on minor loop 1, transfers to major loop 2, then moves on major loop 2, and is read out by detector 3. Minor loop to major loop 2
The transition to is always performed for multiple pieces of information at the same position in each minor loop, and each piece of information is read out serially by the detector 3 in the order of the minor loop position. Multiple chips also rotate synchronously, and information at the same location on each chip is read out at the same timing. Also for write operations,
The basic operations are the same, except that the flow of data is the opposite of that for reading, and the writing timing is slightly different from the reading timing, so all of the following explanation will be based on reading operations. Now, at present, as mentioned above, magnetic bubble chips are often used with some defective parts still included.

If this defective part becomes a major loop, the chip cannot be used, but if it becomes a minor loop, only the corresponding minor loop becomes defective, and other minor loops and major loops can be used. Therefore, a preliminary minor loop is prepared in advance when making the chip. Here, it is assumed that 132 minor loops are prepared in one chip, 128 of which are actually used, and 4
The book is a preliminary loop. FIG. 4 shows the normal and defective states of the minor loops of each chip, with "0" marks indicating normal loops and "x" marks indicating defective loops. From FIG. 4, all of the minor loop numbers #0 of each chip are normal loops, so all information read at the same timing is valid, and this is set as the 0th byte. Regarding the minor loop number #1, since the chip numbered N02 is a defective loop, the chip numbered N02 assigns this information to the minor loop numbered #2. Therefore, as shown by the broken line in FIG. 4, NOO~NO1, N03
The first byte is composed of the minor loop number #1 of the chip of ~N07 and the minor loop number #2 of the chip of N02.
In this way, conventionally, information for a defective loop is assigned to a normal minor loop at the next timing within the same chip.

The hardware configuration in this case is shown in FIG. 2, and the control method is shown in FIGS. 5 and 6. In Fig. 2, 11i (i=0 to 7) is a magnetic bubble chip N○i, 12 is a read-only memory (ROM) that stores information indicating whether it is a normal loop or a bad loop for each minor loop, and 13i is a magnetic bubble chip N○i. Bubble chip (N○i) 4-bit shift register that adjusts the timing of information from 11i, 14i is shift register 13
A selector 15 for selecting the bit to be used from the 4 bits of i is a control signal generating circuit that controls the increment of each shift register 3i and the selection operation of the selector 14i.
The ROM 12 stores data shown in FIG.
The ROM bit positions in FIG. 5 correspond to the chip numbers in FIG. 4, and the addresses in the ROM correspond to the minor loop numbers in FIG. 4, with 0 indicating a normal loop and 1 indicating a defective loop. Now, each chip 11 in one period of the rotating magnetic field applied from the outside.

In steps 117 to 117, 1 bit of information is read out and transferred to the shift register 13. ~137. Therefore, first, due to the 4-cycle timing, the shift register 13i has a chip (N○
i) 4 bits of 11i, i.e. minor loop number #
Information of 0, #1, #2, and #3 is read out.

Shift register 13 at this point. The validity and invalidity of the information of 137 to 137 are shown in FIG. 6a. Here, "0" indicates a valid bit read from a normal loop, and "x" indicates an invalid bit read from a defective loop. The contents of the ROM 12 begin to be read out at the same timing as above. ROM1
The contents read from 2 are expanded by the control signal generation circuit 15, but the contents of the initial ROM address 0 are all 0, and at this time, all shift registers 13o to 13 are expanded.
The third bit of 137 is the selector 14. ~147, and this is sent to the external device as the 0th byte information. At the next timing, the shift register increments by 1 bit, resulting in the contents shown in FIG. 6b. At this timing, ROM
From 12 onwards, the contents of address 1 in the ROM (from 27 = 0,
0, 0, 0, 0, 1, 0, 0) is read out. This indicates that the minor loop of the magnetic bubble chip (N02) 112 is a defective loop, and is developed by the control signal generation circuit 15 and sent to the selectors 14o, 141, 143.
-7 selects the third bit of the corresponding shift register, while selector 142- selects the second bit.

Similarly, information read from the defective loop is skipped by the selector 14 based on the contents of the ROM 12, and information read from the normal loop is sequentially assigned. ZAs mentioned above, in the conventional method, when there is a defective loop, each bit that makes up the unit information (here, 8 bits = 1 byte) is read out from the magnetic bubble chip at different timings, so the number of bits equal to the number of preliminary minor loops is read out from the magnetic bubble chip. This has the drawback that the amount of metal required is enormous, such as the need to provide several shift registers Z. Furthermore, in the conventional method, a chip in which the number of defective loops is greater than the number of spare loops cannot be used, which causes a slowdown.
2. It is an object of the present invention to provide a defective loop selection control method that eliminates the above-mentioned drawbacks of the prior art, uses less metal, is easy to configure, and greatly relaxes chip use restrictions and improves chip speed. There is a particular thing.
2 In order to achieve the above object, the present invention provides a memory device consisting of a plurality of information loops of a shift register-like memory such as a magnetic bubble memory or a CCD, in which memory chips are provided in a number greater than the number of unit information bits, and each chip is It has a means for reading or writing the same loop information at the same timing, and an additional memory such as a read-only memory for storing whether the loop is a normal loop or a defective loop, and the normal loop is selected based on the information in the additional memory. It is something to do. Furthermore, if the number of normal loops read and written three times at the same timing is less than the number of unit information bits, the information is determined to be defective based on the contents of the additional memory, the information read at that timing is considered unused, and the information to be written is It is characterized by temporary matching. 4 Below, the content of the present invention will be explained in detail with reference to Examples. FIG. 7 shows an example of the use of the memory chip according to the present invention and the normal and defective states of the minor loop of each chip.

However, as in the previous conventional example, the unit information is 8 bits = 1
In the conventional example, the number of magnetic bubble chips was 8 chips corresponding to the number of unit information bits, but in the embodiment of the present invention, 10 chips are used. In other words, information is read or written from 10 chips at the same timing, but of the 10 bits corresponding to the 10 chips, 8 bits of the normal loop are used, and if the normal loop is less than 8 bits, the corresponding 10 bits are used. Don't use all the bits. This situation will be explained using FIG. 7. In FIG. 7, all of the 10 chips with minor loop number #0 are normal loops, and in this case, the minor loops of magnetic bubble chips NOO to N07 are numbered 0.
Part-time job.

Regarding the minor loop number #1, since the minor loop of magnetic bubble chip N02 is defective, the minor loops of magnetic bubble chips NO to NO1 and N03 to N08 are set as the first byte. Regarding the minor loop number #2, as in the case of the minor loop number #0, the minor loops from magnetic bubble chips NOO to N07 are used as the second byte. Regarding the minor loop number #3, the minor loops of magnetic bubble chips N05 to N07 are defective, and only seven normal loops remain. Therefore, all the minor loops at this timing are not used. Then, the 8 bits from the magnetic bubble chips NOO to N02 and N05 to NO9 obtained by the minor loop number #4 are set as the third byte. The specific hardware configuration and control method of the present invention are shown in FIGS. 3 and 8. In the following explanation, only the read operation will be described to simplify the explanation, but there is no major difference in the write operation except that the direction of data is reversed. In Figure 3, 21i = (i = 0 to 9) indicates the magnetic bubble chip NOi, 22 indicates whether it is a normal loop or a defective loop for each minor loop that is read and written at the same timing, and also indicates whether it is a normal loop or a defective loop corresponding to the minor loop group. A read-only memory (ROM) stores information indicating that the group is a defective loop; 23i is a selector for selecting a magnetic bubble chip having a normal loop; 24 is a selector for creating a selection signal for the selector 23i based on information in the ROM 22; Furthermore, a control signal generation circuit 25 generates a signal specifying a group of defective loops, and 25 is a defective byte display signal specifying the group of defective loops described above. The selector 23i has a chip (N○i)
Chips 21i+1 and 21i+ are installed outside the output information line of 21i.
2 output information lines are input. The data shown in FIG. 8 is stored in the ROM 22, and the address in the ROM is 7th.
Although it corresponds to the minor loop number shown in the figure, the ROM bit position differs from the conventional system and does not correspond to the chip number shown in FIG. 7, and is used as follows. If there is no defective loop among the 10 minor loops with the same minor loop number, 27 to 27 are all set to 1. 1 bad loop
If there is a loop, indicate the defective chip number in digits and press 27.
~ Pig is all 1. If there are two defective loops, indicate the respective defective chip numbers as 27~〆 and 〆~〆.
If the number of defective loops is 3 or more, set 27 to 1110.
1110 indicates that it is a bad byte. Now, a rotating magnetic field is applied to each chip and the minor loop number #
Each magnetic bubble chip 21 has 10 bits of 0.

-219. In this case, information at address 0 in the ROM is read out from the ROM 22 at the same time. The information at this time is all 1 indicating that the loop is normal, and each selector 23j opens the upper gate 23io of the 3-input select gates by the control signal generation circuit 24, and the magnetic bubble chips 21 of NOO to N07. The information from 217 to 217 is the 0th byte. Next, the minor lube number #1 is read out.

In this case, the information at address 1 in the ROM is read from the ROM 22, 23 to 20 are 0010 indicating the defective chip number #N02, 27 to 24 are all 1 indicating that there are no more defects, and the control signal By the creation circuit 15, the upper gates 23oo, 23, o of the three input gates and the selectors 232 to 23
7, the middle gates 232, 23 of the 3 input gates
7, and set the information of the magnetic bubble chips 22o, 221, 223 to 228 of NO0, NO1, N03 to N08 as the first byte. Next minor loop number #2
Regarding, as in the case of minor loop number #0, N
○o~N07 magnetic bubble chip 21. The information from 217 to 217 is the third byte. Next minor loop number #3
In this case, information 11101110 indicating that 27 to 2o are defective bytes is read from address 3 in the ROM, and the control signal generation circuit 24 closes all gates of each selector 23i and sends a defective byte display signal 25. Displays to the outside that the signal is invalid at the relevant timing. Then, the minor loop number # read out at the next timing
The 8-bit information consisting of 4 is assumed to be the third byte.
The same applies below. As explained above, according to the present invention,
Not only is there no timing difference between the bits constituting one byte as in the conventional system, but a shift register is no longer required, and hardware can be reduced significantly.

Furthermore, in the conventional method, a chip containing more than a predetermined number of defective minor loops in one chip could not be used at all, but with the method of the present invention, for example, 1 byte can be obtained by using 10 chips with 5 defective minor loops. Even if configured, 99.86% of chips can be used,
Therefore, the effect more than compensates for the addition of two chips for backup, and the overall economic efficiency is greatly improved.

[Brief Description of the Drawings] Fig. 1 is a memory unit section of a magnetic bubble memory device, Fig. 2 is a block diagram showing a conventional control method for a magnetic bubble memory device, and Fig. 3 is an implementation of a control method according to the present invention. A block diagram showing an example, FIG. 4 is a conceptual diagram showing a method for selecting a follower of a defective loop in a magnetic bubble memory device, and FIG. 5 is a diagram showing the contents of a ROM used in the method for selecting a defective loop in FIG. 4. , FIG. 6 is a diagram showing the contents of a shift register when the conventional method for selecting a defective loop is applied, and FIG. 7 is a conceptual diagram showing a method for selecting a defective loop in a magnetic bubble memory device when the present invention is applied. , FIG. 8 is a diagram showing the contents of a ROM used in the defective loop selection method of the present invention shown in FIG. 7. 21. ~219...Magnetic bubble chip, 22...Read-only memory, 23. ~237...Selector, 24.
...Control signal generation circuit, 25...Bad byte display signal. Ga 1 Ward Q O 2 Figures Sai 3 Figures Sai 4 Figures Katazu, Toru Figuresai 7 Figures Soup 8 Figures

Claims (1)

[Scope of Claims] 1. It has a plurality of memory chips each including a plurality of information loops of shift register-like memory, each one of the memory chips is designated, and a specific number of bits is assigned to the designated information loop group. In a memory control device that reads or writes a group of unit information bits consisting of a number of bits, an information loop group consisting of one information loop for each of the designated memory chips corresponds to a number of memory chips larger than the specific number of bits. an additional memory for storing information indicating the position of a defective information loop; and based on the information in the additional memory, information loops excluding the defective information loop from the correspondingly designated group of information loops are equal to the specified number of bits. 1. A memory control system, comprising a control means for selecting a specific number of information loops and reading or writing a group of bits serving as unit information for the specific number of information loops. 2. In the additional memory, information indicating whether or not the correspondingly specified information loop group is a defective information loop group is stored, and the information in the additional memory is used to mark the corresponding defective information loop group as unused. A memory control method according to claim 1, characterized in that: