CN111813619A - Loading switching device for large-capacity memory - Google Patents
Loading switching device for large-capacity memory Download PDFInfo
- Publication number
- CN111813619A CN111813619A CN202010522033.8A CN202010522033A CN111813619A CN 111813619 A CN111813619 A CN 111813619A CN 202010522033 A CN202010522033 A CN 202010522033A CN 111813619 A CN111813619 A CN 111813619A
- Authority
- CN
- China
- Prior art keywords
- fpga
- circuit
- trigger
- level
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 78
- 238000003860 storage Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000004590 computer program Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 16
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 4
- 102100031190 Prominin-2 Human genes 0.000 description 4
- 101710143063 Prominin-2 Proteins 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 2
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- -1 VCC2 Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A mass storage load switch device, comprising: the device comprises a controller, a level generator, a trigger and a chip selector; the controller is connected with the mass memories, the level generator, the trigger and the chip selector and is used for sending control signals to the mass memories, the trigger and the chip selector; the level generator is connected with the controller and the trigger and is used for generating at least two level signals with different levels to the trigger; the trigger is connected with the controller, the level generator and the chip selector and is used for sending a second level signal to the chip selector when receiving a first level signal sent by the level generator; the chip selector is connected with the controller, the trigger and the mass memories and used for converting the level signal sent by the trigger into a corresponding switching signal so as to switch a data channel of the controller from the currently loaded mass memory to the next mass memory.
Description
Technical Field
The invention relates to the field of memory testing, in particular to a large-capacity memory loading switching device.
Background
The FPGA (field programmable gate array) is widely applied to the field of control and calculation circuits, the current embedded development based on the embedded soft core of the FPGA reduces the complicated circuit design of a conventional processor and an applied circuit to a certain extent, and the single FPGA can realize the corresponding application circuit design under the condition of meeting the requirement. In practical application, especially for a multi-chip multi-bit wide mass memory, because the memory itself contains a plurality of chip selects or other control signals, only a single chip select and a single control signal can be operated based on an embedded IP core (intellectual property core) of the FPGA, so that the test of the similar memory based on the FPGA needs to be modified corresponding to the embedded IP. Since IP core-based modifications require some IP core design code capability and are not necessarily suitable for most designers.
A conventional single FPGA driving memory chip is characterized in that pins of the memory chip are connected to the FPGA, and the FPGA is embedded with an IP (Internet protocol) to test a single chip by a single core. However, in the test of a large-capacity SIP memory with multiple chip selects and multiple control signals based on the FPGA, a single IP core cannot meet the test requirement of the memory.
If the tested memory has multiple chip-select CS, 32-bit Data [0:31] and multiple control signals, the single IP core can not meet the test requirement, if the designer has no capability of modifying the IP, different test programs need to be programmed for testing for multiple times, and the test is inconvenient and unmanageable. Proper circuit design is required on hardware design, and the memory with multiple chip selection and multiple control signals can be tested by adopting a single embedded IP.
Disclosure of Invention
In view of this, the present invention provides a device for switching a load of a mass storage, a circuit for switching a load of a mass storage based on an FPGA, and a method for controlling the circuit for switching a load of a mass storage based on an FPGA.
First, the present invention provides a device for switching loading of mass storage, which is used for switching and controlling loading of a plurality of mass storage based on level change, and comprises: the device comprises a controller, a level generator, a trigger and a chip selector; wherein the content of the first and second substances,
the controller is connected with the mass memories, the level generator, the trigger and the chip selector and is used for sending control signals to the mass memories, the trigger and the chip selector;
the level generator is connected with the controller and the trigger and is used for generating at least two level signals with different levels to the trigger;
the trigger is connected with the controller, the level generator and the chip selector and is used for sending a second level signal to the chip selector when receiving a first level signal sent by the level generator;
the chip selector is connected with the controller, the trigger and the mass memories and used for converting the level signal sent by the trigger into a corresponding switching signal so as to switch a data channel of the controller from the mass memory loaded currently to the next mass memory.
Further, in the above device provided by the present invention, the chip selector is implemented by an electrical logic device, the controller is implemented by an FPGA, and the high-capacity memory is a PROM memory.
Further, in the above apparatus provided by the present invention, the electrical logic device performs a logic operation on the control signal sent by the controller and the trigger signal sent by the trigger.
Secondly, the invention provides a large-capacity memory loading switching circuit based on an FPGA, wherein the loading switching circuit controls the loading switching among a plurality of PROMs to be tested by using the FPGA, and the loading switching circuit comprises: a level setting circuit, a trigger circuit, and an OR gate circuit;
the level setting circuit is connected with the FPGA chip, the trigger circuit and the OR gate circuit and is used for generating at least two level signals with different levels to the trigger circuit;
the trigger circuit is connected with the FPGA chip, the level setting circuit and the OR gate circuit and is used for sending a second level signal to the switcher when receiving a first level signal sent by the level setting circuit;
the OR gate circuit is connected with the FPGA chip, the level setting circuit and the trigger circuit and is used for executing or processing the level signal sent by the trigger circuit and the chip selection signal sent by the FPGA chip so as to switch the data channel of the controller from the currently loaded memory to the next memory.
Further, in the above circuit proposed by the present invention, the FPGA includes at least a first GPIO interface, a second GPIO interface, and a third GPIO interface; wherein the content of the first and second substances,
the first GPIO interface generates a chip selection signal to an OR gate circuit to select a PROM memory, and stops generating the chip selection signal when the FPGA starts to load a PROM;
after the FPGA finishes program loading of a memory, the second GPIO interface generates a reloading signal so that the first GPIO interface generates a chip selection signal again;
and the third GPIO interface is connected with the trigger circuit, and after the FPGA finishes the program loading of a PROM, the third GPIO interface sends an output overturning signal to the trigger circuit so as to overturn the output of the trigger circuit.
Further, in the above circuit proposed by the present invention, the flip-flop circuit includes a D flip-flop, a CLK port of the D flip-flop is connected to the third GPIO interface, and when the third GPIO interface sends an output inversion signal to the CLK port of the D flip-flop, an output signal of an output port Q and an output port # Q of the D flip-flop are inverted.
Further, in the above circuit proposed by the present invention, the level setting circuit includes: a plurality of resistors, one or more capacitors, and a plurality of supply voltage sources; wherein the content of the first and second substances,
one of the resistors, one of the one or more capacitors and a power supply voltage source form a charging circuit, and the charging circuit sets initial levels for an output port Q and an output port # Q of the D flip-flop; and the number of the first and second electrodes,
the one or more voltage supply sources are connected to one or more GPIO interfaces of the FPGA through one or more resistors and set initial levels for the one or more GPIO interfaces.
Further, the present invention provides the above circuit, wherein the or gate circuit includes at least a first or gate and a second or gate, wherein,
one input port of the first or gate is connected with a Q output port of the D flip-flop, the other input port of the first or gate is connected with the first GPIO interface and one input port of the second or gate, and the output port of the first or gate is connected with a mass storage;
one input end of the second OR gate is connected with a # Q output port of the D flip-flop, the other input port of the second OR gate is connected with one input port of the first OR gate, and the output port of the second OR gate is connected with a PROM memory.
The invention further provides a control method of the loading switching circuit of the high-capacity memory based on the FPGA, which comprises the following steps:
A. setting an initial channel relationship for a chip selector, wherein the channel relationship corresponds to a data channel of a large-capacity memory;
B. after receiving a chip selection signal sent by the FPGA, the chip selector switches a data channel to a corresponding large-capacity memory by applying the channel relation, and the FPGA starts to load a program on the selected large capacity and stops generating the chip selection signal;
C. and after the program loading of one mass storage is finished, changing the channel relation of the chip selector to correspond to the data channel of the other mass storage, generating a reloading signal and generating a chip selection signal again by the FPGA, and executing the step B.
Finally, the invention proposes a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method described above.
The beneficial results of the invention are: the device, the circuit and the method provided by the invention can be used for switching among a plurality of PROMs in sequence, and the chip selection logic after switching is fixed. And then, the FPGA reloading mechanism is triggered to load the program from the selected PROM to carry out corresponding test without modifying the IP core of the FPGA, thereby reducing the test difficulty.
Drawings
FIG. 1 is a schematic diagram of an IP core of an FPGA to check out signals;
FIG. 2 is a block diagram of a first embodiment of a load switch device for mass storage according to the present invention;
fig. 3 is a circuit diagram showing a second embodiment of the load switching circuit for the FPGA-based mass storage according to the present invention;
fig. 4 is a flowchart illustrating a third embodiment of a control method for loading a switching circuit in an FPGA-based mass storage according to the present invention;
fig. 5 is a flowchart illustrating a fourth embodiment of a control method for loading a switching circuit in an FPGA-based mass storage according to the present invention.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The same reference numbers will be used throughout the drawings to refer to the same or like parts.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, the descriptions of upper, lower, left, right, etc. used in this application are only relative to the positional relationship of the various elements of the application with respect to one another in the drawings. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The exemplary embodiments described herein and depicted in the drawings should not be considered limiting. Various mechanical, compositional, structural, electrical, and operational changes, including equivalents, may be made without departing from the scope of this disclosure and the claims. In some instances, well-known structures and techniques have not been shown or described in detail to avoid obscuring the disclosure. The same reference numbers in two or more drawings identify the same or similar elements. Moreover, elements and their associated features, which are described in detail with reference to one embodiment, may be included in other embodiments, where they are not specifically shown or described, where practicable. For example, if an element is described in detail with reference to one embodiment and not described with reference to the second embodiment, it may also be claimed to be included in the second embodiment.
Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" depending on the context.
In an embodiment of the invention, the method steps may be performed in another order. The invention is not limited to the order in which the method steps are performed.
Referring to the schematic diagram of the IP core external signal of the FPGA shown in fig. 1, the external interface of the FPGA with a single IP core is shown in the figure, which indicates that the FPGA has one chip selection signal output interface CS, a Data output interface with 8 bits or 16 bits, and one control signal output interface, and obviously, for a tested memory with multiple chip selection CS signals, 32 bits Data [0:31], and multiple control signals, the single IP core cannot meet the test requirement, and the IP needs to be modified, if a designer does not have the capability of modifying the IP, different test degrees need to be programmed into the memory for multiple times, which greatly affects the efficiency.
Referring to a block diagram of a first embodiment of a load switching device for a mass storage according to the present invention shown in fig. 2, in order to solve the above technical problem, in an embodiment of the present invention, a load switching device for a mass storage is provided for performing switching control on loads of a plurality of mass storages based on a change in level, including: the device comprises a controller, a level generator, a trigger and a chip selector; the controller is connected with the mass memories, the level generator, the trigger and the chip selector and is used for sending control signals to the mass memories, the trigger and the chip selector; the level generator is connected with the controller and the trigger and is used for generating at least two level signals with different levels to the trigger; the trigger is connected with the controller, the level generator and the chip selector and is used for sending a second level signal to the chip selector when receiving a first level signal sent by the level generator; the chip selector is connected with the controller, the trigger and the mass memories and used for converting the level signal sent by the trigger into a corresponding switching signal so as to switch a data channel of the controller from the mass memory loaded currently to the next mass memory.
Preferably, in one embodiment of the present invention, the chip selector is implemented by an electric logic device, the controller is implemented by an FPGA, and the mass storage includes, but is not limited to, a PROM (programmable read only memory) memory. Specifically, the mass storage may be other memories without departing from the spirit of the present invention, and the present invention aims to provide switching of data channels for testing the mass storage with a single-IP FPGA, without limiting the type of the memory, without limiting the memory to be mass storage, and without limiting the controller to be FPGA, and in fact, the device proposed by the present invention may be applied to load switching as long as the number of data output bits of the controller is less than the number of data bits of the memory, or the number of chip selection data output channels of the controller is less than the number of chip selection data channels of the memory.
Further, in the above apparatus provided by the present invention, the electrical logic device performs a logic operation on the control signal sent by the controller and the trigger signal sent by the trigger. Preferably, in an embodiment of the present invention, the electrical logic device is an or gate, and the logic operation is an or operation.
Further, in an embodiment of the present invention, an FPGA-based bulk memory load switching circuit is provided, where the load switching circuit controls load switching between a plurality of PROMs to be tested using an FPGA, and includes: a level setting circuit, a trigger circuit, and an OR gate circuit; the level setting circuit is connected with the FPGA chip, the trigger circuit and the OR gate circuit and is used for generating at least two level signals with different levels to the trigger circuit; the trigger circuit is connected with the FPGA chip, the level setting circuit and the OR gate circuit and is used for sending a second level signal to the switcher when receiving a first level signal sent by the level setting circuit; the OR gate circuit is connected with the FPGA chip, the level setting circuit and the trigger circuit and is used for executing or processing the level signal sent by the trigger circuit and the chip selection signal sent by the FPGA chip so as to switch the data channel of the controller from the currently loaded memory to the next memory.
Further, in an embodiment of the present invention, the FPGA includes at least a first GPIO interface, a second GPIO interface, and a third GPIO interface; the first GPIO interface generates a chip selection signal to an OR gate circuit to select a PROM memory, and stops generating the chip selection signal when the FPGA starts to load a PROM; after the FPGA finishes program loading of a memory, the second GPIO interface generates a reloading signal so that the first GPIO interface generates a chip selection signal again; and the third GPIO interface is connected with the trigger circuit, and after the FPGA finishes the program loading of a PROM, the third GPIO interface sends an output overturning signal to the trigger circuit so as to overturn the output of the trigger circuit.
Further, in one embodiment of the present invention, the flip-flop circuit includes a D flip-flop whose CLK port is connected to the third GPIO interface, and whose output signal of output port Q and output port # Q is inverted when the third GPIO interface sends an output inversion signal to the CLK port of the D flip-flop.
Further, in one embodiment of the present invention, the level setting circuit includes: a plurality of resistors, one or more capacitors, and a plurality of supply voltage sources; one of the resistors, one of the one or more capacitors and a power supply voltage source form a charging circuit, and the charging circuit sets initial levels for an output port Q and an output port # Q of the D flip-flop; and the one or more voltage supply sources are respectively connected to one or more GPIO interfaces of the FPGA through one or more resistors, and initial levels are set for the one or more GPIO interfaces.
Further, in an embodiment of the present invention, the or gate circuit includes at least a first or gate and a second or gate, where one input port of the first or gate is connected to the Q output port of the D flip-flop, another input port of the first or gate is connected to the first GPIO interface and one input port of the second or gate, and an output port of the first or gate is connected to a mass storage; one input end of the second OR gate is connected with a # Q output port of the D flip-flop, the other input port of the second OR gate is connected with one input port of the first OR gate, and the output port of the second OR gate is connected with a PROM memory.
Preferably, referring to the circuit diagram of the second embodiment of the FPGA-based bulk memory load switching circuit according to the present invention as shown in fig. 3, there are shown 1 FPGA, 2 OR gates (OR1 and OR2), two PROM memories (PROM-1 and PROM-2), one D flip-flop, 4 resistors (R1, R2, R3, R4), 1 capacitor C1, and 3 VCCs (VCC1, VCC2, VCC 3). The FPGA used comprises five GPIO interfaces, namely GPIO (# PROM _ CS), GPIO (# PROG _ B), GPIO (R), GPIO (CLK) and GPIO (D), wherein the GPIO (# PROM _ CS) interfaces are respectively connected with one of two input ports of each of OR1 and OR2 and send chip selection instructions; the other input port of the OR1 is connected with the Q output port of the D flip-flop, the other input port of the OR2 is connected with the # Q output port of the D flip-flop, and the output ports of the OR1 and the OR2 are respectively connected with PROM-1 and PROM-2; a GPIO (R) port is connected with a GPIO (# PROG _ B) port and is connected to a # PRE input port of the D flip-flop through R3 and VCC 3; the GPIO (CLK) port is connected with the CLK input port of the D flip-flop through a resistor R2 and is pulled down to the ground through a resistor R2; the GPIO (D) port is connected with the D input port of the D trigger and is pulled up to VCC1 through a resistor R1; the # CLR input port of the D flip-flop is connected with a charging circuit consisting of VCC2, C1 and R4, wherein one end of C1 is grounded.
Preferably, referring to the flowchart of the third embodiment of the control method for loading the switching circuit of the FPGA-based mass storage according to the present invention shown in fig. 4; in this embodiment, the implementation steps of the proposed control method are as follows:
1. resistor R3 sets FPGA GPIO (# PROG _ B) to high during power-up.
2. Resistor R1 sets the FPGA GPIO (D) signal to a high level and resistor R2 sets the FPGA GPIO (CLK) signal to a low level during power-up. The flip-flop # PRE signal is set to high and the flip-flop # CLR signal makes a transition from low to high through the RC charging circuit consisting of R4 and C1. So that the flip-flop output Q is low and # Q is high.
3. During power-on, the FPGA outputs a # PROM _ CS chip selection signal, and the chip selection # CS1 is in low level and the chip selection # CS2 is in high level through two OR gates, so that program loading is carried out on the selected PROM-1.
4. After the program loading is finished, the FPGA executes a corresponding program function, and at the moment, the # PROM _ CS signal is released and set to be in a high level. At this time, two PROM chip selections are all high level through two OR gates, and any PROM is not selected.
5. After the program is loaded, the FPGA GPIO needs to output a GPIO (CLK) signal as low level, a GPIO (D) signal as high level and a GPIO (# PROG _ B) signal as high level.
6. After the program loading is completed, the flip-flop # PRE is at a high level, # CLR is at a high level, # CLK is at a low level, and D is at a high level, so that the flip-flop output is held in the previous state (# Q is at a high level, and Q is at a low level).
And 7, after the PROM-1 program is executed, switching chip selection # CS2 to reload, wherein the signal output of FPGA GPIO (CLK) is low level- > high level- > low level, and a rising jump action is completed. Flip-flop # PRE is high, # CLR high, D high, and there is a rising transition of CLK such that the flip-flop output is # Q low and Q high. Specifically, the flip-flop truth table and the chip select output truth table are shown in tables 1 and 2 below.
TABLE 1 trigger truth table
TABLE 2 truth table for chip select output
Note:
1, X: either state; h: a high level; l: low level.
2.×) c: a rising edge.
And 8, the FPGA GPIO (# PROG _ B) outputs low level, and the FPGA enters a reloading state.
And 9, during the FPGA reloading period, the FPGA outputs a PROM chip selection signal # PROM _ CS, and the output of the trigger keeps the previous state (# Q is low level and Q is high level) because the signal of the trigger # PRE is high level, the signal of the trigger # CLR is high level, the signal of the CLK is low level and the signal of the D is high level. The # PROM _ CS signal, the # Q signal and the Q signal pass through an OR gate, the output chip selection # CS1 is in a high level, and the # CS2 is in a low level, so that PROM-2 is selected to be loaded.
10. After the PROM-2 is loaded, the FPGA releases the # PROM _ CS signal, and the FPGA executes the functional program. The method comprises the steps of controlling the GPIO level state setting, wherein a GPIO (# PROG _ B) signal is in a high level, a GPIO (CLK) signal is in a low level, and a GPIO (D) signal is in a high level.
11. The method realizes that different test programs are programmed in the two PROMs to finish the test of the large-capacity memory with single IP for checking multiple chip selections and control signals.
Referring to fig. 5, a flowchart of a fourth embodiment of a control method for loading a switching circuit in a bulk storage based on an FPGA according to the present invention includes the following steps:
A. setting an initial channel relationship for a chip selector, wherein the channel relationship corresponds to a data channel of a large-capacity memory;
B. after receiving a chip selection signal sent by the FPGA, the chip selector switches a data channel to a corresponding large-capacity memory by applying the channel relation, and the FPGA starts to load a program on the selected large capacity and stops generating the chip selection signal;
C. and after the program loading of one mass storage is finished, changing the channel relation of the chip selector to correspond to the data channel of the other mass storage, generating a reloading signal and generating a chip selection signal again by the FPGA, and executing the step B.
Finally, in an embodiment of the invention, a computer-readable storage medium is proposed, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method described above.
It should be recognized that embodiments of the present invention can be realized and implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with the computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner, according to the methods and figures described in the detailed description. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
Embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the invention. Variations of those described embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the embodiments of the disclosure to be practiced otherwise than as specifically described herein. Accordingly, the scope of the present disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, the scope of the present disclosure encompasses any combination of the above-described elements in all possible variations thereof unless otherwise indicated herein or otherwise clearly contradicted by context.
While the present invention has been described in considerable detail and with particular reference to a few illustrative embodiments thereof, it is not intended to be limited to any such details or embodiments or any particular embodiments, but it is to be construed as effectively covering the intended scope of the invention by providing a broad, potential interpretation of such claims in view of the prior art with reference to the appended claims. Furthermore, the foregoing describes the invention in terms of embodiments foreseen by the inventor for which an enabling description was available, notwithstanding that insubstantial modifications of the invention, not presently foreseen, may nonetheless represent equivalent modifications thereto.
The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. However, it will be apparent that: various modifications and changes may be made thereto without departing from the broader spirit and scope of the application as set forth in the claims.
Other variations are within the spirit of the present application. Accordingly, while the disclosed technology is susceptible to various modifications and alternative constructions, certain embodiments thereof have been shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the application to the specific form or forms disclosed; on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the application, as defined in the appended claims.
Claims (10)
1. A mass storage load switching apparatus for switching control of loading of a plurality of mass storages based on a change in level, comprising: the device comprises a controller, a level generator, a trigger and a chip selector; wherein the content of the first and second substances,
the controller is connected with the mass memories, the level generator, the trigger and the chip selector and is used for sending control signals to the mass memories, the trigger and the chip selector;
the level generator is connected with the controller and the trigger and is used for generating at least two level signals with different levels to the trigger;
the trigger is connected with the controller, the level generator and the chip selector and is used for sending a second level signal to the chip selector when receiving a first level signal sent by the level generator;
the chip selector is connected with the controller, the trigger and the mass memories and used for converting the level signal sent by the trigger into a corresponding switching signal so as to switch a data channel of the controller from the mass memory loaded currently to the next mass memory.
2. The device as claimed in claim 1, wherein the chip selector is implemented by an electrical logic device, the controller is implemented by an FPGA, and the mass storage is a PROM memory.
3. The device as claimed in claim 2, wherein the electrical logic device performs logic operations on the control signal sent by the controller and the trigger signal sent by the trigger.
4. An FPGA-based mass storage load switching circuit that controls load switching between a plurality of mass storage devices to be tested using an FPGA, comprising: a level setting circuit, a trigger circuit, and an OR gate circuit;
the level setting circuit is connected with the FPGA chip, the trigger circuit and the OR gate circuit and is used for generating at least two level signals with different levels to the trigger circuit;
the trigger circuit is connected with the FPGA chip, the level setting circuit and the OR gate circuit and is used for sending a second level signal to the switcher when receiving a first level signal sent by the level setting circuit;
the OR gate circuit is connected with the FPGA chip, the level setting circuit and the trigger circuit and is used for executing or processing the level signal sent by the trigger circuit and the chip selection signal sent by the FPGA chip so as to switch the data channel of the controller from the currently loaded memory to the next memory.
5. The FPGA-based mass memory load switch circuit of claim 4, wherein the FPGA comprises at least a first GPIO interface, a second GPIO interface and a third GPIO interface; wherein the content of the first and second substances,
the first GPIO interface generates a chip selection signal to an OR gate circuit to select a PROM memory, and stops generating the chip selection signal when the FPGA starts to load a PROM;
after the FPGA finishes the program loading of a PROM, the second GPIO interface generates a reloading signal so that the first GPIO interface generates a chip selection signal again;
and the third GPIO interface is connected with the trigger circuit, and after the FPGA finishes the program loading of a memory, the third GPIO interface sends an output overturning signal to the trigger circuit so as to overturn the output of the trigger circuit.
6. The FPGA-based mass memory load switch circuit of claim 5, wherein the flip-flop circuit comprises a D flip-flop having a CLK port connected to the third GPIO interface, and wherein when the third GPIO interface sends an output toggle signal to the CLK port of the D flip-flop, the output signal of output port Q and output port # Q of the D flip-flop toggles.
7. The FPGA-based mass memory load switch circuit of claim 6, wherein the level setting circuit comprises: a plurality of resistors, one or more capacitors, and a plurality of supply voltage sources; wherein the content of the first and second substances,
one of the resistors, one of the one or more capacitors and a power supply voltage source form a charging circuit, and the charging circuit sets initial levels for an output port Q and an output port # Q of the D flip-flop; and the number of the first and second electrodes,
the one or more voltage supply sources are connected to one or more GPIO interfaces of the FPGA through one or more resistors and set initial levels for the one or more GPIO interfaces.
8. The FPGA-based mass memory load switching circuit of claim 7, wherein the OR-gate circuit comprises at least a first OR-gate and a second OR-gate, wherein,
one input port of the first OR gate is connected with a Q output port of the D flip-flop, the other input port of the first OR gate is connected with the first GPIO interface and one input port of the second OR gate, and the output port of the first OR gate is connected with a PROM memory;
one input end of the second OR gate is connected with a # Q output port of the D flip-flop, the other input port of the second OR gate is connected with one input port of the first OR gate, and the output port of the second OR gate is connected with a memory.
9. A control method for loading a switching circuit of a large-capacity memory based on an FPGA is characterized by comprising the following steps:
A. setting an initial channel relationship for a chip selector, wherein the channel relationship corresponds to a data channel of a large-capacity memory;
B. after receiving a chip selection signal sent by the FPGA, the chip selector switches a data channel to a corresponding large-capacity memory by applying the channel relation, and the FPGA starts to load a program on the selected large capacity and stops generating the chip selection signal;
C. and after finishing loading a large-capacity program, changing the channel relation of the chip selector to correspond to a data channel of another large-capacity memory, generating a reloading signal and generating a chip selection signal again by the FPGA, and executing the step B.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program realizes the steps of the method as claimed in claim 9 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010522033.8A CN111813619A (en) | 2020-06-10 | 2020-06-10 | Loading switching device for large-capacity memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010522033.8A CN111813619A (en) | 2020-06-10 | 2020-06-10 | Loading switching device for large-capacity memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111813619A true CN111813619A (en) | 2020-10-23 |
Family
ID=72845753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010522033.8A Pending CN111813619A (en) | 2020-06-10 | 2020-06-10 | Loading switching device for large-capacity memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111813619A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113010233A (en) * | 2021-04-15 | 2021-06-22 | 天津讯联科技有限公司 | FPGA multi-backup program loading method and device suitable for commercial satellite |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129926A (en) * | 1977-04-20 | 1978-11-13 | Hitachi Ltd | Memory control system |
| CN1567208A (en) * | 2003-06-14 | 2005-01-19 | 中兴通讯股份有限公司 | Processor system and method using multi memory of start-up procedure |
| US20100192000A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus |
| CN104965168A (en) * | 2015-07-23 | 2015-10-07 | 北京华峰测控技术有限公司 | FPGA configuration system and method for testing of integrated circuit |
| CN204789920U (en) * | 2015-07-23 | 2015-11-18 | 北京华峰测控技术有限公司 | A FPGA disposes system for integrated circuit test |
-
2020
- 2020-06-10 CN CN202010522033.8A patent/CN111813619A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129926A (en) * | 1977-04-20 | 1978-11-13 | Hitachi Ltd | Memory control system |
| CN1567208A (en) * | 2003-06-14 | 2005-01-19 | 中兴通讯股份有限公司 | Processor system and method using multi memory of start-up procedure |
| US20100192000A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus |
| CN104965168A (en) * | 2015-07-23 | 2015-10-07 | 北京华峰测控技术有限公司 | FPGA configuration system and method for testing of integrated circuit |
| CN204789920U (en) * | 2015-07-23 | 2015-11-18 | 北京华峰测控技术有限公司 | A FPGA disposes system for integrated circuit test |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113010233A (en) * | 2021-04-15 | 2021-06-22 | 天津讯联科技有限公司 | FPGA multi-backup program loading method and device suitable for commercial satellite |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100433686B1 (en) | Memory, programming method and program circuit for memory | |
| CN1905068B (en) | Non-volatile memory device having improved programming speed and associated programming method | |
| US7500148B2 (en) | Test apparatus and testing method | |
| US8572361B2 (en) | Configuration of a multilevel flash memory device | |
| JP2006510332A (en) | Reconfiguring programmable logic in integrated circuits. | |
| US7626861B1 (en) | Employing unused configuration memory cells as scratchpad memory | |
| US7313730B1 (en) | Configuration logic for embedded software | |
| KR0143361B1 (en) | Semiconductor memory device executing a memory test in a plurality test modes | |
| EP0084247A2 (en) | Operation mode setting circuitry for microprocessor | |
| US6553523B1 (en) | System and method for verifying configuration of a programmable logic device | |
| CN111813619A (en) | Loading switching device for large-capacity memory | |
| CN101076866B (en) | System and method for collocating integrate circuit | |
| EP0420388A2 (en) | Test latch circuit | |
| US8780666B2 (en) | Decoupling capacitance calibration devices and methods for DRAM | |
| US7463060B1 (en) | Programmable logic device and method of testing | |
| CN112015490A (en) | Method, apparatus and medium for programmable device implementing and testing reduced instruction set | |
| US20040088621A1 (en) | Built-in self-test circuit | |
| US7535253B1 (en) | Register data retention systems and methods during reprogramming of programmable logic devices | |
| GB2520506A (en) | Partial Scan Cell | |
| US7739566B2 (en) | Scan test circuitry using a state machine and a limited number of dedicated pins | |
| US6680871B1 (en) | Method and apparatus for testing memory embedded in mask-programmable logic device | |
| CN114662429A (en) | Non-destructive read back and write back for integrated circuit devices | |
| US6870383B2 (en) | Semiconductor device with high speed switching of test modes | |
| CN218634117U (en) | Memory circuit and image sensor | |
| Subhashini et al. | Design and analysis of multiple port memory architecture for low power applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201023 |
|
| RJ01 | Rejection of invention patent application after publication |