JPS59208655A - Information processor - Google Patents

Abstract

PURPOSE:To perform rerise processing quickly at the time of system down and to shorten average restoration time by controlling shifting operation so that the same shift data can be shifted in simultaneously. CONSTITUTION:When editing data included in the shift data are to be edited, data transfer from an editing data memory 2 to a shift data memory 1 is executed under control by a firmware. Namely, a shift control circuit 3 controls a device selecting circuit 9 so as to send the shift data simultneously to both logical devices 100, 200 by a device selecting signal on a signal line 30. Subsequently, the same data are shifted in simultaneously by using a shift bus circuit 10. Thus, a register is initialized simultaneously to both devices 100, 200. Since the same shift data can be shifted in simultaneously, the rerise processing at the time of system down can be rapidly executed and the average restoration time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus in which initial setting information, diagnostic information, etc. are written using a shift pass.

(Prior Art) Conventionally, in this type of information processing apparatus, the same information has been individually set for a plurality of logical devices to which initial setting information and diagnostic information are written using a shift pass. For this reason, it takes a very long time to restart the system when it goes down, and the average recovery time becomes long.

(Objective of the Invention) An object of the present invention is to write a plurality of logical devices to which initial setting information, diagnostic information, etc. are written using a shift path.
The above drawbacks are solved by controlling the shift operation so that the same shift data can be shifted in at the same time.
An object of the present invention is to provide an information processing device that quickly performs restart processing when a system goes down and shortens the average repair time.

(Structure of the Invention) The information processing device according to the present invention is of a type that can write initial setting information, diagnostic information, etc. to a plurality of logical devices that perform data processing on a shift bus, With shift data memory.

It is equipped with an address register, a shift bus circuit, a device selection circuit, and a shift control circuit.

The shift data memory is for storing shift data, and the address register is for specifying the address of the shift data memory. The shift path circuit is for shifting the contents of the shift data memory into multiple logic devices. The device selection circuit is for selecting a shift path circuit connected to one or more of the plurality of logic devices.

The shift control circuit is for controlling a shift operation so that the contents of the shift data memory can be shifted in by enabling the shift path circuit for one or more logic devices selected by the device selection circuit.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 for explaining an example of the operation of the main parts of the information processing device according to the present invention, a register 300 is a register to which initial setting information must be written, and its contents include shift in package A configured by ULSI. It is assumed that the data consists of part 2 and part 0 of the data, and part 0 of the shift data in package B configured by an LSI. Here, when the shift data of packages A and B are shifted out (So) to the shift data memory 1, 11-1. ．． Desired data is set in the ■, ■, and ■ sections on the shift-out data memory, respectively, and the data on the shift-out memory is shifted into package A and package B. Due to this, data is written to the register 300.

Next, an embodiment of an information processing apparatus according to the present invention is shown in FIG. In FIG. 2, a shift data memory 1 for storing shift data in an information processing device, an editing data memory 2 for storing editing data included in the shift data, a shift data memory 1 and editing data. memory 2
A shift address register 5 for instructing the respective storage addresses of the shift data memory 1, the write data of the editing data memory 2, and the read data of the pieta memory 2 from bit serial format to byte parallel format. A shift register 4 for conversion, a shift counter 6 for counting the number of shifts in the shift register 4, and a shift register 4 for writing data to the shift register 4.
Eaves/first selection circuit 7 for selection and package A
, B with the same configuration including logical devices 100 and 200,
Shift counter from both packages AjB,
Alternatively, a second selection circuit 8 for selecting the output data from the shift register 4 and a shift path circuit 10 from the shift data memory 1 to the logic devices 100 and 200 are provided.
, and a device selection circuit 9 for simultaneously shifting in the same data, and a shift control circuit 3 for controlling the shift operation.

■, ■, ■ of the contents of the register 300 consist of flip-flops of a bit, b bit, and C bit, respectively,
It is assumed that the shift data memory 1 has addresses m, n, and t, respectively.

During editing, data is transferred from the editing data memory 2 to the shift data memory 1 under the control of firmware. When initial setting data is set in the register 300, the firmware stores the contents of packages A and B from the second selection circuit 8 to the shift data memory 1 via a shift path. Next, the contents (1), (2), and (2) set in the register 300 are stored and searched in the shift register 4 via the first selection circuit 7.

Therefore, the shift counter 61C (a+b+c)
is counted, O is set in the shift address register 5, and the shift control circuit 3 is activated to transfer from the shift azide register 4 to the editing data memory 2. The shift control circuit 3 converts the contents of the shift register 4 from the byte parallel format to the bit serial format, and transfers the contents to the editing data memory 2 one bit at a time according to the address specified by the shift address register 4. Each time one bit is transferred, the contents of the shift address register 5 are incremented by one and updated, but at the same time, the contents of the shift counter 6 are decremented by one until the contents of the shift counter 6 reach O. be done. In this case, data for initializing the register 300 can be stored in the editing data memory 2. Next, the data from the editing data memory 2 is stored in the shift data memory 1 by the firmware. First, the data of part (■) is transferred from the editing data memory 2 to the shift register 4. Therefore, 0 is set in the shift address register 5, a is set in the shift counter 6, and a transfer command from the editing data memory 2 to the shift register 4 is sent to the shift control circuit 3. The shift control circuit 3 sends out the contents of the editing data memory 2 from the address specified by the shift address register 5, converts the data from the bit serial format to the byte parallel format one bit at a time, and stores it in the shift register 4. At this time, each time one bit is transferred, the contents of the shift address register 5 are incremented by one and updated, and the contents of the shift counter 6 are decremented and updated by one until the contents of the shift counter 6 reach 0. be done. After this operation is completed, the shift register 300 stores the 0 part data. Next, in order to transfer the data of part ■ from the shift register 4 to the shift data memory 1,
The firmware sets m in the shift address register 5, sets a in the shift counter 6, and sends a transfer command from the shift register 4 to the shift data memory 1 to the shift control circuit 3.

The shift control circuit 3 converts the contents of the shift register 4 from the byte parallel format to the pit serial format Ki.
On the other hand, one pixel is transferred to the shift data memory 1 according to the address specified by the shift address register 5. At this time, each time one bit is transferred, the contents of the shift address register 5 are incremented by 1 and updated, and the contents of the shift counter 6 are decremented by 1 and updated.
The transfer continues until the contents of the shift counter 6 reach 0. As a result, the data in part 0 of the shift register 4 is stored in the desired position of the shift data memory 1. Next, using the same procedure, edit data memory 2
The data of the 0th part and the 0th part are stored in the desired position of the shift data memory 1. As a result, the data ■, ■, ■ to be initialized in the register 300 are stored in the desired positions on the shift data in the packages A and H on the shift data memory 1.

Finally, the firmware adds each logical device 100
, 200 is instructed to shift data from the shift data memory 1 into the shift control circuit 3 via the shift path.

The device selection signal on the shift control circuit 3 signal line 30 controls the device selection circuit 9 to simultaneously send shift data to both logic devices 100 and 200, and uses the shift path circuit 10 to simultaneously send out the same data. Shift in data. As a result, the registers 300 are simultaneously initialized for the logic devices 100 and 200.

(Effects of the Invention) As explained above, the present invention uses a shift path for multiple logical devices by controlling the shift operation so that the same data can be shifted into multiple logical devices at the same time. If you need to initialize the
The system startup time can be shortened, and the average recovery time can be shortened by quickly performing restart processing when the system goes down.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating an example of the operation of main parts of an information processing apparatus according to the present invention. FIG. 2 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. 1...Shift data memory 2-...Editing data memory 3...Shift control circuit 4...Shift register 5...Shift address register 6...Shift counter 7.8...Selection circuit 9 ...Device selection circuit 10...Shift path circuit 100,200, @Switch logic device 300...Register 30...Device selection signal line Patent applicant: NEC Corporation Representative, Patent attorney Hisashi Inoro

Claims (1)

[Claims] In an information processing device configured to be able to write initial setting information, diagnostic information, etc. using a shift path to a plurality of logical devices that perform data processing, a shift data memory for storing shift data; an address register for instructing the address of the shift data memory; a shift path circuit for shifting the contents of the shift data memory into the plurality of logic devices; and one or more of the plurality of logic devices. a device selection circuit for selecting a shift path circuit connected to a logic device; and a device selection circuit for enabling the shift path circuit corresponding to one or more logic devices selected by the device selection circuit to select the shift data memory. What is claimed is: 1. An information processing apparatus comprising: a shift control circuit for controlling a shift operation so that the contents of the information processing apparatus can be shifted in;