JPS60156159A - 磁気バブルメモリ装置 - Google Patents

磁気バブルメモリ装置

Info

Publication number
JPS60156159A
JPS60156159A JP59010180A JP1018084A JPS60156159A JP S60156159 A JPS60156159 A JP S60156159A JP 59010180 A JP59010180 A JP 59010180A JP 1018084 A JP1018084 A JP 1018084A JP S60156159 A JPS60156159 A JP S60156159A
Authority
JP
Japan
Prior art keywords
data
signal
memory device
bubble memory
magnetic bubble
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59010180A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0544755B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Takayanagi
博 高柳
Kazutoshi Yoshida
和俊 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59010180A priority Critical patent/JPS60156159A/ja
Publication of JPS60156159A publication Critical patent/JPS60156159A/ja
Publication of JPH0544755B2 publication Critical patent/JPH0544755B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP59010180A 1984-01-25 1984-01-25 磁気バブルメモリ装置 Granted JPS60156159A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59010180A JPS60156159A (ja) 1984-01-25 1984-01-25 磁気バブルメモリ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59010180A JPS60156159A (ja) 1984-01-25 1984-01-25 磁気バブルメモリ装置

Publications (2)

Publication Number Publication Date
JPS60156159A true JPS60156159A (ja) 1985-08-16
JPH0544755B2 JPH0544755B2 (enrdf_load_stackoverflow) 1993-07-07

Family

ID=11743084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59010180A Granted JPS60156159A (ja) 1984-01-25 1984-01-25 磁気バブルメモリ装置

Country Status (1)

Country Link
JP (1) JPS60156159A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008013209A1 (fr) * 2006-07-28 2008-01-31 Nec Corporation Circuit de connexion de processeur, dispositif de traitement de données, dispositif opérationnel, et terminal de communications mobiles, et procédé de transfert de données les utilisant

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106642A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Data transfer unit
JPS5654560A (en) * 1979-10-12 1981-05-14 Nippon Telegr & Teleph Corp <Ntt> Memory system
JPS56101261A (en) * 1980-01-16 1981-08-13 Mitsubishi Electric Corp Disc device
JPS5837740A (ja) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> バツフアメモリ制御方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106642A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Data transfer unit
JPS5654560A (en) * 1979-10-12 1981-05-14 Nippon Telegr & Teleph Corp <Ntt> Memory system
JPS56101261A (en) * 1980-01-16 1981-08-13 Mitsubishi Electric Corp Disc device
JPS5837740A (ja) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> バツフアメモリ制御方式

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008013209A1 (fr) * 2006-07-28 2008-01-31 Nec Corporation Circuit de connexion de processeur, dispositif de traitement de données, dispositif opérationnel, et terminal de communications mobiles, et procédé de transfert de données les utilisant
JPWO2008013209A1 (ja) * 2006-07-28 2009-12-17 日本電気株式会社 Ｃｐｕ接続回路、データ処理装置、演算装置及びこれらを用いた携帯通信端末並びにデータ転送方法
US8355326B2 (en) 2006-07-28 2013-01-15 Nec Corporation CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer method
JP5168144B2 (ja) * 2006-07-28 2013-03-21 日本電気株式会社 Ｃｐｕ接続回路、データ処理装置、演算装置及びこれらを用いた携帯通信端末並びにデータ転送方法

Also Published As

Publication number Publication date
JPH0544755B2 (enrdf_load_stackoverflow) 1993-07-07

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