JPS60142458A - アドレス判定方式 - Google Patents

アドレス判定方式

Info

Publication number
JPS60142458A
JPS60142458A JP25002783A JP25002783A JPS60142458A JP S60142458 A JPS60142458 A JP S60142458A JP 25002783 A JP25002783 A JP 25002783A JP 25002783 A JP25002783 A JP 25002783A JP S60142458 A JPS60142458 A JP S60142458A
Authority
JP
Japan
Prior art keywords
address
local storage
input
interface
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25002783A
Other languages
English (en)
Japanese (ja)
Other versions
JPS638501B2 (enrdf_load_stackoverflow
Inventor
Akio Hanazawa
花沢　章夫
Taiho Higuchi
樋口　大奉
Hideaki Chiba
秀章 千葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25002783A priority Critical patent/JPS60142458A/ja
Publication of JPS60142458A publication Critical patent/JPS60142458A/ja
Publication of JPS638501B2 publication Critical patent/JPS638501B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP25002783A 1983-12-28 1983-12-28 アドレス判定方式 Granted JPS60142458A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25002783A JPS60142458A (ja) 1983-12-28 1983-12-28 アドレス判定方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25002783A JPS60142458A (ja) 1983-12-28 1983-12-28 アドレス判定方式

Publications (2)

Publication Number Publication Date
JPS60142458A true JPS60142458A (ja) 1985-07-27
JPS638501B2 JPS638501B2 (enrdf_load_stackoverflow) 1988-02-23

Family

ID=17201744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25002783A Granted JPS60142458A (ja) 1983-12-28 1983-12-28 アドレス判定方式

Country Status (1)

Country Link
JP (1) JPS60142458A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0337702U (enrdf_load_stackoverflow) * 1989-08-23 1991-04-11

Also Published As

Publication number Publication date
JPS638501B2 (enrdf_load_stackoverflow) 1988-02-23

Similar Documents

Publication Publication Date Title
CN106227683A (zh) 电子设备及信息处理方法
JPS63116258A (ja) デ−タ処理システム
JPS60142458A (ja) アドレス判定方式
EP0067519B1 (en) Telecommunications system
JPS6242306B2 (enrdf_load_stackoverflow)
US6711658B2 (en) Architecture and configuring method for a computer expansion board
KR920010977B1 (ko) 개선된 성능의 메모리 버스 아키텍쳐(memory bus architecture)
WO1998015877A1 (en) Universal operator station module for a distributed process control system
JP3079956B2 (ja) プリンタ
JPH11184761A (ja) リードモディファイライト制御システム
JP2841432B2 (ja) データ転送装置
KR900009212Y1 (ko) 어드레스 제어장치
JPH0430059B2 (enrdf_load_stackoverflow)
KR940003845B1 (ko) 하위레벨 프로세서의 통화로계 버스 선택방법
JPH01240938A (ja) データリードバック方法
JPS58139234A (ja) 信号入力方式
KR0171772B1 (ko) 입출력 디바이스보드의 식별방법
JP4174272B2 (ja) デバイス制御装置
JPS622344A (ja) 情報伝達装置
JP2968636B2 (ja) マイクロコンピュータ
JPH0816405A (ja) システム初期化装置
JPS58181134A (ja) デ−タ転送回路
JPH02135560A (ja) アドレスの割付方法
JPS622337A (ja) メモリ拡張方式
JPH0329021A (ja) プリンタサーバ