JPS60117753A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS60117753A
JPS60117753A JP22571883A JP22571883A JPS60117753A JP S60117753 A JPS60117753 A JP S60117753A JP 22571883 A JP22571883 A JP 22571883A JP 22571883 A JP22571883 A JP 22571883A JP S60117753 A JPS60117753 A JP S60117753A
Authority
JP
Japan
Prior art keywords
film
spacer
etching
insulating film
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22571883A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0550138B2 (enrdf_load_stackoverflow
Inventor
Yasushi Sakui
康司 作井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22571883A priority Critical patent/JPS60117753A/ja
Publication of JPS60117753A publication Critical patent/JPS60117753A/ja
Publication of JPH0550138B2 publication Critical patent/JPH0550138B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP22571883A 1983-11-30 1983-11-30 半導体装置の製造方法 Granted JPS60117753A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22571883A JPS60117753A (ja) 1983-11-30 1983-11-30 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22571883A JPS60117753A (ja) 1983-11-30 1983-11-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60117753A true JPS60117753A (ja) 1985-06-25
JPH0550138B2 JPH0550138B2 (enrdf_load_stackoverflow) 1993-07-28

Family

ID=16833720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22571883A Granted JPS60117753A (ja) 1983-11-30 1983-11-30 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60117753A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876216A (en) * 1988-03-07 1989-10-24 Applied Micro Circuits Corporation Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers
US5122473A (en) * 1989-10-24 1992-06-16 Sgs-Thomson Microelectronics S.R.L. Process for forming a field isolation structure and gate structures in integrated misfet devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876216A (en) * 1988-03-07 1989-10-24 Applied Micro Circuits Corporation Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices
US5122473A (en) * 1989-10-24 1992-06-16 Sgs-Thomson Microelectronics S.R.L. Process for forming a field isolation structure and gate structures in integrated misfet devices
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers

Also Published As

Publication number Publication date
JPH0550138B2 (enrdf_load_stackoverflow) 1993-07-28

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