JPS60117671A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60117671A
JPS60117671A JP22560683A JP22560683A JPS60117671A JP S60117671 A JPS60117671 A JP S60117671A JP 22560683 A JP22560683 A JP 22560683A JP 22560683 A JP22560683 A JP 22560683A JP S60117671 A JPS60117671 A JP S60117671A
Authority
JP
Japan
Prior art keywords
lift
film
insulating film
electrodes
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22560683A
Other languages
Japanese (ja)
Inventor
Nobuyuki Kajiwara
梶原 信之
Toru Maekawa
前川 通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22560683A priority Critical patent/JPS60117671A/en
Publication of JPS60117671A publication Critical patent/JPS60117671A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823406Combination of charge coupled devices, i.e. CCD, or BBD

Abstract

PURPOSE:To enable to perform the formation of patterns without using an etching process and to form another electrodes or wirings on the same plane as electrodes or wirngs having been formed earlier after a lift-off method was applied for removing metal layers, photo resists and insulating films by a method wherein the electrodes or wirings having been formed earlier and insulating films, which are formed on the electrodes or wirings, are respectively formed using lift-off films as a mask respectively. CONSTITUTION:An insulating film 2, a photo resist (lift-off film) 8 and a metal layer (lift-off film) 9 are formed on a semiconductor substrate 1. Apertures 10 are provided on the metal layer 9, and further-more apertures 11 wider than the apertures 10 are provided on the photo resist 8 and electrodes 3 are formed on the insulating film 2 using the metal layers 9 as a mask respectively. The metal layers 9 and the metal layers 3 thereon are removed by a lift-off method and interlayer insulating films 4 are formed on the electrodes 3 using the photo resists 8 as a mask respectively. After the photo resists 8 and the insulating films 4 thereon were removed by a lift-off method, an electrode 6 and an insulating film 7 are fomred. As an etching process is not used, such troubles as a stain of an etching liquid appears and a uniformity of etching is bad don't arise. As a result, a charge transfer device having superior characteristics can be realized.

Description

【発明の詳細な説明】 (11発明の対象 本発明は半導体基板上に絶縁膜を介して同一平面上に複
数の電極または配線を有する半導体装置の製造方法に係
り、特に電荷転送装置(CCD)および電荷注入装置(
CI D)等の製造に用いて有効な方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (11) Object of the Invention The present invention relates to a method for manufacturing a semiconductor device having a plurality of electrodes or wirings on the same plane on a semiconductor substrate via an insulating film, and particularly relates to a method for manufacturing a semiconductor device having a plurality of electrodes or wirings on the same plane through an insulating film on a semiconductor substrate. and charge injection device (
This invention relates to an effective method for producing CI D) and the like.

(2)従来技術と問題点 電荷転送装置は複数電極からなり、電極下の半導体基板
中にポテンシャル井戸を形成し、該ポテンシャル井戸の
深さを周期的に変化させることにより電荷の転送を行な
う装置である。この電荷転送装置においては各電極を同
一平面上に配置し、どの電極でも同一の電位にしたとき
、同−深さのポテンシャル井戸が形成されるようにする
方法が考えられている。このようにすれば、各電極の電
位設定が容易であり、かつ、それぞれの電極の電位を操
作して、確実で安定した電荷転送が行なえる。そこで次
に同一平面上に複数の電極を形成する従来方法について
述べる。
(2) Prior art and problems A charge transfer device is a device that consists of multiple electrodes, forms potential wells in a semiconductor substrate under the electrodes, and transfers charges by periodically changing the depth of the potential wells. It is. In this charge transfer device, a method has been considered in which each electrode is arranged on the same plane, and when all electrodes are set to the same potential, a potential well of the same depth is formed. In this way, it is easy to set the potential of each electrode, and reliable and stable charge transfer can be performed by manipulating the potential of each electrode. Next, a conventional method of forming a plurality of electrodes on the same plane will be described.

第1図(a)に示す如く半導体基板1」二に絶縁膜2を
形成し、同図(blに示すように第1の電極3を形成し
た後、同図(C)の如(絶縁膜4を形成し、エツチング
により同図(dlのように絶縁膜4を部分的に除去し、
開孔5を設ける。次に同図(C)の如く、第2の電極6
を形成し、同図([1のように絶縁膜7を形成して、第
1,2の電極3,6を同一平面上に複数形成する。ここ
で半導体基板1がシリコンからなる場合は、一般に電極
3.6をポリシリコンで、絶縁膜4を熱酸化膜で形成す
る。この熱酸化膜をエツチングし、電極6を形成すると
き、該電極6にエツチング液が付くと汚染され特性劣化
を生じる。また、半導体基板1に化合物半導体基板を用
いた場合は、電極3,6を金属2例えば、Au G e
 / A u等で、絶縁11灸4を真空蒸着、スパッタ
リング、CVD等による蒸着膜で形成する。この蒸着膜
のエツチングによるパターニングにおいては、パターン
上へのエツチング液のしみ込みが生じたり、エツチング
の均一性が悪いという欠点があった。
After forming an insulating film 2 on a semiconductor substrate 1''2 as shown in FIG. 1(a) and forming a first electrode 3 as shown in FIG. 4 is formed, and the insulating film 4 is partially removed by etching as shown in the figure (dl).
An opening 5 is provided. Next, as shown in the same figure (C), the second electrode 6
is formed, and the insulating film 7 is formed as shown in FIG. Generally, the electrodes 3.6 are made of polysilicon and the insulating film 4 is made of a thermal oxide film.When etching this thermal oxide film to form the electrode 6, if the electrode 6 gets contaminated with etching liquid, it will be contaminated and the characteristics will deteriorate. In addition, when a compound semiconductor substrate is used as the semiconductor substrate 1, the electrodes 3 and 6 are made of a metal 2, for example, Au Ge
/ Au, etc., and the insulation 11 and the moxibustion 4 are formed by a vapor deposition film by vacuum evaporation, sputtering, CVD, etc. This patterning of a deposited film by etching has disadvantages in that the etching solution may seep onto the pattern and the etching uniformity is poor.

(3) 発明の目的 本発明の目的は、電極または配線と、その上に形成する
絶縁膜のそれぞれをリフトオフ膜をマスクとして形成す
ることで、電極または配線上の絶縁膜をエツチングしな
くともパターン形成が行なえ、リフトオフ後、前記電極
または配線と同一平面上に別の電極または配線を形成で
きる方法を提供するにある。
(3) Purpose of the Invention The purpose of the present invention is to form an electrode or wiring and an insulating film formed thereon using a lift-off film as a mask, thereby forming a pattern without etching the insulating film on the electrode or wiring. The object of the present invention is to provide a method in which another electrode or wiring can be formed on the same plane as the electrode or wiring after lift-off.

(4)発明の構成 上記の目的は、本発明Gこよれば、第1の絶縁膜を形成
した半導体基板上に第1のリフトオフ膜を形成する工程
、前記第1のリフトオフ膜上に前記第1のリフトオフ膜
とは種類の異なる第2のリフトオフ膜を形成した後、該
第2のリフトオフ膜を部分的に除去して第2の開孔部を
設ける工程、前記第2の開孔部の第1のリフトオフ映部
分を除去し、前記第2の開花部より広い第1の開孔部を
設けて前記第1の絶縁膜を露出させる工程、前記第1.
2のリフトオフ膜とは異なる第1の導電l丙を前記第2
のリフトオフ膜をマスクとして前記絶縁股上に形成する
工程、前記第2のリフトオフ)吹およびその膜上の第1
の導電層をリフトオフ法により除去する工程、前記第1
のリフ1−オフ法をマスクとして前記第1の導電層上に
第2の絶縁膜を形成する工程、前記第1のりフトオフ映
およびその膜上の第2の絶縁膜をリフトオフ法により除
去し、第1の絶縁膜を露出させる工程、第1の絶縁膜の
露出部分に第2の導電層を形成する工程を具備してなる
ことにより達成される。
(4) Structure of the Invention According to the present invention, a step of forming a first lift-off film on a semiconductor substrate on which a first insulating film is formed; forming a second lift-off film different in type from the first lift-off film, and then partially removing the second lift-off film to provide a second opening; removing the first lift-off mirror portion and providing a first opening wider than the second flowering portion to expose the first insulating film;
The first conductive layer different from the second lift-off film is
forming a lift-off film on the insulating crotch as a mask;
a step of removing the conductive layer by a lift-off method;
forming a second insulating film on the first conductive layer using the lift-off method as a mask; removing the first lift-off film and the second insulating film on the film by a lift-off method; This is achieved by comprising the steps of exposing the first insulating film and forming a second conductive layer on the exposed portion of the first insulating film.

(5)発明の実施例 第2図乃至第8図は、本発明一実施例を説明するための
工程要所における半導体装置の側断面図であり、これ等
の図を参照しつつ記述する。
(5) Embodiment of the Invention FIGS. 2 to 8 are side sectional views of a semiconductor device at important points in the process for explaining an embodiment of the present invention, and the description will be made with reference to these figures.

本発明の方法で電荷転送装置の複数電極を同一平面上に
形成するには、先づ図第2図に示す如く、例えばP形シ
リコンからなる半導体基板1上に例えば二酸化シリコン
からなる絶縁膜2を厚さ例えば1000人程形成し、フ
第1・レジスト8を厚さ例えばlμrn程塗布した後1
例えばアルミニウムからなる金属層9を厚さ例えば30
00人程形成する。
In order to form a plurality of electrodes of a charge transfer device on the same plane using the method of the present invention, first, as shown in FIG. After forming the first resist 8 to a thickness of, for example, 1 μrn,
For example, the metal layer 9 made of aluminum has a thickness of, for example, 30 mm.
Approximately 00 people will be formed.

次に第3図に示す如く金属層9を部分的に除去して開孔
lOを設ける。さらに同一部分においてフォトレジスト
8を除去して金属層9の開孔10より広い開孔部11を
設け、絶縁膜2を露出さ−Uる。
Next, as shown in FIG. 3, the metal layer 9 is partially removed to form an opening 1O. Further, the photoresist 8 is removed from the same portion to provide an opening 11 wider than the opening 10 of the metal layer 9, and the insulating film 2 is exposed.

次に第4図の如く、例えばA u G e / A u
からなる金属層3を厚さ例えば1000人程蒸着法。
Next, as shown in Fig. 4, for example, A u G e / A u
The metal layer 3 is deposited to a thickness of, for example, about 1,000 layers.

スパッタまたはCVD法により堆積させ、前記金属層9
をマスクとして絶縁膜2上に電極3を形成する。ここで
、金属層をマスクとするので精度の良い電極が形成でき
る。
The metal layer 9 is deposited by sputtering or CVD.
An electrode 3 is formed on the insulating film 2 using as a mask. Here, since the metal layer is used as a mask, highly accurate electrodes can be formed.

金属層9および金属層9上の金属層3をリフ1−オフ法
にて、除去し、第5図の如く、例えば二酸化シリコンか
らなる絶縁膜4を厚さ例えば2000人程蒸着により堆
積させ、フォトレジスト8をマスクとして、電極3上に
層間絶縁膜4を形成する。ここで、フォトレジストの開
孔11を金属層9の開孔10より広くしておいたので電
極3が層間絶縁膜4によりほぼ完全に覆われる。
The metal layer 9 and the metal layer 3 on the metal layer 9 are removed by a riff 1-off method, and as shown in FIG. 5, an insulating film 4 made of silicon dioxide is deposited to a thickness of about 2000 by evaporation, as shown in FIG. Interlayer insulating film 4 is formed on electrode 3 using photoresist 8 as a mask. Here, since the opening 11 in the photoresist is made wider than the opening 10 in the metal layer 9, the electrode 3 is almost completely covered by the interlayer insulating film 4.

第6図に示す如く、マスクとして使用したフ第1・レジ
スト8およびこのフ第1・レジスト8上の絶縁膜4をリ
フトオフ法にて除去して、絶縁膜2を露出させる。
As shown in FIG. 6, the first resist 8 used as a mask and the insulating film 4 on the first resist 8 are removed by a lift-off method to expose the insulating film 2.

そして第7図、第8図の如く、電極3と動作の異なる電
極6および絶縁膜7を形成する。したがって、電極3と
電極6が同一平面上に形成でき、それぞれの電極が同一
電位のとき、同−深さのポテンシャル井戸が形成される
ので、各電極の電゛位設定が容易であり、かつ、それぞ
れの電極の電位を操作して確実で安定した電荷転送が行
なえる。
Then, as shown in FIGS. 7 and 8, an electrode 6 and an insulating film 7, which operate differently from the electrode 3, are formed. Therefore, electrode 3 and electrode 6 can be formed on the same plane, and when each electrode has the same potential, potential wells of the same depth are formed, so it is easy to set the potential of each electrode. , reliable and stable charge transfer can be performed by manipulating the potential of each electrode.

さらに、絶縁膜2上の電極3および絶縁膜4を金属層9
.フォトレジスト8のリフトオフ膜をマスクとして、形
成し、フォトレジスト8のリフトオフによりエツチング
を行なわずに電極6を形成するために絶縁1ii!2を
露出できるので、エツチングを使用した場合のエツチン
グ液のじみが生じたり、エツチングの均一性が悪いとい
う問題がなく、良好な特性の電荷転送装置が得られる。
Further, the electrode 3 and the insulating film 4 on the insulating film 2 are replaced with a metal layer 9.
.. The insulation 1ii! is formed using the lift-off film of the photoresist 8 as a mask, and the electrode 6 is formed by lift-off of the photoresist 8 without etching. 2 can be exposed, so there is no problem of bleeding of etching solution or poor etching uniformity when etching is used, and a charge transfer device with good characteristics can be obtained.

なお、本実施例においては電荷転送装置について述べた
が、本発明は電荷転送装置に限定されるものではなく、
電荷転送装置以外の複数電極または配線を有する半導体
装置においても用いることができる。また、半導体基板
として化合物半導体基板を用いても効果がある。
Note that although a charge transfer device has been described in this embodiment, the present invention is not limited to charge transfer devices;
It can also be used in semiconductor devices having multiple electrodes or wiring other than charge transfer devices. Further, it is also effective to use a compound semiconductor substrate as the semiconductor substrate.

(6)発明の効果 本発明によれば半導体基板上に絶縁膜を介して複数電極
または配線を形成するときに、一部の電極または配線お
よびその上に形成する眉間絶縁膜のそれぞれをリフトオ
フ膜をマスクとして形成し、リフトオフを行なうことで
エツチング液程なしに絶縁膜上を露出させ、前記電極ま
たは配線と同一平面上に別の電極または配線が形成でき
るのでエツチングによるエツチング液のしみ込みが生じ
たりエツチングの均一性が悪いという問題がなく、良好
な特性の半導体装置が得られる。
(6) Effects of the Invention According to the present invention, when forming a plurality of electrodes or wirings on a semiconductor substrate via an insulating film, each of some of the electrodes or wirings and the glabella insulating film formed thereon is removed using a lift-off film. By forming a mask as a mask and performing lift-off, the top of the insulating film is exposed without using an etching solution, and another electrode or wiring can be formed on the same plane as the electrode or wiring, so that the etching solution will not seep in due to etching. There is no problem of poor etching uniformity, and a semiconductor device with good characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明するための工程要所における電荷
転送装置の側断面図、第2図乃至第8図は本発明−実施
例を説明するための工程要所Gこおける電荷転送装置の
側IJJi面図である。 図において、1は半導体基板、2,4.7は絶縁膜(二
酸化シリコン)、3.6は導電層、5゜10.11は開
孔、8.9はリフトオフ119である。 草 1 図 芥 6 口
FIG. 1 is a side cross-sectional view of a charge transfer device at a key process point for explaining a conventional example, and FIGS. 2 to 8 are a side sectional view of a charge transfer device at a key process point G for explaining the present invention-embodiment. It is a side IJJi view of . In the figure, 1 is a semiconductor substrate, 2 and 4.7 are insulating films (silicon dioxide), 3.6 is a conductive layer, 5° 10.11 is an opening, and 8.9 is a lift-off 119. Grass 1 Illustration 6 Mouth

Claims (1)

【特許請求の範囲】[Claims] 第1の絶縁膜を形成した半導体基板上に第1のリフトオ
フ膜を形成する工程、前記第1のリフトオフ膜上に前記
第1のリフトオフ1模とは種類の異なる第2のリフトオ
フ膜を形成した後、該第2のリフトオフ膜を部分的に除
去して第2の開孔部を設ける工程、前記第2の開孔部の
第1のリフトオフ膜部分を除去し、前記第2の開孔部よ
り広い第1の開孔部を設けて前記第1の絶縁膜を露出さ
せる工程、前記第1. 2のリフトオフ膜とは異なる第
1の導電層を前記第2のリフトオフ膜をマスクとして前
記絶縁膜上に形成する工程、前記第2のリフトオフ膜お
よびその股上の第1の導電層をリフトオフ法により除去
する工程、前記第1のリフトオフ膜をマスクとして前記
第1の導電層上に第2の絶縁膜を形成する工程、前記第
1のリフトオフ膜およびその膜上の第2の絶縁膜をリフ
トオフ法により除去し、第1の絶縁膜を露出させる工程
、第1の絶縁膜の露出部分に第2の導電層を形成する工
程を具備してなることを特徴とする半導体装置の製造方
法。
forming a first lift-off film on the semiconductor substrate on which the first insulating film has been formed, a second lift-off film different in type from the first lift-off pattern 1 on the first lift-off film; After that, a step of partially removing the second lift-off film to form a second aperture, removing a portion of the first lift-off film of the second aperture, and forming the second aperture. a step of exposing the first insulating film by providing a wider first opening; forming a first conductive layer different from the second lift-off film on the insulating film using the second lift-off film as a mask; forming the second lift-off film and the first conductive layer on its crotch by a lift-off method; removing the first lift-off film, forming a second insulating film on the first conductive layer using the first lift-off film as a mask, and removing the first lift-off film and the second insulating film thereon by a lift-off method. 1. A method of manufacturing a semiconductor device, comprising the steps of: removing the first insulating film by removing the first insulating film to expose the first insulating film; and forming a second conductive layer on the exposed portion of the first insulating film.
JP22560683A 1983-11-30 1983-11-30 Manufacture of semiconductor device Pending JPS60117671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22560683A JPS60117671A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22560683A JPS60117671A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60117671A true JPS60117671A (en) 1985-06-25

Family

ID=16831956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22560683A Pending JPS60117671A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60117671A (en)

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