JPS5885547A - Forming method for conductive pattern - Google Patents
Forming method for conductive patternInfo
- Publication number
- JPS5885547A JPS5885547A JP18324181A JP18324181A JPS5885547A JP S5885547 A JPS5885547 A JP S5885547A JP 18324181 A JP18324181 A JP 18324181A JP 18324181 A JP18324181 A JP 18324181A JP S5885547 A JPS5885547 A JP S5885547A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- substrate
- forming
- length
- turn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
本発明は微細な導電・千ターン、特に金属配線を形成す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming fine conductive wires, particularly metal wires.
従来より第1図〜第3図に示すように、いわゆる゛°リ
フトオフ法”を利用して基板上に微細・母ターンを有す
る電極金属層を形成する方法が知られている。すなわち
基板I上に例えばボッ形フォトレジスト・母ターン2を
通常の写眞蝕刻法により形成する(第1図)。次に真空
蒸着法により配線用電極金属層3をレジストパターン2
を含む基板1表面に形成する(第2図)。その後、レノ
スト・母ターン2を溶解除去し得る溶剤を用いて、レジ
ストパターン2を除去するとV)ストノ+ターン2上の
金属1傷3もレジストパターン2と共に同時に除去され
る。その結果第3図に示すように、所望の・リーンを有
する配線金属層3が基板1上に形成される。このような
従来の方法を実施することにより得られる良好な配線金
属!−影形成歩留りはレノストパターン2を容易r(除
去し得るか否かにががっている。As shown in FIGS. 1 to 3, there is a conventionally known method of forming an electrode metal layer having fine master turns on a substrate by using the so-called "lift-off method". For example, a boss-shaped photoresist/mother turn 2 is formed on the photoresist pattern 2 by a normal photolithography method (Fig. 1).Next, a wiring electrode metal layer 3 is formed on the resist pattern 2 by a vacuum evaporation method.
(FIG. 2). Thereafter, when the resist pattern 2 is removed using a solvent capable of dissolving and removing the renost/main turn 2, the metal 1 scratch 3 on the ston/main turn 2 is also removed together with the resist pattern 2. As a result, as shown in FIG. 3, a wiring metal layer 3 having a desired leanness is formed on the substrate 1. Good wiring metal obtained by implementing such a conventional method! -The shadow formation yield depends on whether the Lennost pattern 2 can be easily removed.
レジスト・母ターン2を容易に除去するためには、レノ
ストパターン2の端部が配線金唄「尚3の形成後に、露
出するか又は配線金属層3によって巧く被覆されている
状搏にあることが必要である。そのためにはレノストの
膜厚と配線金属の膜厚との相対比に制限があり一般的に
は前者を後者の約3倍以−ヒにしなければ信頼性の高い
配線金属・2ターンの形成は困難である。レノスト膜を
厚く形成すれは膜厚の厚い電極配線の形成が可能となる
が、レジスト膜厚の増大は一般にレノスト像の解像力を
低下させる。一方、配線制購膜の厚さを薄くした場合に
は、基板上に段差が存在すると、いわゆる金属膜の”段
切れ”が発生する。In order to easily remove the resist/main turn 2, the edges of the resist pattern 2 must be left exposed or well covered by the wiring metal layer 3 after the formation of the wiring metal layer 3. To achieve this, there is a limit to the relative ratio between the thickness of the Lennost film and the thickness of the wiring metal, and in general, the former must be approximately three times greater than the latter to ensure reliable wiring. It is difficult to form two turns of metal.If the Lennost film is formed thickly, it becomes possible to form a thick electrode wiring, but an increase in the resist film thickness generally reduces the resolution of the Lennost image. When the thickness of the metal film is reduced, if a step exists on the substrate, so-called "step breakage" occurs in the metal film.
本発明の目的は充分な膜厚を有する導電パターンを確実
に形成することのできる方法を提供することである。An object of the present invention is to provide a method that can reliably form a conductive pattern having a sufficient thickness.
上記目的を達成することのできる本発明の導電・2ター
ンの形成方法は基板上に上面の長さが下面の長さよりも
蜆かい断面略台形状の第1の物質より成る@1の・母タ
ーンを形成する工程;上記第1の・々ターンを含む基板
表面に第2の物I瓜より成る層を形成する工程;上記第
2の物質より成る1悩を上記第1の・ぞターンの上面が
6出する深さまで除去する工程;上記第1の・母ターン
を除去しこれ((よって上面の長さが下面の長さよりも
長い断面略逆台形1ノコの第2の物質より成る第2の・
ぞターンを基板上に残置させる工程;上記第217)
zRパターン含む基板表面に導電性物質を第2の・ぞタ
ーンの厚さよりも薄<1i覆する工程;上記第2の・ぞ
ターンおよびこの上の導11工性物・改を同時に除去し
、これによって基板上に導電性自縄から成る第3の・や
ターンを残置させる工程を具備することを特徴とする。The method for forming a conductive two-turn structure of the present invention which can achieve the above object is to form a conductive double-turn structure on a substrate using a first material having a substantially trapezoidal cross section in which the length of the upper surface is longer than the length of the lower surface. forming a layer of a second substance on the surface of the substrate including the first turns; forming a layer of a second substance on the surface of the substrate including the first turns; Step of removing the first main turn to a depth where the upper surface protrudes; 2.
Step of leaving the turn on the substrate; 217th above)
A step of covering the surface of the substrate including the zR pattern with a conductive substance thinner than the thickness of the second groove; simultaneously removing the second groove and the conductive material thereon; The present invention is characterized in that it includes a step of leaving a third turn made of conductive rope on the substrate.
以下に本発明の一実施例を第4図〜第1O図に基づいて
説明する。An embodiment of the present invention will be described below with reference to FIGS. 4 to 1O.
基板1ノ上にポジ形フォトレジスト膜(東京応化社商品
名oFpRs 00 )を1.0μmの厚さに回転塗布
法により形成し、約90°0に加熱して溶剤を蒸発させ
、ついで通常の写眞蝕刻法により上記レノスト膜を選択
的に除去して、ポジ形しジストノ(ターン12を形成す
る(第4図)。A positive photoresist film (Tokyo Ohka Co., Ltd. product name: oFpRs 00) is formed on the substrate 1 to a thickness of 1.0 μm by spin coating, heated to approximately 90°0 to evaporate the solvent, and then subjected to conventional coating. The above film is selectively removed by photolithography to form a positive pattern (turns 12) (FIG. 4).
次にポジレジストパターン12を140〜160℃の温
度で10〜20分加熱すると、ポルシスト・母ターン1
2は熱的変形を起して、上面の長さが下面の長さよりも
短かい断面略台形状のポジレジスト・ぐターン12Aを
形成する(第5図)。ポルシスト・量ターン12kを含
む基板11表面にネガ形フォトレジスト膜J3(東京応
化社商品名OMR−83)を2.0μmの厚さに回転塗
布法により形成する(第6図)。Next, when the positive resist pattern 12 is heated at a temperature of 140 to 160°C for 10 to 20 minutes, the positive resist pattern 12 is
2 is thermally deformed to form a positive resist pattern 12A having a substantially trapezoidal cross section in which the length of the upper surface is shorter than the length of the lower surface (FIG. 5). A negative photoresist film J3 (trade name: OMR-83, manufactured by Tokyo Ohka Co., Ltd.) is formed on the surface of the substrate 11 including the porcyst turns 12k to a thickness of 2.0 μm by spin coating (FIG. 6).
この場合、第6図から明らかのようにポジレジスト・ザ
ターン12A上に位置するネガレジスト吟13の厚さは
基板11上に位置するネガレジスト膜13の厚さよりも
必然的に薄くなる。In this case, as is clear from FIG. 6, the thickness of the negative resist film 13 located on the positive resist layer 12A is necessarily thinner than the thickness of the negative resist film 13 located on the substrate 11.
次に1.t?ポジレジスト平ターフ12にの上面が完全
に露出するまでネガレジスト膜13の全面エツチングを
酸素プラズマにより実施する。その結果、ネガレノスト
膜13の厚さはIゾレジスト・fターン12人の膜厚と
ほぼ同一となり、=5−
上面の長さが下面の長さよりも長い断面略逆台形状のネ
がレゾスト・母ターン13kが形成される(第7図)。Next 1. T? The entire surface of the negative resist film 13 is etched using oxygen plasma until the upper surface of the positive resist flat turf 12 is completely exposed. As a result, the thickness of the negative resist film 13 is almost the same as the film thickness of the I sole resist f-turn 12, and = 5 - the negative resist film 13 has a substantially inverted trapezoidal cross section in which the length of the upper surface is longer than the length of the lower surface. A turn 13k is formed (FIG. 7).
次にポジレジストパターンJ、?Aに対し溶解性を示し
、ネガレノスト・母ターン13Aに対し非溶解性を示す
溶剤、例えばアセトンを用いてポルシスト) t4ター
ン121Lを完全に溶解除去し断面略逆台形状のネガレ
ジストノeターン13kを基板11上に残置させる(第
8図)。次に80℃で10分間加熱し、アセトンを蒸発
させる。この温度では略逆台形状のネガレジス) ノ4
ターン13には変形せずに元の形状を保つことができる
。その後ネガレジストパターン13Aを含む基板11表
面に配線用金属5例えばAtを蒸着法によりネガレジス
ト・母ターン13Aの厚さよりも薄く、例えば約0.8
μm厚に堆積して配線金属層14を形成する(第9図)
。Next, positive resist pattern J,? Using a solvent (for example, acetone) that shows solubility in A and non-solubility in the negative resist/mother turn 13A, the T4 turn 121L is completely dissolved and removed, and a negative resist No. 11 (Figure 8). Next, heat at 80° C. for 10 minutes to evaporate acetone. At this temperature, the negative resist is approximately inverted trapezoidal) No. 4
The turn 13 can maintain its original shape without being deformed. Thereafter, a wiring metal 5, for example, At, is deposited on the surface of the substrate 11 including the negative resist pattern 13A by vapor deposition to make the wiring metal 5 thinner than the thickness of the negative resist/mother turn 13A, for example, about 0.8
The wiring metal layer 14 is formed by depositing it to a thickness of μm (Fig. 9).
.
第91mより明らかのように、ネガレジスト・母ターフ
131Lの側面には配線金属が付着し難いため、ネがレ
ゾス) ノfターン13人上面に堆積している盆属1−
14と基板11上面に堆積してい一武 −
る金属層14とは分離しており、したがって次の工程に
おいて、ネガレジスト・ぐターン13にと共にこの上に
形成されている金属1−14を除去する作業は極めて容
易に実施される。最後にレジスト剥離液(OMR剥離液
東京応化社製商品名)を用いてネガレジストパターン1
3AとそのAtI#14を同時に除去して、所望の配線
電極z母ターン14を得る(第10図)。As is clear from No. 91m, since it is difficult for wiring metal to adhere to the side surface of the negative resist/mother turf 131L, the wiring metal is deposited on the upper surface of the negative resist/mother turf 131L.
The metal layer 14 deposited on the upper surface of the substrate 11 is separated from the metal layer 14 deposited on the upper surface of the substrate 11. Therefore, in the next step, the metal layer 1-14 formed thereon along with the negative resist pattern 13 is removed. The task of doing so is extremely easy to perform. Finally, use a resist stripping solution (OMR stripping solution manufactured by Tokyo Ohka Co., Ltd., trade name) to remove the negative resist pattern 1.
3A and its AtI #14 are simultaneously removed to obtain the desired wiring electrode z mother turn 14 (FIG. 10).
上述の実施例においては第1のパターン形成物質として
ポジ形7オトレジストを、第2のパターン形成物質とし
てネガ形フォトレノストを用いたが本発明においては第
1および第2のパターン形成物質をそれぞれ上記と逆に
してもよい。また第1の・母ターン形成物質としてシリ
コン酸化物を使用し、第2の・ぞターン形成物質として
ポリイミドのような塗布形成可能な樹脂を用いてもよい
。また上記実施例においては導電パターンの形成物質と
してAtのような金属を用いたが、本発明はその他にも
不純物が添加されたd oped−ポリシリコンのよう
な導電物質を用いてもよい。In the above-mentioned embodiments, positive type 7 photoresist was used as the first pattern forming material and negative type photoresist was used as the second pattern forming material, but in the present invention, the first and second pattern forming materials are each of the above. You can do it the other way around. Alternatively, silicon oxide may be used as the first mother turn forming material, and a resin that can be formed by coating, such as polyimide, may be used as the second mother turn forming material. Further, in the above embodiment, a metal such as At was used as the material for forming the conductive pattern, but the present invention may also use other conductive materials such as doped polysilicon to which impurities are added.
本発明は以上説明したように最後の工程において基板表
面から除去される第2のパターンの形状を断面略逆台形
状にすることによって導電物質が第2の・ヤターンの側
面に付着することを防止し、これにより膜厚の大きい導
電・母ターンを容易に形成することができる。As explained above, the present invention prevents the conductive material from adhering to the side surface of the second pattern by making the shape of the second pattern removed from the substrate surface in the final step substantially inverted trapezoidal in cross section. However, this makes it possible to easily form a conductive/mother turn with a large film thickness.
第1図〜第3図は従来の方法を工程J@に示す断面図、
第4〜第10図は本発明の一実施例の方法を工程順に示
す断面図である。
1ノ・・・基板、7.’A・・第1の・1°ターン、J
、9A・・・第2のノやターン、14・・・導電パター
ン。Figures 1 to 3 are cross-sectional views showing the conventional method at step J@;
4 to 10 are cross-sectional views showing a method according to an embodiment of the present invention in order of steps. 1. Board, 7. 'A...first 1° turn, J
, 9A...second hole or turn, 14...conductive pattern.
Claims (1)
形状の第1の物質より成る第1の・母ターンを形成する
工程;上記第1の・2ターンを含む基板表面に第2の物
質より成るI−を形成する工程;上記第2の物質より成
る1−を上記第1の・9ターンの上面が露出する深さま
で除去する工程;上記第1のパターンを除去しこれによ
って上面の長さが下面の長さよりも長い断面略逆台形状
の第2の物質より成る第2のパターンを基板上に残置さ
せる工程;上記第2の・平ターンを含む基板表面に導電
性物質を第2の・ゼターンの厚さよりも薄く被覆する工
程;上記第2の・セターンおよびこの上の導電性物質を
同時に除去し、これによって基板上に導電性物質から成
る第3のパターンを残置させる工程を具備する導iパタ
ーンの形成方法。 1−[Claims] A step of forming a first mother turn made of a first material having a substantially trapezoidal cross section in which the length of the upper surface is shorter than the length of the lower surface on the substrate; the first two turns; forming an I- made of a second material on the surface of the substrate containing the second material; removing the I- made of the second material to a depth where the upper surface of the first nine turns is exposed; removing the pattern and thereby leaving on the substrate a second pattern made of a second material having a generally inverted trapezoidal cross section in which the length of the upper surface is longer than the length of the lower surface; including the second flat turn; Coating the surface of the substrate with a conductive material thinner than the thickness of the second setane; removing the second setane and the conductive material thereon at the same time, thereby depositing a conductive material on the substrate. A method for forming a conductive i-pattern, comprising the step of leaving the pattern of step 3. 1-
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18324181A JPS5885547A (en) | 1981-11-16 | 1981-11-16 | Forming method for conductive pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18324181A JPS5885547A (en) | 1981-11-16 | 1981-11-16 | Forming method for conductive pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5885547A true JPS5885547A (en) | 1983-05-21 |
Family
ID=16132241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18324181A Pending JPS5885547A (en) | 1981-11-16 | 1981-11-16 | Forming method for conductive pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885547A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521678A (en) * | 1993-12-21 | 1996-05-28 | Xerox Corporation | Electrostatographic imaging drum having a periphery flush with periphery of an end cap |
US5576803A (en) * | 1993-12-21 | 1996-11-19 | Xerox Corporation | Electrostatographic imaging drum end cap and drum assembly |
-
1981
- 1981-11-16 JP JP18324181A patent/JPS5885547A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521678A (en) * | 1993-12-21 | 1996-05-28 | Xerox Corporation | Electrostatographic imaging drum having a periphery flush with periphery of an end cap |
US5576803A (en) * | 1993-12-21 | 1996-11-19 | Xerox Corporation | Electrostatographic imaging drum end cap and drum assembly |
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