JPS60116137A - Multilayer film for semiconductor device - Google Patents

Multilayer film for semiconductor device

Info

Publication number
JPS60116137A
JPS60116137A JP58224933A JP22493383A JPS60116137A JP S60116137 A JPS60116137 A JP S60116137A JP 58224933 A JP58224933 A JP 58224933A JP 22493383 A JP22493383 A JP 22493383A JP S60116137 A JPS60116137 A JP S60116137A
Authority
JP
Japan
Prior art keywords
film
wirings
electrode
insulating
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58224933A
Other languages
Japanese (ja)
Inventor
Takashi Hosaka
俊 保坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP58224933A priority Critical patent/JPS60116137A/en
Publication of JPS60116137A publication Critical patent/JPS60116137A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain withstand against strong alkaline ions and excellent moisture absorption by alternately laminating Si oxide films and Si nitride films to form an insulating layer for electrically insulating between electrodes and wirings. CONSTITUTION:An SiN4 film 3 is formed on lower electrode and wirings 1, and an SiO2 film 4 is formed on the film 3. An insulating film made of 2-layers of the films 3, 4 electrically insulate the wirings 3 and the upper electrode wirings 5, having both features of the Si3N4 film and the SiO2 film. In other words, it has strong withstand for alkaline ions and excellent moisture absorption. Further, it has high insulation. A mask material has pinholes, and even if the film 4 is etched at the etching time, the lower film 3 is not etched. Accordingly, the electrode and the wirings are not shortcircuited.

Description

【発明の詳細な説明】 本発明は、二層以上の電極・配線構造を有する半導体装
置に使用される電極・配線相互間の絶縁層の構造に関す
るものである。すなわち、電極・配線相互間を電気的に
絶縁する絶縁膜の構造は、シリコン窒化膜（以下、Ｓｉ
３Ｎ４膜と記述する）とシリコン酸化膜（以下、５ｈｏ
２膜と記述する）どの少なくとも二層以上の多層膜から
成る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of an insulating layer between electrodes and wiring used in a semiconductor device having an electrode and wiring structure of two or more layers. In other words, the structure of the insulating film that electrically insulates between electrodes and wiring is silicon nitride film (hereinafter, Si
3N4 film) and silicon oxide film (hereinafter referred to as 5ho film)
A multilayer film consisting of at least two or more layers (described as a two-layer film).

二層以上の電極構造を有する半導体装置における従来の
電極・配線相互間の絶縁層は、化学気相成長法で形成さ
れたｓｈｏ！膜から形成されているが、このｓ　６　ｏ
ｓ膜はアルカリイオン等の可動イオンを通しやすい為に
１フィールド部の基板が反転した力、電界効果型トラン
ジスタのゲートしきい値電圧が不安定になるという問題
点がある。Conventional insulating layers between electrodes and wiring in semiconductor devices having an electrode structure of two or more layers are formed using chemical vapor deposition. Although it is formed from a membrane, this s 6 o
Since the s-film easily allows mobile ions such as alkali ions to pass through it, there is a problem that the force caused by the inversion of the substrate in one field portion and the gate threshold voltage of the field effect transistor become unstable.

また、このアルカリイオンの侵入対策として、リンをド
ープしたｓ　４　ｏ、膜（以下ＰＥＩＧ膜と記述する）
あるいは、化学気相成長法によって形成した８ｉｓＮａ
Ｍを使用する場合もある。しかし、ＰＳＧ膜は吸湿性の
問題がちり、ＥｉａＮ４膜の場合はＳ　Ｚ　Ｏ２膜と比
べ誘電率が高く電流が流れやすいという問題点がある。In addition, as a countermeasure against the intrusion of alkali ions, a phosphorus-doped S 4 O membrane (hereinafter referred to as PEIG membrane) is used.
Alternatively, 8isNa formed by chemical vapor deposition
M may also be used. However, the PSG film tends to have a problem of hygroscopicity, and the EiaN4 film has a problem in that it has a higher dielectric constant than the SZO2 film and allows current to flow more easily.

本発明は、上に述べた従来の問題点を解決するものであ
る。以下図面に本発明の一実施例を示す。The present invention solves the above-mentioned conventional problems. An embodiment of the present invention is shown in the drawings below.

１はフィールド酸化膜、２は下部電極・配線としての多
結晶シリコン膜である。この上に、化学気相成長法によ
ｔ）ｓ４３ｎ４膜８を形成する。さらにこの５１３Ｎ、
膜８の上に化学気相成長法によりｓｉ○２膜４を形成す
る。これらの５ｚ３Ｎ４膜８とＳ２０２膜４の二層構造
から成る絶縁層は下部電極・配線２と上部電極・配線５
（たとえばｈＢで形成する）とを電気的に絶縁しておシ
、Ｓｉ：ｌＮ４膜と５ｈｏ２膜の両方の特徴を有してい
る。すなわち、アルカリイオンに対する耐性が強く、シ
かも耐吸湿性に優れている。さらに高い絶縁特性も有し
ている。またｓ”ｔｓＮ４ＭとＳ　＠　０２　膜の二層
より形成されている為、マスク材料にピンホールがちｐ
エツチング時に５ｈｏ２膜がエツチングされても下層の
Ｓ？：ｚＮ４Ｍがエツチングされない事によフ、電極・
配線間（たとえば下部電極・配線２と上部電極配線５〕
の短絡という問題もなくなる。1 is a field oxide film, and 2 is a polycrystalline silicon film as a lower electrode/wiring. On top of this, a s43n4 film 8 is formed by chemical vapor deposition. Furthermore, this 513N,
A Si*2 film 4 is formed on the film 8 by chemical vapor deposition. The insulating layer, which has a two-layer structure of the 5z3N4 film 8 and the S202 film 4, is the lower electrode/wiring 2 and the upper electrode/wiring 5.
(for example, made of hB) and has the characteristics of both a Si:lN4 film and a 5ho2 film. That is, it has strong resistance to alkali ions and excellent moisture absorption resistance. It also has higher insulation properties. Also, since it is formed from two layers of s”tsN4M and S@02 film, the mask material tends to have pinholes.
Even if the 5ho2 film is etched during etching, is the underlying S? : Since zN4M is not etched, electrodes and
Between wiring (for example, lower electrode/wiring 2 and upper electrode wiring 5)
This also eliminates the problem of short circuits.

図面で説明した様な下層がＳｉ３Ｎ４膜で上層がＳ　Ｚ
　Ｏ！膜の二層構造を有する絶縁膜のを１かに、下層が
５（０２膜で上層がＥ３ｉ３Ｎ４朕の二層構造でも、さ
らに”　ｉ　０２　ｋと８１３膜４月１ｋがサンドイン
チ構造に多層に積層した構造でも、前述した優れた特徴
を有する事は明らかである。As explained in the drawing, the lower layer is Si3N4 film and the upper layer is SZ
O! Even if the insulating film has a two-layer structure, the lower layer is 5 (02 film and the upper layer is E3i3N4), the 02 k and 813 film April 1 k are multilayered into a sandwich structure. It is clear that even a laminated structure has the above-mentioned excellent characteristics.

また、下部および上部の電極・配線の材料が図面で示し
た′多結晶シリコンやＡＡＫ限る事はなく、他の導電体
材料でも本発明の絶縁膜を使用できる。Further, the materials of the lower and upper electrodes and wirings are not limited to the polycrystalline silicon and AAK shown in the drawings, and the insulating film of the present invention can be used with other conductor materials.

さらに、本発明の絶縁膜は化学気相成長法以外の方法（
たとえば、物理的気相成長方法）でも作製可能である。Furthermore, the insulating film of the present invention can be produced by methods other than chemical vapor deposition (
For example, it can also be produced using a physical vapor phase growth method.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明による実施例を示す断面図である。 １：フィールド酸化膜　２：下部電極・配線８　：　Ｓ
　ｉｓＨ＜膜　４：ｓｚｏ、膜５膜上部電極・配線　６
：半導体基板 以　上 出願人　セイコー電子工業株式会社 代理人　弁理士　最　上　務The drawings are cross-sectional views showing embodiments of the present invention. 1: Field oxide film 2: Lower electrode/wiring 8: S
isH < film 4: szo, film 5 film upper electrode/wiring 6
: Semiconductor substrates and above Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami

Claims (1)

【特許請求の範囲】[Claims] 半導体装置に使用される二層以上の電極・配線構造にお
いて、電極・配線相互間を電気的に絶縁する絶縁層の構
造がシリコン酸化膜とシリコン窒化膜とが交互に積層し
た少くとも二層から形成されていることを特徴とする半
導体装置用多層膜。In an electrode/wiring structure with two or more layers used in a semiconductor device, the structure of the insulating layer that electrically insulates the electrodes/wirings from each other is composed of at least two layers of alternating layers of silicon oxide films and silicon nitride films. A multilayer film for a semiconductor device, characterized in that:
JP58224933A 1983-11-29 1983-11-29 Multilayer film for semiconductor device Pending JPS60116137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224933A JPS60116137A (en) 1983-11-29 1983-11-29 Multilayer film for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224933A JPS60116137A (en) 1983-11-29 1983-11-29 Multilayer film for semiconductor device

Publications (1)

Publication Number Publication Date
JPS60116137A true JPS60116137A (en) 1985-06-22

Family

ID=16821449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224933A Pending JPS60116137A (en) 1983-11-29 1983-11-29 Multilayer film for semiconductor device

Country Status (1)

Country Link
JP (1) JPS60116137A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114231A (en) * 1985-11-14 1987-05-26 Fujitsu Ltd Semiconductor device
JPS62104445U (en) * 1985-12-23 1987-07-03

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135292A (en) * 1974-09-20 1976-03-25 Matsushita Electric Ind Co Ltd Handotaisochi oyobi sonoseizohoho
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS58164244A (en) * 1982-03-25 1983-09-29 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135292A (en) * 1974-09-20 1976-03-25 Matsushita Electric Ind Co Ltd Handotaisochi oyobi sonoseizohoho
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS58164244A (en) * 1982-03-25 1983-09-29 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114231A (en) * 1985-11-14 1987-05-26 Fujitsu Ltd Semiconductor device
JPH0738443B2 (en) * 1985-11-14 1995-04-26 富士通株式会社 Semiconductor device
JPS62104445U (en) * 1985-12-23 1987-07-03

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