JPH0561783B2 - - Google Patents
Info
- Publication number
- JPH0561783B2 JPH0561783B2 JP62219916A JP21991687A JPH0561783B2 JP H0561783 B2 JPH0561783 B2 JP H0561783B2 JP 62219916 A JP62219916 A JP 62219916A JP 21991687 A JP21991687 A JP 21991687A JP H0561783 B2 JPH0561783 B2 JP H0561783B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- superconducting material
- gate electrode
- layer
- high temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 24
- 239000011224 oxide ceramic Substances 0.000 claims description 14
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 14
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052784 alkaline earth metal Inorganic materials 0.000 claims description 3
- 150000001342 alkaline earth metals Chemical class 0.000 claims description 3
- 229910052788 barium Inorganic materials 0.000 claims description 3
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 3
- 150000002910 rare earth metals Chemical class 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 27
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000002411 adverse Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Containers, Films, And Cooling For Superconductive Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は半導体装置に関し、特にMIS型半導
体素子を有する半導体装置の高速化技術に係わ
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a technology for increasing the speed of a semiconductor device having an MIS type semiconductor element.
（従来技術）
MIS型半導体素子のゲート電極配線には多結晶
シリコン層が通常使用されるが、この多結晶シリ
コン層には配線抵抗が必ず存在するため、動作速
度の高速化を妨げる原因となる。これを解決する
ためには、従来ゲート電極配線として使用されて
いた多結晶シリコン層やポリサイド層の代わり
に、例えば超伝導材料を使用することが考えられ
る。このような超伝導材料としては、例えば文献
（“Z.PHYS.”、1986年、bol64、第189頁、または
“PHYS.REV.LETT”、1987年、bol58、第908
頁）に記載されているように、銅、酸素、アルカ
リ土類金属、希土類金属を含む酸化物セラミツク
高温超伝導材料や、銅、酸素、バリウム、イツト
リウムを含む酸化物セラミツク高温超伝導材料、
または銅、酸素、ランタンを含む酸化物高温超伝
導材料が知られている。(Prior art) A polycrystalline silicon layer is usually used for the gate electrode wiring of MIS type semiconductor devices, but since wiring resistance always exists in this polycrystalline silicon layer, it becomes a cause of hindering the increase in operating speed. . In order to solve this problem, it is conceivable to use, for example, a superconducting material instead of the polycrystalline silicon layer or polycide layer that has been conventionally used as the gate electrode wiring. Such superconducting materials include, for example, the literature (“Z.PHYS.”, 1986, bol 64, p. 189, or “PHYS.REV.LETT”, 1987, bol 58, p. 908).
oxide ceramic high temperature superconducting materials containing copper, oxygen, alkaline earth metals, and rare earth metals; oxide ceramic high temperature superconducting materials containing copper, oxygen, barium, and ythtrium;
Alternatively, oxide high-temperature superconducting materials containing copper, oxygen, and lanthanum are known.
しかしながら、従来のMIS型半導体素子のゲー
ト電極配線として単に酸化物セラミツク高温超伝
導材料を使用しただけでは、良好な超伝導特性を
得ることはできない。これは、MIS型半導体素子
の絶縁層にはシリコン酸化膜やシリコン窒化膜、
またはこれらの混合膜が通常使用されているから
である。このような材料より成る絶縁層上に酸化
物セラミツク高温超伝導材料を堆積してもこの材
料に良好な超伝導特性を持たせるのが困難な事は
既に知られている。 However, it is not possible to obtain good superconducting characteristics simply by using oxide ceramic high temperature superconducting material as the gate electrode wiring of a conventional MIS type semiconductor device. This is because the insulating layer of MIS type semiconductor devices is silicon oxide film, silicon nitride film, etc.
Alternatively, a mixed membrane of these is commonly used. It is already known that even if an oxide ceramic high temperature superconducting material is deposited on an insulating layer made of such a material, it is difficult to impart good superconducting properties to this material.
（発明が解決しようとする問題点）
この発明は前述の事情に鑑みなされたもので、
従来の半導体装置では動作の高速化を計るために
ゲート電極配線を超伝導材料で形成しても、その
下層となる絶縁層がシリコン酸化膜で形成されて
いるため良好な超伝導特性を得ることができなか
つた点を改善し、ゲート電極に良好な超伝導特性
を持たせられるようにし、高速動作可能な半導体
装置を提供することを目的とする。(Problems to be solved by the invention) This invention was made in view of the above-mentioned circumstances.
In conventional semiconductor devices, even if the gate electrode wiring is made of superconducting material to speed up operation, the underlying insulating layer is made of silicon oxide film, so good superconducting properties cannot be obtained. The purpose of this invention is to provide a semiconductor device capable of high-speed operation by improving the points that could not be achieved in the prior art, by providing a gate electrode with good superconducting properties.
［発明の構成］
（問題点を解決するための手段）
この発明による半導体装置にあつては、
MIS型半導体素子を有する半導体装置におい
て、前記MIS型半導体素子のゲート電極配線を超
伝導材料により形成し、このゲート電極配線下の
絶縁層の少なくとも前記ゲート電極配線に接触す
る部分はチタン酸ストロンチウムにより形成した
ものである。[Structure of the Invention] (Means for Solving the Problems) In a semiconductor device according to the present invention, in a semiconductor device having an MIS type semiconductor element, a gate electrode wiring of the MIS type semiconductor element is formed of a superconducting material. However, at least a portion of the insulating layer under the gate electrode wiring that contacts the gate electrode wiring is made of strontium titanate.
（作用）
前記構成の半導体装置にあつては、超伝導材料
により形成されるゲート電極配線は、チタン酸ス
トロンチウム層上に形成されるので、従来のシリ
コン酸化膜のように超伝導特性に悪影響を及ぼす
ことがなく、良好な超伝導特性をゲート電極配線
に持たせることが可能となる。また、前記チタン
酸ストロンチウムは、エネルギーギヤツプが約
3.15eVであり、比誘電率が約300であるので絶縁
性もよく、薄い絶縁膜が要求される素子の微細化
にも充分に対応することができる。(Function) In the semiconductor device having the above structure, the gate electrode wiring made of a superconducting material is formed on the strontium titanate layer, so it does not have an adverse effect on superconducting properties like a conventional silicon oxide film. It is possible to provide the gate electrode wiring with good superconducting properties without causing any adverse effects. Furthermore, the strontium titanate has an energy gap of approximately
3.15 eV and a relative dielectric constant of about 300, it has good insulation properties and can fully respond to miniaturization of elements that require thin insulating films.
（実施例）
以下、第１図を参照してこの発明の一実施例を
その製造工程に基づいて説明する。(Example) Hereinafter, an example of the present invention will be described based on its manufacturing process with reference to FIG.
まず第１図Ａに示すように、半導体基板１０１
上に周知の方法を用いて素子分離領域１０２を形
成した後、SiO2膜１０３を形成する。続いて、
例えばスパツタ法により全面にチタン酸ストロン
チウム（SrTiO3）層１０４を堆積形成する。次
にスパツタ法により超伝導材料材料、例えば銅、
酸素、アルカリ土類金属、希土類金属を含む酸化
物セラミツク高温超伝導材料を全面に堆積して、
酸化物セラミツク高温超伝導層１０５を形成す
る。そして、所定の条件下で熱処理を行なうこと
により、酸化物セラミツク高温超伝導層１０５に
超伝導特性を持たせる。 First, as shown in FIG. 1A, a semiconductor substrate 101
After forming an element isolation region 102 thereon using a well-known method, a SiO 2 film 103 is formed. continue,
For example, a strontium titanate (SrTiO 3 ) layer 104 is deposited over the entire surface by sputtering. Next, the superconducting material, such as copper, is
Oxide ceramic high temperature superconducting material containing oxygen, alkaline earth metals, and rare earth metals is deposited on the entire surface.
An oxide ceramic high temperature superconducting layer 105 is formed. Then, by performing heat treatment under predetermined conditions, the oxide ceramic high temperature superconducting layer 105 is imparted with superconducting properties.
次に第１図Ｂに示すように、PEP法および選
択エツチング法を用いて酸化物セラミツク高温超
伝導層１０５、チタン酸ストロンチウム層１０
４、SiO2膜１０３を加工して図示のようなゲー
ト電極部を形成した後、イオン注入により不純物
を導入してソースおよびドレイン領域１０６，１
０７をそれぞれ形成する。 Next, as shown in FIG. 1B, the oxide ceramic high temperature superconducting layer 105 and the strontium titanate layer 10 are etched using the PEP method and the selective etching method.
4. After processing the SiO 2 film 103 to form a gate electrode portion as shown in the figure, impurities are introduced by ion implantation to form source and drain regions 106 and 1.
07 respectively.
次に第１図Ｃに示すように、層間絶縁膜１０８
を全面に堆積形成した後に、ソースおよびドレイ
ン領域１０６，１０７上にコンタクトホールを開
孔し、そこにソース電極１０９、ドレイン電極１
１０をそれぞれ形成する。 Next, as shown in FIG. 1C, the interlayer insulating film 108
After depositing on the entire surface, contact holes are formed on the source and drain regions 106 and 107, and a source electrode 109 and a drain electrode 1 are formed therein.
10 each.
このようにこの発明にあつては、ゲート電極配
線を超伝導層により形成すると共に、充分な絶縁
層性を有ししかも超伝導特性に悪影響を及ぼさな
いチタン酸ストロンチウム層上にその超伝導層を
形成しており、さらにこのチタン酸ストロンチウ
ム層はペロブスカイト構造を有して格子定数のマ
ツチングも良くなり、良好な超伝導特性をゲート
電極配線に持たせることが可能となる。 In this way, in this invention, the gate electrode wiring is formed of a superconducting layer, and the superconducting layer is formed on a strontium titanate layer that has sufficient insulating properties and does not adversely affect the superconducting properties. Furthermore, this strontium titanate layer has a perovskite structure, which improves the matching of lattice constants, making it possible to provide the gate electrode wiring with good superconducting properties.
尚、この実施例ではゲート電極配線下の絶縁層
をSiO2膜１０３とチタン酸ストロンチウム層１
０４との積層膜で形成したが、SiO2膜１０３を
形成せずにチタン酸ストロンチウム層１０４だけ
で絶縁層を形成してもよい。また、この発明を
MIS型構造のキヤパシタに適用することもでき
る。この場合には、酸化物セラミツク高温超伝導
層１０５がキヤパシタの一方の電極となり、チタ
ン酸ストロンチウム層１０４およびSiO2膜１０
３が誘電体となり、そして半導体基板１０１がそ
の他方の電極となる。 In this embodiment, the insulating layer under the gate electrode wiring is composed of a SiO 2 film 103 and a strontium titanate layer 1.
Although the insulating layer is formed using a laminated film of strontium titanate layer 104 and strontium titanate layer 104 without forming the SiO 2 film 103. Also, this invention
It can also be applied to capacitors with MIS type structure. In this case, the oxide ceramic high temperature superconducting layer 105 becomes one electrode of the capacitor, and the strontium titanate layer 104 and the SiO 2 film 10
3 serves as a dielectric, and the semiconductor substrate 101 serves as the other electrode.
また、超伝導材料としては、銅、酸素、バリウ
ム、イツトリウムを含む酸化物セラミツク高温超
伝導材料や、銅、酸素、ランタンを含む酸化物セ
ラミツク高温超伝導材料を使用することもでき
る。 Further, as the superconducting material, an oxide ceramic high temperature superconducting material containing copper, oxygen, barium, and yttrium, and an oxide ceramic high temperature superconducting material containing copper, oxygen, and lanthanum can also be used.
［発明の効果］
以上のようにこの発明によれば、ゲート電極に
良好な超伝導特性を持たせることが可能となり、
高速動作可能な半導体装置を得ることができる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a gate electrode with good superconducting properties,
A semiconductor device capable of high-speed operation can be obtained.
第１図はこの発明の一実施例に係る半導体装置
を説明する断面図である。
１０１……半導体基板、１０２……素子分離領
域、１０３……SiO2膜、１０４……チタン酸ス
トロンチウム層、１０５……酸化物高温超伝導
層。
FIG. 1 is a sectional view illustrating a semiconductor device according to an embodiment of the present invention. 101... Semiconductor substrate, 102... Element isolation region, 103... SiO 2 film, 104... Strontium titanate layer, 105... Oxide high temperature superconducting layer.
Claims (1)
て、 前記MIS型半導体素子のゲート電極配線は超伝
導材料により形成され、このゲート電極配線下の
絶縁層の少なくとも前記ゲート電極配線に接触す
る部分はチタン酸ストロンチウムにより形成され
ていることを特徴とする半導体装置。 ２ 前記絶縁層は下層がシリコン酸化膜で上層が
チタン酸ストロンチウムより成る２層構造である
ことを特徴とする特許請求の範囲第１項記載の半
導体装置。 ３ 前記超伝導材料は、銅、酸素、アルカリ土類
金属、希土類金属を含む酸化物セラミツク高温超
伝導材料であることを特徴とする特許請求の範囲
第１項記載の半導体装置。 ４ 前記超伝導材料は、銅、酸素、バリウム、イ
ツトリウムを含む酸化物セラミツク高温超伝導材
料であることを特徴とする特許請求の範囲第１項
記載の半導体装置。 ５ 前記超伝導材料は、銅、酸素、ランタンを含
む酸化物セラミツク高温超伝導材料であることを
特徴とする特許請求の範囲第１項記載の半導体装
置。[Claims] 1. In a semiconductor device having an MIS type semiconductor element, a gate electrode wiring of the MIS type semiconductor element is formed of a superconducting material, and an insulating layer under the gate electrode wiring is in contact with at least the gate electrode wiring. A semiconductor device characterized in that a portion thereof is formed of strontium titanate. 2. The semiconductor device according to claim 1, wherein the insulating layer has a two-layer structure in which a lower layer is a silicon oxide film and an upper layer is strontium titanate. 3. The semiconductor device according to claim 1, wherein the superconducting material is an oxide ceramic high temperature superconducting material containing copper, oxygen, an alkaline earth metal, and a rare earth metal. 4. The semiconductor device according to claim 1, wherein the superconducting material is an oxide ceramic high temperature superconducting material containing copper, oxygen, barium, and yttrium. 5. The semiconductor device according to claim 1, wherein the superconducting material is an oxide ceramic high temperature superconducting material containing copper, oxygen, and lanthanum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62219916A JPS6461952A (en) | 1987-09-02 | 1987-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62219916A JPS6461952A (en) | 1987-09-02 | 1987-09-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6461952A JPS6461952A (en) | 1989-03-08 |
| JPH0561783B2 true JPH0561783B2 (en) | 1993-09-07 |
Family
ID=16743031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62219916A Granted JPS6461952A (en) | 1987-09-02 | 1987-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6461952A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6474758A (en) * | 1987-09-17 | 1989-03-20 | Fujitsu Ltd | Insulated gate field-effect transistor |
| JP2540185B2 (en) * | 1988-04-14 | 1996-10-02 | 松下電子工業株式会社 | Semiconductor device |
| JP2004503920A (en) * | 2000-05-31 | 2004-02-05 | モトローラ・インコーポレイテッド | Semiconductor device and method of manufacturing the semiconductor device |
| JP2002026312A (en) | 2000-07-06 | 2002-01-25 | National Institute Of Advanced Industrial & Technology | Semiconductor device |
-
1987
- 1987-09-02 JP JP62219916A patent/JPS6461952A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6461952A (en) | 1989-03-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |