JPS60106171A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60106171A JPS60106171A JP21469683A JP21469683A JPS60106171A JP S60106171 A JPS60106171 A JP S60106171A JP 21469683 A JP21469683 A JP 21469683A JP 21469683 A JP21469683 A JP 21469683A JP S60106171 A JPS60106171 A JP S60106171A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type
- diffusion
- semiconductor substrate
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66393—Lateral or planar thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は１例えばプレーナ型サイリスタ（シリコン制
御整流素子）において、特に、電気的特性を半導体菓子
の垂直距離で制御する際に用いられる半導体装置の製造
方法に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor device used, for example, in a planar thyristor (silicon-controlled rectifying element), particularly when electrical characteristics are controlled by the vertical distance of a semiconductor confectionery. Regarding the manufacturing method.
（発明の技術的背景とその問題点〕
一般に、ブレーナ型のサイリスタは、第１図に示すよう
な素子構造で形成されている。すなわち、先ず、Ｎ型半
導体基板１１に対して、その両面よりＰ型アイソレーシ
ョン拡散層（絶縁分離層）ｚ２ａ、ｚ２ｂを形成し、コ
ノ後、Ｐ型アノード拡散層１３およびＰ型ゲート拡散層
１４を、それぞれ同時または順次選択的に形成する。そ
して、このＰ型ゲート拡散層１４の表面に、Ｎ＋型カソ
ード拡散層１５を形成して。(Technical background of the invention and its problems) In general, a Brehner-type thyristor is formed with an element structure as shown in Fig. 1. First, an N-type semiconductor substrate 11 is P-type isolation diffusion layers (insulating separation layers) z2a and z2b are formed, and after this, a P-type anode diffusion layer 13 and a P-type gate diffusion layer 14 are selectively formed simultaneously or sequentially. An N+ type cathode diffusion layer 15 is formed on the surface of the type gate diffusion layer 14.
Ｐ型とＮ型との導電性の異なる４つの領域（Ｐ−、Ｎ−
ＰＮ）を形成し、ｆイリスタを構成している。Four regions with different conductivities (P-, N-
PN) and constitutes an f iris register.
ここで１例えば、このサイリスタの電気的時゛性を制御
するために、Ｐ型アノード拡散層１３とＰ型ゲート拡散
層１４との垂直距離人を、特に、狭くして形成する場合
には、第１の手段として、予め薄く形成した半導体基板
を用ｂ）る方法がある。しかし、このよう（二薄り）半
導体基板を用いると、製造工程中に半導体基板の反０不
良や割れ不良等が発生する状態となり、製品歩留を低下
させてしまう。For example, if the vertical distance between the P-type anode diffusion layer 13 and the P-type gate diffusion layer 14 is particularly narrowed in order to control the electrical timing of the thyristor, As a first means, there is a method (b) of using a semiconductor substrate formed thinly in advance. However, when such a (bi-thin) semiconductor substrate is used, defects such as anti-zero defects and cracking defects of the semiconductor substrate occur during the manufacturing process, resulting in a decrease in product yield.
また、第２の手段として、先ず、Ｐ型カソード拡散層１
３を予め深く拡散形成し、次１−１．．Ｐ型ゲート拡散
層１４を形成して、その相互距離Ａを狭く形成する方法
も考えられている。し力１し、このように、Ｐ型カソー
ド拡散Ｎ１３とＰ型ゲート拡散層１４とを、それぞれ別
々の２回の拡散工程から形成したのでは、製造工程カー
複雑化して加工費が増加するという問題カー化じる。In addition, as a second means, first, the P-type cathode diffusion layer 1
3 is deeply diffused in advance, and then 1-1. ．． A method has also been considered in which the P-type gate diffusion layer 14 is formed and the mutual distance A thereof is narrowed. However, if the P-type cathode diffusion layer N13 and the P-type gate diffusion layer 14 were formed in two separate diffusion steps, the manufacturing process would become complicated and the processing cost would increase. It turns into a problem car.
この発明は上記のような問題点に鑑みなされたもので１
例えば厚めの半導体基板を用ｂ）るような場合でも、拡
散工程が複雑化することなく。This invention was made in view of the above problems.1
For example, even when using a thicker semiconductor substrate, the diffusion process does not become complicated.
半導体素子の垂直距離を任意に制御すること力ｔできる
半導体装置の製造方法を提供することを目的とする。It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows the vertical distance of semiconductor elements to be arbitrarily controlled.
すなわちこの発明に係る半導体装置の製造方法は、アイ
ソレーション拡散層とアノード拡散層とを、それぞれ同
一の拡散層として同時に形成し、上記アノード拡散層の
拡散距離をさらに深めるようにしたものである。That is, in the method of manufacturing a semiconductor device according to the present invention, an isolation diffusion layer and an anode diffusion layer are simultaneously formed as the same diffusion layer, and the diffusion distance of the anode diffusion layer is further deepened.
以下図面によりこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図（５）乃至（Ｑはそれぞれその製造工程を示すも
ので、先ず同図（５）に示すように、Ｎ型半導体基板１
１の表面には、例えば、フォトエツチング工程（ＰＥＰ
）により、選択的に絶縁酸化膜２ｚを形成する、次に、
第２図（ａに示すように、Ｎ型半導体基板１１の表面に
は、ホウ素Ｂ縁の不純物を使用してＰ型のアイソレーシ
ョン拡散層（絶縁分離層）２２ａ、２２ｂを選択的に形
成し、これと同時にその裏面には、Ｐ型アノード拡散層
２３を上記と同様の不純物（この場合、ホウ累Ｂ）によ
り全面的に形成する。この場合、上記アイソレーション
拡散層２２ ａ ＊２２ｂとアノード拡散層２３とは、
それぞれ同一の拡散層として形成されるもので、このそ
れぞれの拡散層２２ａ、２２ｂおよび２３の拡散深さＹ
ｌおよびＹ、を調節することにより、この半導体装置の
電気的特性を任意に制御する。FIG. 2 (5) to (Q indicate the manufacturing process, respectively. First, as shown in FIG. 2 (5), an N-type semiconductor substrate 1
For example, the surface of 1 is subjected to a photo-etching process (PEP
) to selectively form an insulating oxide film 2z.
As shown in FIG. 2(a), P-type isolation diffusion layers (insulating separation layers) 22a and 22b are selectively formed on the surface of the N-type semiconductor substrate 11 using boron B-edge impurities. At the same time, a P-type anode diffusion layer 23 is formed entirely on the back surface using the same impurity as described above (in this case, borosilicate B).In this case, the isolation diffusion layer 22a*22b and the anode What is the diffusion layer 23?
They are formed as the same diffusion layer, and the diffusion depth Y of each of these diffusion layers 22a, 22b, and 23 is
By adjusting l and Y, the electrical characteristics of this semiconductor device can be arbitrarily controlled.
ここで、アノード拡散層２３を深く拡散すると。Here, if the anode diffusion layer 23 is deeply diffused.
電気的特性が安定し、また、逆に浅く拡散すると、絶縁
耐圧が上昇する。The electrical characteristics become stable, and conversely, when the material is diffused shallowly, the dielectric strength increases.
そして、第２図（Ｃ）に示すように、上記Ｐ型アイソレ
ーション拡散層２２ａ、２２ｂおよびＰ型アノード拡散
層２３により包囲される、半導体基板１１のＮ型ベース
領域２４に対して、Ｐ型ゲート拡散層２５を形成し、さ
らにその表面にＮ＋型カソード拡散層２６を形成する。Then, as shown in FIG. 2(C), a P-type A gate diffusion layer 25 is formed, and an N+ type cathode diffusion layer 26 is further formed on the surface thereof.
この後、Ｐ型ゲート拡散層２５およびＮ 型カソード拡
散ＩＭ２６の表面にそれぞれゲートＧおよびカソードに
電極導出部２７ａ、２’ｉｂを形成し、また、Ｐ型アノ
ード拡散層２３の表面にも、Ｐ＋型アノード高濃度層２
８を介してアノードＡ電極導出部２’ＩＣを形成する。Thereafter, electrode lead-out portions 27a and 2'ib are formed on the gate G and cathode, respectively, on the surfaces of the P-type gate diffusion layer 25 and the N-type cathode diffusion layer 26, and also on the surface of the P-type anode diffusion layer 23, P+ Type anode high concentration layer 2
8 to form an anode A electrode lead-out portion 2'IC.
すなわちこのような製造工程においては、Ｐ型アイソレ
ーション拡散層２２ａ、２２ｂとＰ型アノード拡散層２
３とを、それぞｎ同時：′″−拡散形成するようにした
ので、例えば、このＰ型アノード拡散層２３とＰ型ゲー
ト拡散層２５とを、それぞＩｔ ＪＩＩＤ次別々の工程
で形成するような場合でも、実質的にその製造工程が複
雑化することはない。したがって％Ｐ型アノード拡散層
２３をＰ型アイソレーション層２２ａ、２２ｂと同時に
、予め任意の拡散深さで形成しておくことにより、この
後の工程で形成されるＰ型ゲート拡散層２５との垂直距
離へを任意よ二調節することが可能となり、電気的特性
を容易Ｃ二制御することができる。That is, in such a manufacturing process, the P-type isolation diffusion layers 22a, 22b and the P-type anode diffusion layer 2
3 and 3 are simultaneously formed by diffusion, for example, the P-type anode diffusion layer 23 and the P-type gate diffusion layer 25 are formed in separate steps. Even in such a case, the manufacturing process is not substantially complicated.Therefore, the P-type anode diffusion layer 23 is formed in advance at an arbitrary diffusion depth at the same time as the P-type isolation layers 22a and 22b. As a result, it becomes possible to arbitrarily adjust the vertical distance to the P-type gate diffusion layer 25 formed in the subsequent step, and the electrical characteristics can be easily controlled.
以上のようにこの発明によれば１例えば厚めの半導体基
板を用いるような場合でも、拡散工程を複雑化すること
なく、半導体素子の垂直距離を任意に調節することがで
き、電気的特性な簡単ビ制御することが可能となる。As described above, according to the present invention, 1. Even when using a thick semiconductor substrate, the vertical distance of the semiconductor element can be arbitrarily adjusted without complicating the diffusion process, and the electrical characteristics can be easily adjusted. It becomes possible to control the
第１図はプレーナ型サイリスタを示す断面構成図％第２
図（５）乃至（Ｑはそれぞれこの発明の一実施例に係る
半導体装置の製造方法をその工程順に示す断面構成図で
ある、
１１・・・Ｎ型半導体基板、２１・・・絶縁酸化膜。
２２ａ、２２ｂ・・・Ｐ型アイソレーション拡散層、２
３・・・Ｐ型アノード拡散層、２４・・・Ｎ型ペース領
域、２５・・・Ｐ型ゲート拡散層、２６・・・Ｎ＋型カ
ソード拡散層、２７ａ〜２７ｂ・・・電極導出部。
２８・・・Ｐ＋型アノード高濃度層。
出願人代理人 弁理士 鈴 江 武 彦第１図
（Ｂ）Figure 1 is a cross-sectional diagram showing a planar thyristor%2
Figures (5) to (Q) are cross-sectional configuration diagrams showing the method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, 11...N-type semiconductor substrate, 21... Insulating oxide film. 22a, 22b...P type isolation diffusion layer, 2
3...P type anode diffusion layer, 24...N type space region, 25...P type gate diffusion layer, 26...N+ type cathode diffusion layer, 27a-27b...electrode lead-out portion. 28...P+ type anode high concentration layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (B)
Claims (1)
シユレーシヨン拡散層を形成する手段と、この第２導電
型アイシユレーシヨン拡散層の形成時と同時に上記第１
導電型半導体基板の裏面に全面的に第２導電型アノード
拡散層を形成する手段と、この第２導電型アノード拡散
層と上記第２導電型アイシユレーシヨン拡散層とによっ
て包囲されてなる第１導電型ベース領域の表面に第２導
電型ゲート拡散層を形成する手段とを具備し、上記第２
導電型アイシユレーシヨン拡散層と第２導電型アノード
拡散層とをそ牡ぞれ同一の拡散層として形成することを
特徴とする半導体装置の製造方法。means for selectively forming a second conductivity type islation diffusion layer on the surface of the first conductivity type semiconductor substrate;
means for forming a second conductivity type anode diffusion layer on the entire back surface of the conductivity type semiconductor substrate; means for forming a second conductivity type gate diffusion layer on the surface of the first conductivity type base region;
1. A method of manufacturing a semiconductor device, comprising forming a conductive type isolation diffusion layer and a second conductive type anode diffusion layer as the same diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21469683A JPS60106171A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21469683A JPS60106171A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60106171A true JPS60106171A (en) | 1985-06-11 |
Family
ID=16660084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21469683A Pending JPS60106171A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60106171A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4838080A (en) * | 1971-09-16 | 1973-06-05 | ||
| JPS5224475A (en) * | 1975-08-20 | 1977-02-23 | Nec Corp | Planar thyristor process |
-
1983
- 1983-11-15 JP JP21469683A patent/JPS60106171A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4838080A (en) * | 1971-09-16 | 1973-06-05 | ||
| JPS5224475A (en) * | 1975-08-20 | 1977-02-23 | Nec Corp | Planar thyristor process |
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