JPS5928368A - Semiconductor capacitor - Google Patents

Abstract

PURPOSE:To contrive to increase the value of capacity by a method wherein a row of deep grooves or an unevenness is provided on the surface of an N (or P)- type semiconductor substrate, a P (or N)-layer is superposed, and then the P-N junction is determined as a capacitor. CONSTITUTION:The row of deep grooves 11 is formed by selectively etching the surface of the N type Si layer 10, the P-epitaxial layer 12 is superposed, windows are opened through the SiO2 film 13 of the flatted surface, and Al electrodes 14 and 15 are laid. As the angle of inclination theta of a groove is more increased, and widths (a) and (b) of the flat part are more decreased, the surface area more increases, and accordingly the P-N junction capacity more increases. When rows of grooves are provided lengthwise and crosswise, the rate of increase of the surface area becomes the second power of the case of one direction. Or, when an N<+> diffused layer 17 is provided on the surface of the deep etched groove 11, an Al electrode 19 is provided via a thermal oxide film 18, an N<+> layer 20 and an electrode 21 are provided outside the groove row region, the value of capacity can be also increased. This constitution enables to increase the value of capacity with the same area.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor capacitive element formed as part of a monolithic IC (semiconductor integrated circuit device).

Semiconductor capacitor elements include junction capacitors using semiconductor PN junctions and MOS transistors using MOS (metal/oxide film/semiconductor) structures.
O3 type capacitor is known.

As shown in FIG. 1, the junction capacitor is formed by diffusing P-type impurities into the N-type epitaxial layer J and then diffusing high concentration N+ into the P-type layer 2. Terminals 4 and 5 are provided on each N-type layer 3 to form a junction type capacitor.

In the case of such a junction type capacitor, in order to increase the capacitance value per unit area, it is sufficient to increase the difference in concentration of impurities, but the withstand voltage becomes small.

Therefore, in order to obtain a large capacity, it is necessary to increase the area of the capacitor.

As shown in FIG. 2, the MQS type capacitor is made of an oxide film (SiQ
, a film) 6 is formed, the top thereof is covered with AL, and an AL electrode 7 is formed.
An electrode 8 is provided between the capacitor and the N-type epitaxial layer to form an MO8 type capacitor.

In the case of such an MO8 type capacitor, in order to increase the capacitance per unit area, it is necessary to reduce the thickness of the oxide film.

In the case of distortion, the flat surface of the semiconductor (epitaxial layer) is also used, and there is a limit to how much capacitance can be increased in the same area.

The present invention aims to obtain large capacitance in the same area by partially forming groove arrays or unevenness on the semiconductor surface to increase the surface area by some method.

FIG. 3 shows a cross-sectional structural diagram of the proposed junction capacitive element.

This semiconductor capacitive element has a deep groove array 11 formed by selective etching on the surface of an N (or P) type S+ substrate lo (which may be an epitaxial layer), and on which a deep groove array 11 is formed by selective etching, that is, a P (or N) type semiconductor S1 layer 12 is epitaxially grown, and an oxide film (Si
n, ) 13 is opened, and the N(P) base side and P(
N) Electrodes 14 and ' 15 each made of A4 on the layer side.
It has been established. FIG. 5 shows the form of the groove array in a slanted view.

By forming the groove array as described above, the surface area becomes larger than that in the case where the surface area is flat. That is, the larger the inclination angle θ of the groove (<90°) or the smaller the widths a and b of the flat portions, the larger the surface area can be. Therefore, according to the present invention, since the surface area is increased by the groove array, the capacitance value can be increased in proportion to the increase in surface area.

Note that the groove rows are not limited to one direction, and may be formed as a large number of uneven portions 16 by providing groove rows in the vertical and horizontal directions as shown in FIG. In this case, the rate of increase in surface area due to the groove array is the square of that in the case of one direction.

FIG. 4 shows a cross-sectional structure of an MO8 type capacitive element according to the present invention. This semiconductor capacitive element has an N (or P) type Si substrate 10
A groove array 11 is formed by deep etching on the surface, and a highly concentrated N+ (or p+ > type diffusion layer 17) is formed on the surface.
was formed, an oxide film (stow film) 18 was formed by thermal oxidation, and then Ap was evaporated to form an electrode 19.
An N+ type scattered layer 2o is also formed on the surface of the substrate where the groove array is not formed, and the other electrode 21 is provided on that surface.

In this case as well, as in the embodiment described above (FIG. 3), the surface area is increased by forming the groove array, and therefore the capacitance value can be increased. Note that the groove array may also be formed in an uneven shape as shown in FIG.

[Brief explanation of the drawing]

FIG. 1 shows a cross-sectional structural diagram of a junction type capacitor currently in use. FIG. 2 shows a cross-sectional structural diagram of an MO8 type capacitor currently in use. FIG. 3 shows a cross-sectional structural diagram of the junction type capacitor newly invented. FIG. 4 shows a cross-sectional structural diagram of the MO8 type capacitor invented this time. FIG. 5 and vK6 show the shapes of the groove rows (irregularities) using oblique views. 1...N epitaxial layer, 2...P+ diffusion layer, 3
...N+ type scattering layer 4.5...A! β electrode 6...
Oxide film, 7, 8 ・A At electrode, 10 ・N (P)
Type base, 11...Groove array, 12...P (N) type Si
Layer, 13... Oxide film, 14.15... Aβ electrode, 1
6... Uneven portion, 17... N+ type scattering layer 18...
Oxide film, 19...Aβ electrode, 2°...N+ type diffusion layer, 2nd grade...Apβ electrode agent Patent attorney Susuki 1) Toshiyuki, 3, 7. [ノ−゛、“：；・′ 、、 、、!

Claims (1)

[Claims] 1. A deep groove array or unevenness is formed on the surface of an N (or P) type semiconductor substrate, and a P layer of conductivity type opposite to that of the substrate is formed on the surface on which the groove array or unevenness is formed. 1. A semiconductor capacitive element, characterized in that a (or N) type semiconductor layer is formed, and a PN junction between the N(P) type substrate and the P(N) type layer serves as a capacitor. 2. The semiconductor capacitive element according to claim 1, wherein the P (or N) type semiconductor layer formed on the groove array or the unevenness is a semiconductor layer formed by epitaxial growth. 3. Forming deep groove rows or unevenness on the surface of the semiconductor substrate, forming a conductive film on the surface where the groove rows or the unevenness are formed with an insulating film interposed therebetween, and combining the semiconductor substrate with the insulating film and the conductive film. A semiconductor capacitive element characterized in that its capacitance is MO8 capacitance. 4. The semiconductor capacitive element according to claim 3, wherein the insulating film is a semiconductor oxide film obtained by oxidizing the semiconductor surface on which groove rows or grooves are formed.