JPH04348563A - Semiconductor ic - Google Patents
Semiconductor icInfo
- Publication number
- JPH04348563A JPH04348563A JP12112691A JP12112691A JPH04348563A JP H04348563 A JPH04348563 A JP H04348563A JP 12112691 A JP12112691 A JP 12112691A JP 12112691 A JP12112691 A JP 12112691A JP H04348563 A JPH04348563 A JP H04348563A
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- conductivity type
- lower electrode
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000010354 integration Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はバイポーラ素子とＭＯＳ
素子とを混在したＢｉ−ＣＭＯＳ半導体素子の容量素子
に関する。[Industrial Application Field] The present invention relates to bipolar devices and MOS devices.
The present invention relates to a capacitive element of a Bi-CMOS semiconductor element in which a Bi-CMOS semiconductor element is mixed.
【０００２】0002
【従来の技術】バイポーラ型集積回路に組み込まれる容
量素子として、ＰＮ接合を利用するもの、酸化膜（Ｓｉ
Ｏ２）や窒化膜（ＳｉＮ）を利用するものが知られてい
る。前者は構造が簡単である特徴を有し、後者は単位面
積当りの容量値を大きくできる利点を有する。そのため
微細化を押し進めた半導体装置では後者が多用されてい
る。[Prior Art] Capacitive elements incorporated in bipolar integrated circuits include capacitors that utilize PN junctions and oxide films (Si).
There are known devices that utilize O2) and nitride film (SiN). The former has a feature of simple structure, and the latter has the advantage of being able to increase the capacitance value per unit area. For this reason, the latter is often used in semiconductor devices that have been miniaturized.
【０００３】後者の代表的な構造を図３に示す。即ち、
半導体基板（１）上のエピタキシャル層を分離した島領
域（２）内に、Ｎ＋型拡散領域を形成して下部電極（３
）とし、ＳｉＯ２又はＳｉＮから成る誘電体薄膜（４）
上にＡｌ配線で上部電極（５）を形成したものである（
例えば、特公昭６１−２４８２５号公報）。尚、（６）
はＮ＋埋め込み層、（７）はＰ＋分離領域、（８）はＡ
ｌ電極、（９）は酸化膜である。また、前記下部電極（
３）としては、直列抵抗分を下げるため、および工程の
共用化の点でＮＰＮトランジスタのエミッタ拡散が使わ
れている。A typical structure of the latter is shown in FIG. That is,
An N+ type diffusion region is formed in an island region (2) separated from the epitaxial layer on the semiconductor substrate (1) to form a lower electrode (3).
) and a dielectric thin film (4) made of SiO2 or SiN.
An upper electrode (5) is formed on top using Al wiring (
For example, Japanese Patent Publication No. 61-24825). Furthermore, (6)
is N+ buried layer, (7) is P+ isolation region, (8) is A
The l electrode (9) is an oxide film. In addition, the lower electrode (
As for 3), emitter diffusion of an NPN transistor is used in order to reduce the series resistance and to share the process.
【０００４】近年、バイポーラ素子とＭＯＳ素子とを混
在化したＢｉ−ＣＭＯＳ集積回路が出現し、斯る装置に
も容量素子を組み込む要望が強い。この場合、ＭＯＳ素
子と上記後者の構造とが近似しているため、誘電体薄膜
（４）にゲート酸化膜を、上部電極（５）にゲート電極
を利用する試みが成されている。その際、工程の簡素化
の点でＮＰＮトランジスタのエミッタとＮｃｈＭＯＳの
ソース・ドレイン領域とを共用化した場合、容量素子の
下部電極（３）としてエミッタ拡散を利用することがで
きなくなる。そのため、エミッタ拡散工程前に形成する
領域、例えばＰ＋型分離領域（７）や、ＮＰＮトランジ
スタのコレクタ低抵抗取り出し領域等を下部電極（３）
として利用することになる。[0004] In recent years, Bi-CMOS integrated circuits in which bipolar elements and MOS elements are mixed have appeared, and there is a strong desire to incorporate capacitive elements into such devices. In this case, since the MOS element and the latter structure are similar, attempts have been made to use a gate oxide film as the dielectric thin film (4) and a gate electrode as the upper electrode (5). In this case, if the emitter of the NPN transistor and the source/drain region of the NchMOS are shared in order to simplify the process, it becomes impossible to use the emitter diffusion as the lower electrode (3) of the capacitive element. Therefore, regions formed before the emitter diffusion process, such as the P+ type isolation region (7) and the low resistance extraction region of the collector of an NPN transistor, are used as the lower electrode (3).
It will be used as.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記Ｐ
＋型分離領域（７）やコレクタ低抵抗取り出し領域は、
いずれも製造工程の前半から中盤にかけて形成するもの
であり、エミッタ拡散程表面濃度を上げることは困難で
ある。また、ゲート電極のポリシリコン層もＡｌ電極程
抵抗値を下げることができない。そのため容量の直列抵
抗が増大し、容量素子のＱの周波数特性が悪化する欠点
があった。[Problem to be solved by the invention] However, the above P
The + type isolation region (7) and collector low resistance extraction region are
Both are formed from the first half to the middle of the manufacturing process, and it is difficult to increase the surface concentration to the extent of emitter diffusion. Further, the resistance value of the polysilicon layer of the gate electrode cannot be lowered as much as the Al electrode. Therefore, there is a drawback that the series resistance of the capacitor increases and the frequency characteristic of the Q of the capacitor element deteriorates.
【０００６】[0006]
【課題を解決するための手段】本発明は上記課題に鑑み
成されたもので、同一基板（１３）上にバイポーラ素子
、ＭＯＳ素子、および容量素子を一体化したものにおい
て、ＮＰＮトランジスタのエミッタ拡散以外の工程で形
成した容量素子の下部電極領域（２７）と、下部電極領
域（２７）の表面を被覆する、ＭＯＳ素子のゲート酸化
膜（２４）と共用化した誘電体薄膜（２８）と、誘電体
薄膜（２８）上に形成した、ＭＯＳ素子のゲート電極（
２５）と共用化した上部電極（２９）と、下部電極領域
（２７）の表面にコンタクトする一方のＡｌ電極（３０
）と、上部電極（２９）にコンタクトする他方のＡｌ電
極（３１）とを有し、一方の電極（３０）と他方の電極
（３１）とを櫛歯状に配置することにより、周波数特性
に優れた容量素子を効率的に一体化するものである。[Means for Solving the Problems] The present invention has been made in view of the above-mentioned problems, and in which a bipolar element, a MOS element, and a capacitive element are integrated on the same substrate (13), the emitter diffusion of an NPN transistor is A lower electrode region (27) of the capacitive element formed in a process other than the above, and a dielectric thin film (28) shared with the gate oxide film (24) of the MOS element, which covers the surface of the lower electrode region (27). The gate electrode (of the MOS element) formed on the dielectric thin film (28)
25) and one Al electrode (30) in contact with the surface of the lower electrode region (27).
) and the other Al electrode (31) in contact with the upper electrode (29), and by arranging one electrode (30) and the other electrode (31) in a comb-like shape, the frequency characteristics can be improved. This efficiently integrates excellent capacitive elements.
【０００７】[0007]
【作用】本発明によれば、下部電極領域（２７）、誘電
体薄膜（２８）、および上部電極（２９）を他素子と共
用化できるので、専用工程を必要としないで一体化でき
る。また、一方の電極（３０）と他方の電極（３１）と
を櫛歯状に形成したので、電極の取り出し抵抗を低減で
きる。さらに、ゲートポリシリコンから成る上部電極（
２９）の上に他方の電極（３０）を配置したので、ゲー
ト酸化膜から成る誘電体薄膜（２８）を他の工程で露出
することなく、膜質を安定に保つことができる。According to the present invention, the lower electrode region (27), the dielectric thin film (28), and the upper electrode (29) can be shared with other elements, so they can be integrated without the need for a dedicated process. Further, since the one electrode (30) and the other electrode (31) are formed in a comb-teeth shape, the resistance to take out the electrodes can be reduced. In addition, an upper electrode made of gate polysilicon (
Since the other electrode (30) is placed on top of the gate oxide film (29), the dielectric thin film (28) made of the gate oxide film is not exposed in other steps, and the film quality can be kept stable.
【０００８】[0008]
【実施例】以下に本発明の一実施例を図面を参照しなが
ら詳細に説明する。図１はＮＰＮトランジスタ（１０）
、ＮｃｈＭＯＳ（１１）、および容量素子（１２）を示
す断面図である。同図において、（１３）はＰ型のシリ
コン半導体基板、（１４）は基板（１３）上に形成した
Ｎ型エピタキシャル層を貫通して複数の島領域を形成す
るＰ＋型分離領域、（１５）は基板（１３）と前記エピ
タキシャル層との間に埋め込まれたＮ＋型埋め込み層、
（１６）は基板（１３）と前記エピタキシャル層との間
に埋め込まれたＰ＋型埋め込み層、（１７）はＬＯＣＯ
Ｓ酸化膜である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Figure 1 shows an NPN transistor (10)
, an NchMOS (11), and a capacitive element (12). In the figure, (13) is a P-type silicon semiconductor substrate, (14) is a P+ type isolation region that penetrates the N-type epitaxial layer formed on the substrate (13) and forms a plurality of island regions, and (15) is an N+ type buried layer buried between the substrate (13) and the epitaxial layer;
(16) is a P+ type buried layer buried between the substrate (13) and the epitaxial layer, (17) is a LOCO
It is an S oxide film.
【０００９】ＮＰＮトランジスタ（１０）は、エピタキ
シャル層表面に形成したＰ型のベース領域（１７）、ベ
ース領域（１７）表面に形成したヒ素（Ａｓ）をドーパ
ントとするＮ＋型エミッタ領域（１８）、およびエピタ
キシャル層表面に形成した、エミッタ領域（１８）より
深いＮ＋型コレクタ低抵抗領域（１９）から成る。各領
域上にはＡｌ電極（２０）がコンタクトする。コレクタ
低抵抗領域（１９）は、リン（Ｐ）をドーパントとし拡
散時にエミッタ領域（１８）と同程度の不純物濃度（１
０２１ａｔｏｍｓ．ｃｍ−２）を与えられるが、熱拡散
によってその表面濃度はエミッタ領域（１８）より低下
している。望ましくは、Ｎ＋型埋め込み層（１５）と連
結するまで深く形成する。ベース領域（１７）表面のＰ
＋型ベースコンタクト領域（２１）はＰｃｈＭＯＳのソ
ース・ドレインを利用して形成されたものである。The NPN transistor (10) includes a P type base region (17) formed on the surface of the epitaxial layer, an N+ type emitter region (18) doped with arsenic (As) formed on the surface of the base region (17), and an N+ type collector low resistance region (19) formed on the surface of the epitaxial layer and deeper than the emitter region (18). An Al electrode (20) contacts each region. The collector low resistance region (19) is doped with phosphorus (P) and has an impurity concentration (1
021atoms. cm-2), but its surface concentration is lower than that of the emitter region (18) due to thermal diffusion. Desirably, it is formed deep enough to connect with the N+ type buried layer (15). P on the surface of the base region (17)
The + type base contact region (21) is formed using the source and drain of PchMOS.
【００１０】ＮｃｈＭＯＳトランジスタ（１１）は、エ
ピタキシャル層の導電型を反転させ、Ｐ＋型埋め込み層
（１６）と連結するＰ型ウェル領域（２２）と、Ｐ型ウ
ェル領域（２２）の表面に形成したＮ＋型のソース・ド
レイン領域（２３）と、ソース・ドレイン領域（２３）
で挟まれたウェル領域（２２）上にゲート酸化膜（２４
）を介して配設したポリシリコンから成るゲート電極（
２５）から成り、各ソース・ドレイン領域（２３）には
Ａｌ電極（２６）がオーミックコンタクトする。Ｎｃｈ
ＭＯＳ（１１）のソース・ドレイン領域（２３）はＮＰ
Ｎトランジスタ（１０）のエミッタ領域（１８）形成と
同時的に行なわれる。[0010] The NchMOS transistor (11) is formed by inverting the conductivity type of the epitaxial layer and forming a P-type well region (22) connected to the P+ type buried layer (16) and a surface of the P-type well region (22). N+ type source/drain region (23) and source/drain region (23)
A gate oxide film (24) is formed on the well region (22) sandwiched between
A gate electrode made of polysilicon (
25), and an Al electrode (26) is in ohmic contact with each source/drain region (23). Nch
The source/drain region (23) of the MOS (11) is NP
This is done simultaneously with the formation of the emitter region (18) of the N transistor (10).
【００１１】容量素子（１２）は、ＮＰＮトランジスタ
（１０）のＮ＋型コレクタ低抵抗領域（１９）と同時形
成されたＮ＋型の下部電極領域（２７）、下部電極領域
（２７）上にＮｃｈＭＯＳ（１１）のゲート酸化膜（２
４）と同時形成された膜厚数百Åのシリコン酸化膜（Ｓ
ｉＯ２）から成る誘電体薄膜（２８）、および誘電体薄
膜（２８）上にＮｃｈＭＯＳ（１１）のゲート電極（２
５）と同時形成された膜厚３０００〜６０００Åのポリ
シリコンから成る上部電極（２９）から成り、下部電極
領域（２７）上に第１のＡｌ電極（３０）が、上部電極
（２９）に第２のＡｌ電極（３１）がコンタクトする。
ＮＰＮトランジスタ（１０）のＮ＋型コレクタ低抵抗領
域（１９）と同時形成する下部電極領域（２７）は、先
にも述べたようにＮＰＮトランジスタ（１０）のエミッ
タ領域（１８）より表面濃度がやや低く、シート抵抗で
４０〜６０Ω／□の値を示す。また、ゲート電極（２５
）と同時形成される上部電極（２９）は、ゲート電極（
２５）と同様にリンドープを受け、シート抵抗で１０〜
３０Ω／□の値を示す。The capacitive element (12) includes an N+ type lower electrode region (27) formed simultaneously with the N+ type collector low resistance region (19) of the NPN transistor (10), and an NchMOS ( 11) gate oxide film (2)
A silicon oxide film (S) with a thickness of several hundred Å was formed simultaneously with 4).
dielectric thin film (28) consisting of iO2), and a gate electrode (28) of NchMOS (11) on the dielectric thin film (28).
5) and an upper electrode (29) made of polysilicon with a film thickness of 3,000 to 6,000 Å formed at the same time as the first Al electrode (30) on the lower electrode region (27), and a first Al electrode (30) on the upper electrode (29). No. 2 Al electrode (31) makes contact. As mentioned earlier, the lower electrode region (27) formed simultaneously with the N+ type collector low resistance region (19) of the NPN transistor (10) has a slightly higher surface concentration than the emitter region (18) of the NPN transistor (10). It has a low sheet resistance of 40 to 60Ω/□. In addition, the gate electrode (25
) is formed at the same time as the gate electrode (29).
25), it was doped with phosphorus and the sheet resistance was 10~
Indicates a value of 30Ω/□.
【００１２】図２は容量素子（１２）の上面図である。
一様に形成されたＮ＋型下部電極領域（２７）に対し、
上部電極（２９）が複数に分割され、分割された部分に
第１の電極（３０）がストライプ状に延在し、全長にわ
たって下部電極領域（２７）とオーミック接触している
。上部電極（２９）はＢＰＳＧ膜で覆われ、前記ＢＰＳ
Ｇ膜の開孔（スルーホール）を通して第２の電極（３１
）が上部電極（２９）にコンタクトし、上部電極（２９
）の全長にわたり第２の電極（３１）がストライプ状に
延在する。そして、第１と第２の電極（３０）（３１）
が相対向するように、櫛歯状に形成されている。FIG. 2 is a top view of the capacitive element (12). For the uniformly formed N+ type lower electrode region (27),
The upper electrode (29) is divided into a plurality of parts, and a first electrode (30) extends in a stripe shape in the divided parts and is in ohmic contact with the lower electrode region (27) over the entire length. The upper electrode (29) is covered with a BPSG film, and the BPS
The second electrode (31
) contacts the upper electrode (29), and the upper electrode (29
) The second electrode (31) extends in a stripe shape over the entire length of the electrode. and the first and second electrodes (30) (31)
They are formed in a comb-like shape so that they face each other.
【００１３】以上に説明した本発明の構成によれば、抵
抗値が高い下部電極領域（２７）および上部電極（２９
）に対して、抵抗値が極めて小さい第１の電極（３０）
と第２の電極（３１）の両方を櫛歯状にコンタクトさせ
たので、両者の取出し抵抗を低減できる。従って、容量
素子（１２）の直列抵抗を大幅に低減し、周波数特性を
向上できるものである。尚、上記実施例はコレクタ低抵
抗領域（１９）を用いたものについて説明したが、例え
ばＰ＋分離領域（１４）を利用したものについても同等
の効果が得られるのは明らかである。According to the configuration of the present invention described above, the lower electrode region (27) and the upper electrode (29) having a high resistance value are
), the first electrode (30) has an extremely small resistance value.
Since both the first electrode and the second electrode (31) are brought into contact in a comb-teeth shape, the extraction resistance of both can be reduced. Therefore, the series resistance of the capacitive element (12) can be significantly reduced and the frequency characteristics can be improved. Although the above embodiment has been described using the collector low resistance region (19), it is obvious that the same effect can be obtained by using, for example, the P+ isolation region (14).
【００１４】[0014]
【発明の効果】以上説明したように、本発明によれば、
下部電極領域（２７）、誘電体薄膜（２８）、および上
部電極（２９）を他の素子と工程を共用化できるので、
効率的に組み込むことができる利点を有する。また、第
１と第２の電極（３０）（３１）により下部電極領域（
２７）と上部抵抗（２９）の取出し抵抗を低減できるの
で、容量素子（１２）の直列抵抗を減じて周波数特性を
大幅に改善できる利点をも有する。[Effects of the Invention] As explained above, according to the present invention,
Since the lower electrode region (27), dielectric thin film (28), and upper electrode (29) can be shared with other elements,
It has the advantage of being able to be incorporated efficiently. In addition, the lower electrode area (
27) and the upper resistor (29), it also has the advantage of reducing the series resistance of the capacitive element (12) and significantly improving frequency characteristics.
【図１】本発明を説明するための断面図である。FIG. 1 is a sectional view for explaining the present invention.
【図２】本発明を説明するための平面図である。FIG. 2 is a plan view for explaining the present invention.
【図３】従来例を説明する断面図である。FIG. 3 is a sectional view illustrating a conventional example.
Claims (3)
に形成した逆導電型のエピタキシャル層と、前記エピタ
キシャル層を分離する一導電型の分離領域と、前記分離
領域で島状に分離された複数の島領域と、前記島領域の
底部に埋め込まれた一導電型の埋め込み層と、前記島領
域の表面に形成した一導電型のベース領域と、前記ベー
ス領域の表面にＭＯＳ素子のソース・ドレイン領域と同
時形成された逆導電型のエミッタ領域と、他の島領域の
表面に形成した、前記エミッタ領域より深く且つ高比抵
抗の下部電極領域と、前記下部電極領域の表面を被覆す
る前記ＭＯＳ素子のゲート絶縁膜と同時形成された誘電
体薄膜と、前記誘電体薄膜の上に前記ＭＯＳ素子のゲー
ト電極と同時形成された上部電極と、前記下部電極領域
の表面にオーミック接触する一方の電極と、前記上部電
極にコンタクトする他方の電極とを備え、前記一方の電
極と他方の電極とを互いに対向するように櫛歯状に配置
したことを特徴とする半導体集積回路。1. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, an isolation region of one conductivity type that separates the epitaxial layer, and a semiconductor substrate separated into islands by the isolation region. a plurality of island regions, a buried layer of one conductivity type buried in the bottom of the island region, a base region of one conductivity type formed on the surface of the island region, and a source of a MOS element on the surface of the base region.・An emitter region of the opposite conductivity type formed simultaneously with the drain region, a lower electrode region deeper than the emitter region and having a higher specific resistance formed on the surface of the other island region, and covering the surface of the lower electrode region. a dielectric thin film formed at the same time as the gate insulating film of the MOS element; an upper electrode formed on the dielectric thin film at the same time as the gate electrode of the MOS element; and one side in ohmic contact with the surface of the lower electrode region. What is claimed is: 1. A semiconductor integrated circuit comprising: an electrode; and another electrode in contact with the upper electrode, the one electrode and the other electrode being arranged in a comb-teeth shape so as to face each other.
ジスタ素子のコレクタ低抵抗領域と同時形成された逆導
電型の領域であることを特徴とする請求項１記載の半導
体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the lower electrode region is a region of an opposite conductivity type formed simultaneously with a collector low resistance region of a bipolar transistor element.
シリコンであることを特徴とする請求項第１項記載の半
導体集積回路。3. The semiconductor integrated circuit according to claim 1, wherein the upper electrode is made of phosphorus-doped polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12112691A JP2627369B2 (en) | 1991-05-27 | 1991-05-27 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12112691A JP2627369B2 (en) | 1991-05-27 | 1991-05-27 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04348563A true JPH04348563A (en) | 1992-12-03 |
| JP2627369B2 JP2627369B2 (en) | 1997-07-02 |
Family
ID=14803527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12112691A Expired - Lifetime JP2627369B2 (en) | 1991-05-27 | 1991-05-27 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2627369B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6204104B1 (en) | 1997-11-21 | 2001-03-20 | Nec Corporation | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-05-27 JP JP12112691A patent/JP2627369B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6204104B1 (en) | 1997-11-21 | 2001-03-20 | Nec Corporation | Semiconductor device and manufacturing method thereof |
| US6307227B2 (en) | 1997-11-21 | 2001-10-23 | Nec Corporation | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2627369B2 (en) | 1997-07-02 |
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