JPS60126864A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60126864A JPS60126864A JP58234563A JP23456383A JPS60126864A JP S60126864 A JPS60126864 A JP S60126864A JP 58234563 A JP58234563 A JP 58234563A JP 23456383 A JP23456383 A JP 23456383A JP S60126864 A JPS60126864 A JP S60126864A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buried
- epitaxial layer
- layers
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.
従来、半導体層の同一島内にトランジスタを２個組込ん
だ所！ＩＩ ＣＦＬ回路（コレクター・ファンクション
・ロジ、り回路）がら表る半導体装置として、例えば第
１図（Ａ）、に示す構造のものが使用されている。図中
１は、Ｐ導−形の半導体基板である。半導体基板１上に
は、所定間隔で設置したＮ＋埋込層２，２を介して、Ｎ
−半導体層からなるエピタキシャル層３が形成すしてい
る。エピタキシャル層３には、その主面がらＮ＋埋込層
２，２に接続するようにしてＮ土層４．４が形成されて
いる。耐層４，４とＮ＋埋込層２，２で囲まれたエピタ
キシャル層３内には、その主面から所定の拡散深さでＰ
形のペース層５が形成されている。ペース層５内には、
Ｎ形のエミッタ層６，６が所定間隔で形成されてムる。Conventionally, two transistors were built into the same island of a semiconductor layer! II As a semiconductor device representing a CFL circuit (collector function logic circuit), for example, one having the structure shown in FIG. 1(A) is used. In the figure, 1 is a P-type semiconductor substrate. On the semiconductor substrate 1, N+ buried layers 2, 2 are provided at predetermined intervals.
- An epitaxial layer 3 consisting of a semiconductor layer is being formed. An N soil layer 4.4 is formed on the epitaxial layer 3 so as to be connected to the N+ buried layers 2, 2 from its main surface. In the epitaxial layer 3 surrounded by the resistive layers 4, 4 and the N+ buried layers 2, 2, P is formed at a predetermined diffusion depth from its main surface.
A shaped paste layer 5 is formed. In the pace layer 5,
N-type emitter layers 6, 6 are formed at predetermined intervals.
エミッタ層６，６の表面には、第１、第２のエミッタ電
極７ａ 、７ｂが形成され、１層４．４の表面には、第
１、第２のコレクタ電極ａｈ、８ｂが形成され、ペース
層５０表面には、ペース電極９が形成されている。なお
、同図１０は、エピタキシャル層３に半導体基板１に達
する拡散深さで形成されたアイソレーション層である。First and second emitter electrodes 7a and 7b are formed on the surfaces of the emitter layers 6 and 6, and first and second collector electrodes ah and 8b are formed on the surface of the first layer 4.4, A pace electrode 9 is formed on the surface of the pace layer 50. Note that FIG. 10 shows an isolation layer formed in the epitaxial layer 3 with a diffusion depth reaching the semiconductor substrate 1.
このように構成された半導体装置１５は、同図（Ｂ）に
示す如く、エピタキシャル層３の同一島内に２個トラン
ジスタ１１．１２を組込んだ回路を形成している。The semiconductor device 15 configured in this manner forms a circuit in which two transistors 11 and 12 are incorporated in the same island of the epitaxial layer 3, as shown in FIG. 3B.
而して、このような半導体装置１５の製造は、第２図に
示す如く、半導体基板１の所定領域に耐埋込層２，２及
びＰ＋埋込層１０ａ、１０ａを形成した後、その表面に
エピタキシャル成長によってエピタキシャル層３を積層
する。このため、エピタキシャル成長を行う際にＮ＋埋
込層２．２中の不純物が外部拡散によって飛散する。As shown in FIG. 2, manufacturing of such a semiconductor device 15 involves forming anti-buried layers 2, 2 and P+ buried layers 10a, 10a in predetermined regions of a semiconductor substrate 1, and then depositing the surface Then, an epitaxial layer 3 is laminated by epitaxial growth. Therefore, during epitaxial growth, impurities in the N+ buried layer 2.2 are scattered by external diffusion.
このため、Ｎ＋埋込層２，２間にできる所謂コレクタ抵
抗（Ｒｃｃ ）の値が低下する。その結果、所定の素子
！！４ｆ性が得られかい問題があった。Therefore, the value of the so-called collector resistance (Rcc) formed between the N+ buried layers 2 is reduced. As a result, a given element! ! There was a problem that 4f properties could not be obtained.
本発明は、コレクタ間の抵抗を所定値に設定することに
より、素子特性の向上を達成した半導体装置を提供する
ことをその目的とするものである。An object of the present invention is to provide a semiconductor device in which device characteristics are improved by setting the resistance between the collectors to a predetermined value.
本発明は、埋込層間に半導体基板と反対導電形の不純物
領域を設けたことによシ、コレクタ間の抵抗値を所定値
に設定して素子特性の向上を達成した半導体装置である
。The present invention is a semiconductor device in which the resistance value between collectors is set to a predetermined value by providing an impurity region of a conductivity type opposite to that of the semiconductor substrate between buried layers, thereby achieving improvement in device characteristics.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第３図は、本発明の一実施例の概略構成を示す説明図で
おる。図中２０は、Ｐ導電形の半導体基板である。半導
体基板２０上には、所定間隔で設置したＮ＋埋込層２１
．２１−を介してＮ−半導体層からなるエピタキシャル
層２２が形成されている。耐埋込層２１．２１間の半導
体基板２０の領域には、Ｐ導電形のコレクタ間抵抗制御
層２３が形成されている。コーレクタ間抵抗制御層２３
は、半導体基板２０と同じ導電形に設定されておシ、そ
の不純物濃度を第５図中特性！（Ｂ）、（Ｃ）のように
所定の値に設定することによシ、後述する所謂コレクタ
間抵抗（Ｒｃｅ ）の値を所定値に設定するものである
。FIG. 3 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. In the figure, 20 is a P conductivity type semiconductor substrate. On the semiconductor substrate 20, N+ buried layers 21 are provided at predetermined intervals.
．． An epitaxial layer 22 made of an N-semiconductor layer is formed via a layer 21-. A P conductivity type inter-collector resistance control layer 23 is formed in a region of the semiconductor substrate 20 between the buried-proof layers 21 and 21. Inter-collector resistance control layer 23
is set to have the same conductivity type as the semiconductor substrate 20, and its impurity concentration is shown in FIG. By setting the resistor to a predetermined value as shown in (B) and (C), the value of the so-called collector-to-collector resistance (Rce), which will be described later, is set to a predetermined value.
よって、コレクタ間抵抗制御層２３の不純物濃度は、製
造しようとする半導体装置の仕′ＪｒＭＫ応じて、特に
Ｎ十埋込層２１．２１の製造時の濃度低下を考慮して設
定するのが望ましい。エピタキシャル層２２には、その
主面からＮ＋埋込層ｊ １ ａ ２１に接続するように
して耐層２４．２４が形成されている。１層２４．２４
とＮ＋埋込層ｘｌ 、２１で囲まれたエピタキシャル層
２２内には、その主面から所定の拡散探さでＰ形のペー
ス層２５が形成されている。ペース層２５内には、Ｎ形
のエミッタ層２６．２６が所定間隔で形成されている。Therefore, it is desirable to set the impurity concentration of the inter-collector resistance control layer 23 according to the specifications of the semiconductor device to be manufactured, especially taking into account the concentration drop during the manufacture of the N buried layers 21 and 21. . A breakdown layer 24.24 is formed in the epitaxial layer 22 so as to be connected to the N+ buried layer j 1 a 21 from its main surface. 1 layer 24.24
In the epitaxial layer 22 surrounded by the N+ buried layer xl and 21, a P-type space layer 25 is formed with a predetermined diffusion distance from its main surface. Within the space layer 25, N-type emitter layers 26, 26 are formed at predetermined intervals.
エミッタＮｌ２６，２６、ペース層２５．１層３４．２
４の表面には、エミッタ電極２７ｍ、２７ｂ、、ぺ・−
スミ極２８、コレクタ電極２９ｍ、２９ｂが夫々形成さ
れている。なお、同図中３０は、半導体基板２０に達す
る拡散深さでエピタキシャル層２２に形成されたアイソ
レーション層である。Emitter Nl26, 26, pace layer 25.1 layer 34.2
4, emitter electrodes 27m, 27b, pe-
A sum pole 28 and collector electrodes 29m and 29b are formed, respectively. Note that 30 in the figure is an isolation layer formed in the epitaxial layer 22 with a diffusion depth reaching the semiconductor substrate 20.
このように構成された半導体装置Ｑによれば、第５図に
特性線（Ｂ ）、（Ｃ）で示す如く、コレクタ間抵抗制
御層２３を設けているので、コレクタ間の半導体基板２
０とエピタキシャル層２２の界面の地点（Ｘ）における
不純物濃度を、特性線（Ａ）にて示す従来の半導体装置
の場合よシも高く設定することができる。このため、半
導体装置４０−の製造工程でＮ−１−＝埋込層２１の不
純物濃度が外部拡散によって低下しても、コレクタ間の
抵抗（Ｒｅｅ ）の値を常に所定のものに設定すること
ができる。これは、耐埋込層２ノの形成後にエピタキシ
ャル成長を行った際に、コレクタ間抵抗制御層２３中の
不純物がエピタキシャル層２２中に再分布するためであ
兎。According to the semiconductor device Q configured in this way, as shown by characteristic lines (B) and (C) in FIG. 5, since the inter-collector resistance control layer 23 is provided, the semiconductor substrate 2 between the collectors
The impurity concentration at the point (X) at the interface between the epitaxial layer 22 and the epitaxial layer 22 can be set higher than that in the conventional semiconductor device shown by the characteristic line (A). Therefore, even if the impurity concentration of the N-1-=buried layer 21 decreases due to external diffusion in the manufacturing process of the semiconductor device 40-, the value of the resistance (Ree) between the collectors must always be set to a predetermined value. I can do it. This is because impurities in the inter-collector resistance control layer 23 are redistributed into the epitaxial layer 22 when epitaxial growth is performed after the formation of the anti-buried layer 2.
その結果、素子特性の向上を達成するこ゛とができる。As a result, it is possible to improve device characteristics.
なお、コレクタ間抵抗制御層２３の形成は、例えば次の
ようにして行う。先ず、第４図（Ａ）に示す如く、Ｐ形
半導体基板２０の所定領域に、耐埋込層２１，２１及び
アイソレーション層３０となるＰ＋層３０ａを所定間隔
で形成する。Note that the inter-collector resistance control layer 23 is formed, for example, as follows. First, as shown in FIG. 4(A), P+ layers 30a, which will become the anti-buried layers 21 and 21 and the isolation layer 30, are formed in predetermined regions of the P-type semiconductor substrate 20 at predetermined intervals.
次いで、同図（Ｂ）に示す如く、耐埋込層２１゜２１．
２層３０ａを含む半導体基板２０の表面に１酸化膜３１
を形成する。次いで、酸化膜３１上に計理込層ｚｌ、２
１間の領域に対応する部分に、窓３２を有するレジスト
膜３３を形成し、このレジスト膜３３をマスクにして例
えばはロン３４を半導体基板２０中に注入する。Next, as shown in FIG.
A single oxide film 31 is formed on the surface of the semiconductor substrate 20 including the second layer 30a.
form. Next, a calculation layer zl, 2 is formed on the oxide film 31.
A resist film 33 having a window 32 is formed in a portion corresponding to the region between 1 and 1, and using this resist film 33 as a mask, for example, ions 34 are implanted into the semiconductor substrate 20.
次いで、レジスト膜３３を除去した後、熱処理を施して
同図（Ｃ）に示す如く、耐埋込層２１゜２１間の半導体
基板２０内にコレクタ間抵抗制御層２３を形成する。然
る後、酸化膜３１を除去してから同図（Ｄ）に示す如く
、エピタキシャル成長により半導体基板２０上にエピタ
キシャル層２２を形成する。この後、エピタキシャル層
２２内にづ−ス層２５等を形成して上述の半導体装置Ｑ
が組立てられる。Next, after removing the resist film 33, a heat treatment is performed to form an inter-collector resistance control layer 23 in the semiconductor substrate 20 between the buried resistant layers 21 and 21, as shown in FIG. Thereafter, the oxide film 31 is removed, and then an epitaxial layer 22 is formed on the semiconductor substrate 20 by epitaxial growth, as shown in FIG. 3(D). Thereafter, a base layer 25 and the like are formed in the epitaxial layer 22 to form the semiconductor device Q described above.
is assembled.
以上説明した如く、本発明に係る半導体装置によれば、
コレクタ間の抵抗値を所定値に設定して、素子特性を向
上させることができるものである。As explained above, according to the semiconductor device according to the present invention,
By setting the resistance value between the collectors to a predetermined value, the device characteristics can be improved.
第１図（Ａ）は、従来の半導体装置の概略構成を示す説
明図、同図（Ｂ）は、同半導体装置の回路図、第２図は
、従来の半導体装置の問題点を示す説明図、第３図は、
本発明の一実施例の概略構成を示す説明図、第４図（Ａ
）乃至同図（Ｄ）は、同実施例の半導体装置の製造工程
の主な部分を示す説明図、第５図は、基板の深さとバル
ク濃度の関係を示す説明図である。
２０・・・半導体基板、２１・・・耐埋込層、２２・・
・エピタキシャル層、２３・・・コレクタ間抵抗制御層
、２４・・・耐層、２５・・・ペース層、２６・・・エ
ミ゛ツタ層、２７ｈ、２７ｂ・・・エミッタ電極、２８
・・・へ” ’ｆｌＬ’ＦＭ、２９ ａ ｙ ２９ ｂ
・・・コレクタを極、３０・・・アイソレーション層、
４ｏ・・・半導体装置。
出願人代理人 弁理士 鈴 江 武 彦第４図
第５図
〔ｃｒｒｒ ３：
林碌３（Ｘｊ）”“２FIG. 1(A) is an explanatory diagram showing the schematic structure of a conventional semiconductor device, FIG. 1(B) is a circuit diagram of the same semiconductor device, and FIG. 2 is an explanatory diagram showing problems of the conventional semiconductor device. , Figure 3 is
An explanatory diagram showing a schematic configuration of an embodiment of the present invention, FIG.
) to (D) are explanatory diagrams showing the main parts of the manufacturing process of the semiconductor device of the same example, and FIG. 5 is an explanatory diagram showing the relationship between the depth of the substrate and the bulk concentration. 20... Semiconductor substrate, 21... Burying resistant layer, 22...
・Epitaxial layer, 23... Inter-collector resistance control layer, 24... Resistance layer, 25... Space layer, 26... Emitter layer, 27h, 27b... Emitter electrode, 28
...” 'flL'FM, 29 a y 29 b
...Collector as pole, 30...Isolation layer,
4o...Semiconductor device. Applicant's representative Patent attorney Takehiko Suzue Figure 4 Figure 5 [crrr 3: Lin Roku 3 (Xj)'' 2
Claims (1)
の埋込層を介して形成された半導体層と、該埋込層間の
前・起生導体基板に同導電形で形成されたコレクタ間抵
抗制御層と、前記半導体層の主面から前記埋込層と同導
電形で前記埋込層に接続、するよう□に延出する不純物
領域と、該不純物領域で囲まれた前記半導体層内に反対
導電形で形成されたペース層と、該ペース層内に反対導
電形で所間隔で形成されたエミツタ層とを具備すること
を特徴とする半導体装置。A semiconductor layer formed on a semiconductor substrate of one conductivity type through buried layers of the opposite conductivity type provided at predetermined intervals, and a collector formed of the same conductivity type on a previous conductive substrate between the buried layers. an impurity region extending from the main surface of the semiconductor layer in a square shape so as to be connected to the buried layer with the same conductivity type as the buried layer; and the semiconductor layer surrounded by the impurity region. 1. A semiconductor device comprising: a paste layer formed therein with an opposite conductivity type; and an emitter layer formed with an opposite conductivity type at a predetermined interval within the paste layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58234563A JPS60126864A (en) | 1983-12-13 | 1983-12-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58234563A JPS60126864A (en) | 1983-12-13 | 1983-12-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60126864A true JPS60126864A (en) | 1985-07-06 |
Family
ID=16972971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58234563A Pending JPS60126864A (en) | 1983-12-13 | 1983-12-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60126864A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962913A (en) * | 1996-01-19 | 1999-10-05 | Mitsubishi Denki Kabushiki Kaisha | Bipolar transistor having a particular contact structure |
| JP2009021313A (en) * | 2007-07-11 | 2009-01-29 | Hitachi Ltd | Semiconductor device |
| CN102496626A (en) * | 2011-12-30 | 2012-06-13 | 清华大学 | Silicon germanium heterojunction bipolar transistor structure |
-
1983
- 1983-12-13 JP JP58234563A patent/JPS60126864A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962913A (en) * | 1996-01-19 | 1999-10-05 | Mitsubishi Denki Kabushiki Kaisha | Bipolar transistor having a particular contact structure |
| JP2009021313A (en) * | 2007-07-11 | 2009-01-29 | Hitachi Ltd | Semiconductor device |
| CN102496626A (en) * | 2011-12-30 | 2012-06-13 | 清华大学 | Silicon germanium heterojunction bipolar transistor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3274461A (en) | High frequency and power field effect transistor with mesh-like gate structure | |
| JPS60126864A (en) | Semiconductor device | |
| JP3253611B2 (en) | Circuit structure having bipolar transistor and method of manufacturing the same | |
| JPH02229437A (en) | Manufacture of high performance bipolar structure | |
| EP0182400A1 (en) | Method of manufacturing a bipolar transistor having emitter series resistors | |
| JPS5969943A (en) | Manufacture of semiconductor device | |
| JPS61284961A (en) | Semiconductor device | |
| JPH07221116A (en) | Transistor | |
| JPH07169771A (en) | Semiconductor device and its manufacture | |
| US3298082A (en) | Method of making semiconductors and diffusion thereof | |
| JPS6174361A (en) | Buried resistance semiconductor device | |
| JPS5832455A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH01225155A (en) | Bipolar semiconductor integrated circuit device and manufacture thereof | |
| JPH0312782B2 (en) | ||
| JPS63136668A (en) | Manufacture of semiconductor device | |
| JPS61284960A (en) | Semiconductor device | |
| JPS59111364A (en) | Semiconductor device | |
| JPH0587974B2 (en) | ||
| JPH01273353A (en) | Bipolar transistor and manufacture thereof | |
| JPS60229373A (en) | Semiconductor device | |
| JPH05243243A (en) | Semiconductor device and manufacture thereof | |
| JPS6014465A (en) | Manufacture or semiconductor integrated circuit | |
| JPS63152170A (en) | Manufacture of semiconductor device | |
| JPS6095939A (en) | Manufacture of semiconductor integrated circuit | |
| JPS58135669A (en) | Manufacture of semiconductor device |