JPS60105041A - 加算器 - Google Patents

加算器

Info

Publication number
JPS60105041A
JPS60105041A JP21363183A JP21363183A JPS60105041A JP S60105041 A JPS60105041 A JP S60105041A JP 21363183 A JP21363183 A JP 21363183A JP 21363183 A JP21363183 A JP 21363183A JP S60105041 A JPS60105041 A JP S60105041A
Authority
JP
Japan
Prior art keywords
block
carry
bit
adder
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21363183A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0218727B2 (enrdf_load_stackoverflow
Inventor
Takeshi Shindo
新藤　猛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21363183A priority Critical patent/JPS60105041A/ja
Publication of JPS60105041A publication Critical patent/JPS60105041A/ja
Publication of JPH0218727B2 publication Critical patent/JPH0218727B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP21363183A 1983-11-14 1983-11-14 加算器 Granted JPS60105041A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21363183A JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21363183A JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Publications (2)

Publication Number Publication Date
JPS60105041A true JPS60105041A (ja) 1985-06-10
JPH0218727B2 JPH0218727B2 (enrdf_load_stackoverflow) 1990-04-26

Family

ID=16642350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21363183A Granted JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Country Status (1)

Country Link
JP (1) JPS60105041A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047976A (en) * 1988-03-25 1991-09-10 Fujitsu Limited Logic circuit having carry select adders
US5434810A (en) * 1988-04-20 1995-07-18 Fujitsu Limited Binary operator using block select look ahead system which serves as parallel adder/subtracter able to greatly reduce the number of elements of circuit with out sacrifice to high speed of computation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047976A (en) * 1988-03-25 1991-09-10 Fujitsu Limited Logic circuit having carry select adders
US5434810A (en) * 1988-04-20 1995-07-18 Fujitsu Limited Binary operator using block select look ahead system which serves as parallel adder/subtracter able to greatly reduce the number of elements of circuit with out sacrifice to high speed of computation

Also Published As

Publication number Publication date
JPH0218727B2 (enrdf_load_stackoverflow) 1990-04-26

Similar Documents

Publication Publication Date Title
US5151875A (en) MOS array multiplier cell
JP3144967B2 (ja) 半導体集積回路およびその製造方法
US4363107A (en) Binary multiplication cell circuit
EP1475697A1 (en) Arithmetic circuit
JPH01174011A (ja) 集積回路
JPS63102510A (ja) 排他的ｏｒゲートおよび／または排他的ｎｏｒゲートを構成する組合せ回路
JPS60116034A (ja) 加算回路
US4860242A (en) Precharge-type carry chained adder circuit
JPH0225537B2 (enrdf_load_stackoverflow)
US4905179A (en) CMOS cell for logic operations with fast carry
JPH0477931B2 (enrdf_load_stackoverflow)
JPS60105041A (ja) 加算器
JPH11143686A (ja) 部分積生成回路
JPH01243117A (ja) ２進計算回路
JPH07202680A (ja) 基本論理セル回路
US5422581A (en) Gate array cell with predefined connection patterns
CN101799747A (zh) 一种基于可逆逻辑的算术逻辑单元alu
JPH0778068A (ja) 半導体集積回路
JP3137629B2 (ja) 桁上げ‐セーブ算術演算機構に対する加算器セル
JPS63193229A (ja) 加算回路
JPH0142431B2 (enrdf_load_stackoverflow)
JPH04227534A (ja) アレイ乗算器
JP2508041B2 (ja) インクリメント回路
JP2002305439A (ja) プログラマブル論理回路および半導体装置
JPS60140425A (ja) キヤリ−回路