JPS6010350A - Test equipment of error processing function of computer - Google Patents

Abstract

PURPOSE:To check with high quality by storing revisably information designating a function circuit to which a pseudo error signal is to be supplied and information designating the period of the signal is supplied to control the pseudo error signal to be supplied to each function circuit. CONSTITUTION:An output of a decoder 3 is inputted to AND gates G1-Gn based on information data in a register 2 by a test start signal, and a timing pulse ERP from an error generating time control circuit 7 based on the information data in registers 4, 5 is inputted to the AND gates G1-Gn. When, e.g., the AND gate G1 is brought into the permissible state through the status combination of the decode output and the timing pulse ERP from the decoder 3, the pseudo error signal from a pseudo error signal generating circuit EG1 is supplied to the function circuit in a computer 10 via the AND gate G1 and when the result of operating processing is based on the error processing function, the circuit is discriminated as normal.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention applies a pseudo error signal to each functional circuit in a computer to perform a PA test on the error processing function of the computer.

(2) Background of the technology In recent years, in order to improve the reliability of bee meter systems, various types of error checking have been performed in addition to the original arithmetic processing of computers, and error handling functions have been developed to perform recalculation (recovery) when errors occur. , the so-called RAS (R
availability
5service ability) It has become essential to enhance the functionality. In a computer system that has this RAS function, it is possible to check the original functions of the computer system in a normal state by checking the operation according to a program such as a commonly performed function test. It is not possible to confirm the validity of processing for the state (error processing).

Therefore, the numbing machine is operated while an artificially generated pseudo error signal is applied to each functional circuit such as a register in IT, and the error processing function described above is activated based on the arithmetic processing result in that case. I am checking to see if it is normal.

By the way, this error processing function depends on the hardware inside the divider, that is, the configuration of the functional circuit, and although the logic specifications are unified among various types of computers,
Different functional circuit configurations result in different error handling.

As a result, the error handling function cannot be checked according to a unified check specification, but is currently performed according to a predetermined check specification for each calculation (completed).

(3) Prior Art and Problems Conventionally, the following methods have been used to check the error handling function of a computer.

First, clip the signal line connected to the functional circuit that pulls the register, etc., forcefully hold the functional circuit in an error state, activate the calculation, and process the calculation. The so-called manual method checks based on the results.In addition, a pseudo-error signal generation circuit is installed in the computer (corresponding to each functional circuit to be pulled), and the pseudo-error signal is sequentially detected according to a simulation program created based on the functional circuit configuration. This is a method in which a pseudo error signal output from a signal generation circuit is applied to each functional circuit and checked based on the result of arithmetic processing in that case.

However, in the above-mentioned manual method, if the computer system is not large, it takes a lot of time to check, and it is not possible to perform a sufficient check within a limited time. In addition, in the method using the above simulation program, even if the error occurs in the same functional circuit, the error processing may differ depending on the calculation processing state of the computer, that is, which instruction is being executed. If individual errors including such cases are assumed, the simulation program will take up an enormous amount of time, and there is a problem in that it takes a lot of man-hours to create this program.

(4) Purpose of the Invention The present invention has been made in view of the above points, and it is an object to easily realize high-quality checking under various error conditions when checking the error processing function of a computer. The purpose is to provide an error handling test device that can perform the following tasks.

(5) Structure of the Invention In order to achieve the above object, the present invention provides a device for testing the error handling function of a computer by applying a pseudo error signal to each functional circuit in the computer. storing information specifying the functional circuit to which the signal should be applied;
A first storage means that allows the information to be updated arbitrarily; and a second storage means that stores information for specifying a poetry period in which a pseudo error signal should not be applied, and that allows the information to be updated arbitrarily.
storage means, and application of the pseudo error signal to each functional circuit is controlled based on each piece of information stored in the first and second storage means.

(6) Examples of the invention Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of an error handling function testing device according to the present invention. ,・In the same figure, 10
is a computer that operates according to an independent program, and each functional circuit such as a register in J3 in this δ1 calculator 1o (
Pseudo error signal generation circuit E corresponding to hardware)
G+, EG2.

..., EGn are provided. The pseudo error signals output from each pseudo error signal generating circuit are applied to the corresponding functional circuits via AND gates G+, G2, . . . Gn.

On the other hand, 1 is a console where the operator performs input operations, etc., 2 is a register that stores information specifying the functional circuit to which the pseudo error signal from the pseudo error generating circuit is applied, and the information data of register 2 is Decoder 3
J, r is converted into an 11-bit binary number, and this n p1
− Each binary number] ~ is an and gate G+, G2...
・, Qn are respectively input. 4 is a register that stores timing information at which the pseudo error signal should be applied; 5 is a register that stores information on the minimum time interval (for example, 1 second) at which the pseudo error signal is applied;
The timing information and minimum time interval information stored in the registers 4 and 5 are input to the error occurrence timing control circuit 7 along with the machine cycle data from the computer system cycle control circuit 6; Based on the above data, a timing pulse ERP is generated to indicate when an error has occurred. Specifically, the timing pulse ERP is generated at a time interval that is an integral multiple of the minimum time interval.

In this way, the timing pulse ERP generated from the error occurrence timing control circuit 7 is controlled by the AND gate G1°G2. ...
It is input to each of Gn.

The contents of each of the registers 2, 4.5 are input by an operator from the console 1. Further, a register 2 that stores information specifying a functional circuit to which a pseudo error signal should be applied and a register 4 that stores timing information to which a pseudo error signal should be applied are each connected to a data update circuit 8 such as an incrementer. and 9, the information content is updated. The data updating circuits 8 and 9 may operate according to, for example, a certain program (or may perform a certain, for example, increment operation based on an instruction from the console 1).

Note that the second storage means according to the present invention is constituted by a register 4, a register 5, and a data update circuit 9.

Also, while the registers 2.4.5, decoder 3, and data update circuits 8 and 9 are configured in an independent microprocessor, the el! System cycle control circuit 6, error occurrence timing control circuit 7, pseudo error signal Bi times! fJ
EG+, EQ2, -EGn, 7-game 1-G+
, G2-Qn are configured within the CPU on the computer 10 side.

Next, the operation of the apparatus shown in FIG. 1 will be explained.

First, corresponding information data is input from the console 1 to each register 2, 4.5 based on an input operation by operator A. Therefore, when the star 1 signal to start the test is issued, the computer 10 starts operating according to its own function test program, and the decoded output from the decoder 3 based on the information data in the register 2 is sent to each AND gate G.
A timing pulse ERP from the error occurrence timing control circuit 7 based on the information data in the registers 4 and 5 is input to each AND gate GI to Qn.

Here, if the AND gate G1 becomes an allowable state due to the combination of the decoded output from the decoder 3 and the timing pulse ERP, the pseudo error signal generating circuit EG
The pseudo error signal from + is applied to the corresponding functional circuit in the computer 10 via the AND gate G1. and,
Check whether the arithmetic processing result of the computer 10 in a state where a pseudo-error signal is applied to the device n and the circuit concerned is originally based on the error processing function when the device n and the circuit become abnormal (function test program If it is determined that the error processing function is based on the error processing function (operation of the error processing program within the system), it is determined that the error processing function is operating normally.

If the information contents of each register 2, 4.5 are fixed, an error similar to the above will occur when the timing pulse ERP
occurs in the computer 10 each time an error occurs, and the error handling function at that time can be confirmed in the same way as above.

Furthermore, if the data update circuit 9 sequentially increments the information data in the register 4 at a predetermined synchronization, the output synchronization of the timing pulse changes accordingly, and even if an error occurs in the same functional circuit, the computer 10 can perform various commands. You can check the error handling function when running . Furthermore, if the data update circuit 8 sequentially increments the information data in the register 2 with a predetermined synchronization, the decoded output from the decoder 3 will change accordingly, and a pseudo error signal will be sent to various functional circuits in the computer 10. is applied, and various error handling functions corresponding to it can be confirmed.

As described above, according to this embodiment, =+pseudo error signal generation circuits EG+ to E corresponding to each functional circuit in the old Io
At the same time, the registers 2, 4, 5 that store each specified information, the data update circuits 8, 9, etc. that update the contents are configured in hardware on the S1 calculation system side, and the Because it is configured as a Also, gt n m1
Even if the model of 0 changes, if the corresponding pseudo error signal generation circuit etc. and each register etc. are drawn as shown in Fig. 1, it can be done without creating a special operating program.
Various errors! You can check the functionality.

(7) Effects of the Invention As explained in detail above, according to the present invention, when checking the single processing function of a computer, high quality checking can be easily realized under various error conditions. This has the effect of making it possible to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Console 2,4.5...Register 3...
・Decoder 6... Computer system cycle control circuit 7... Error occurrence timing control circuit 8.9... Data update circuit 10... Computer EG+~EGn... Pseudo error signal generation circuit G+~Q
n...and gate

Claims (1)

[Claims] A device for testing the error processing function of a computer by applying a pseudo error signal to each functional circuit in a computer stores information specifying the functional circuit to which the pseudo error signal is to be applied, and stores the information arbitrarily. The first thing that made it possible to update
and a second storage means that stores information specifying the timing at which the pseudo error signal is applied and allows the information to be updated at will, and the first and second storage means are provided. An error processing function testing device for a computer, characterized in that application of the pseudo error signal to each functional circuit is controlled based on each piece of information stored in the means.