JPH01217645A - Generating system for pseudo malfunction of microprocessor - Google Patents

Abstract

PURPOSE:To generate a pseudo malfunction of a microprocessor in the proper timing and with the proper contents by providing the malfunction generating instruction information and the malfunction contents specifying information that can be controlled by software. CONSTITUTION:A switch signal S1 which decides whether a microprocessor should be set in an execution mode for normal actions only or a monitor mode which can perform a pseudo action is supplied to an execution/monitor mode switch terminal 2 of a microprocessor chip 1. While a register 3 which can be controlled by software serves as a malfunction generation instructing information means and a malfunction contents specifying information memory means to store the malfunction generation instructing information showing the execution of a pseudo malfunction and the malfunction contents specifying information showing the contents of the pseudo malfunction. As described above, the malfunction generation instruction information and the malfunction contents specifying information which can be controlled by software are provided. Thus it is possible to generate a pseudo malfunction of a microprocessor in the proper timing and with the proper contents.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for generating a pseudo-malfunction in a microprocessor, and in particular, a method for generating a pseudo-malfunction in a microprocessor for testing error recovery operation by causing a pseudo-malfunction in a microprocessor. Regarding the method.

[Conventional technology]

In a dual microprocessor configuration, one microprocessor performs a pseudo-malfunction to test the error recovery operation.The conventional method for generating a pseudo-malfunction in a microprocessor is to use a shift system that connects flip-flops inside the microprocessor. By using the shift bus function that inputs and outputs internal information by moving the internal information in the mode, or by manually inserting input signals by connecting a switch etc. to the input terminal of the microprocessor, it is possible to cause a pseudo malfunction in the microprocessor. is being executed.

[Problem to be solved by the invention]

In the conventional microprocessor pseudo-malfunction generation method described above, when using the shift bus function, it is necessary to interrupt the execution of the software in the evaluation environment where the software is running and perform operation using a completely different shift bus function. have to transition.

In addition, when connecting switches, etc., adding a switch at the end causes various problems such as a delay in the circuit delay in the microprocessor and an increase in the amount of hardware to be added. It is only possible to cause a certain malfunction.

For this reason, conventional microprocessor pseudo-malfunction generation methods have the problem that, although they can generate a certain pseudo-malfunction in the microprocessor, they cannot generate the pseudo-malfunction at an appropriate timing.

If it is not possible to cause a pseudo-malfunction to occur at an appropriate time, we will analyze in detail what kind of situation and timing the malfunction occurred, and provide the optimal treatment for each case. Conventional microprocessor pseudo-malfunction generation methods have the drawback of being insufficient for the development and evaluation of operating systems that must be carried out.

An object of the present invention is to generate a pseudo-malfunction in a microprocessor that can cause a microprocessor to generate a pseudo-malfunction at an appropriate timing and with appropriate contents by providing software-controllable malfunction occurrence instruction information and malfunction content identification information. The purpose is to provide a method.

[Means to solve the problem]

The pseudo-malfunction generation method of the microprocessor of the present invention is as follows: (A> Execution/monitoring mode switching in which a signal is input to switch between the execution mode in which normal operations are performed and the monitoring mode in which pseudo-malfunctions are caused. a terminal; (B) malfunction occurrence instruction information storage means for storing malfunction occurrence instruction information indicating that the pseudo malfunction is to be performed in a software controllable register; (C) malfunction content specifying information indicating the content of the pseudo malfunction; (D) when a signal indicating a monitoring mode is input to the execution/monitoring mode switching terminal;
A malfunction generation circuit that decodes the malfunction occurrence instruction information and the malfunction content specifying information and generates the pseudo malfunction of the instructed and specified content.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a pseudo malfunction generation method for a microprocessor according to the present invention.

In FIG. 1, an execution/monitoring mode switching terminal 2 of a microprocessor chip 1 determines whether the microprocessor is placed in an execution mode in which it only performs normal operations, or in a monitoring mode in which it can also perform pseudo-malfunctions. A switching signal St (“1” when in execution mode, “O” when in monitoring mode) is input.

On the other hand, the software controllable register 3 serves as a malfunction occurrence instruction information storage means and a malfunction content specifying information storage means, and stores malfunction occurrence instruction information indicating that a pseudo malfunction is to be performed and malfunction content specifying information indicating the content of the pseudo malfunction. do.

FIG. 2 is an information explanatory diagram showing pseudo-malfunction-related information and its functions that the software-controllable register 3 has.

As shown in FIG. 2, the software controllable register 3 has a pseudo malfunction on/off bit A (1" when on, 1" when off), which is malfunction occurrence instruction information, in the leftmost 4 bits. °-0”), read/write designation bit B (“1” for read, “0” for write), which is 3-bit soto malfunction specific information, and instruction/operand designation bit C (for instruction "1" for data, "O" for data) and address/data designation bit D (1 for address, "°O" for data).

Further, the decoder 4 and the control signal generation circuits 5, 6, 7.8, which are malfunction generation circuits, generate pseudo Deciphers the malfunction on/off bit A, read/write designation bit B, instruction/operand designation bit C, and address/data designation bit D, and generates a pseudo malfunction with the specified contents as shown below. .

First, the decoder 4 selects the leftmost 4 pits (A, B) of the register 3.
, C, D and the contents thereof, as shown in FIG. 2, a mask signal S2. S3゜S4. S5 is generated respectively.

When the switching signal Sl is "0" in the monitoring mode, the mask signal S
When "1" occurs in 2, the control signal generation circuit 5 sends an inverted signal to the multiplexer 21 which selects whether to output the contents of the write data buffer 10 to the data bus 20 as is or inverted. to select the output operation.

Therefore, the data bus 20 is connected to the write data buffer 1.
It receives pseudo error data with the contents of 0 inverted and sends it to the outside.

Next, when the switching signal S1 is "0" in the monitoring mode and "1" is generated in the mask signal S3, the control signal generation circuit 6 generates information from the data bus 20 to be read out to the read data buffer 11. The read data buffer 1
1 does not store read data.

As a result, the read data buffer 11 has pseudo error data in which the read data has been erased.

Further, when the switching signal S1 is "0" in the monitoring mode and "1" is generated in the mask signal S4, the control signal generation circuit 7 suppresses information from the data bus 20 that is read to the instruction buffer 12. , the instruction buffer 12 is not allowed to store read data.

Therefore, the instruction buffer 12 has a pseudo error instruction whose instruction information has been erased.

On the other hand, when the switching signal S1 is "0" in the monitoring mode and "1" is generated in the mask signal S5, the control signal generation circuit 8 outputs the contents of the memory address buffer 13 as is to the address bus 22. The multiplexer 23, which selects whether to invert or output the signal, selects the operation of inverting and outputting the signal.

Therefore, the address bus 22 receives a pseudo error address obtained by inverting the contents of the memory address buffer 13 and sends it to the outside.

Moreover, the above mask signal S2. S3. Since S4 and S5 are not necessarily exclusive, two or more can be generated at the same time to cause double pseudo-malfunctions.

Note that in this embodiment, the pseudo-malfunctions of addresses are collectively classified into one type, but it is possible to determine whether the pseudo-malfunction is generated at the address when writing data or when the pseudo-malfunction is generated at the address when reading data. Alternatively, it is also possible to set detailed conditions such as whether a pseudo-malfunction is caused at an address when reading an instruction.

As described above, the microprocessor pseudo-malfunction generation method of the present embodiment generates a pseudo-malfunction by providing software-controllable malfunction occurrence instruction information and malfunction content specification information, and when generating a pseudo-malfunction, By leaving it up to the software developer, especially the operating system developer, to decide what kind of things should happen and when, the fault control system employs redundant microprocessors and improves reliability.
When developing a tolerant system, the development and debugging of error handling related to the operating system and external peripheral circuits can be easily and efficiently performed.

Particularly in fault-tolerant systems, the quality of the operating system that provides recovery in the event of a malfunction is extremely important.

For this reason, the operating system's error handling is
When did the malfunction occur? Are the contents of memory corrupted? What location in memory is corrupted? Are the contents of registers within the processor corrupted? Is retry possible? It is necessary to perform various analyzes such as , etc., and the error handling will vary depending on the timing of the malfunction.
In order to evaluate them in detail, it is important to use the microprocessor pseudo-malfunction generation method of this embodiment to freely generate various pseudo-malfunctions using software at desired timings.

〔Effect of the invention〕

As explained above, the microprocessor pseudo-malfunction generation method of the present invention provides software-controllable malfunction occurrence instruction information and malfunction content identification information, so that a pseudo-malfunction is generated in the microprocessor at an appropriate timing and with appropriate content. It has the effect that it can be generated in

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a pseudo-malfunction generating method for a microprocessor according to the present invention, and FIG. 2 is an information explanatory diagram showing information related to pseudo-malfunctions possessed by software-controllable registers and their functions.

Claims (1)

[Claims] (A) An execution/monitoring mode switching terminal that inputs a signal for switching between an execution mode in which normal operation is performed and a monitoring mode in which pseudo-malfunctions are caused; (B) the pseudo-malfunction Malfunction occurrence instruction information storage means for storing malfunction occurrence instruction information indicating that a malfunction is to be performed in a software controllable register; (C) storing malfunction content specifying information indicating the content of the pseudo malfunction in a software controllable register; (D) When a signal indicating a monitoring mode is input to the execution/monitoring mode switching terminal, a malfunction content specifying information storage means decodes the malfunction occurrence instruction information and the malfunction content specifying information and specifies the instruction. A pseudo-malfunction generation method for a microprocessor, comprising: a malfunction generation circuit that generates the pseudo-malfunction of the content.