JPH02130641A - Pseudo failure setting system - Google Patents

Abstract

PURPOSE:To set the pseudo failure of large freedom degree to a package circuit to be tested without shortening the line of the said circuit or generating breaking-down by providing a pseudo failure setting means, which corresponds to respective input signals, to set the pseudo failure to the input signal. CONSTITUTION:When the pseudo failure is set to input signals 9#1-9#n the failure is set through pseudo failure setting means 14#1-14#n such as an OR circuit, etc., for example. Thus, even when the output impedance of a circuit in a front step, for which the signals 9#1-9#n are outputted, is small, a current does not flow between decode outputs 13#1-13#n and the output side of the circuit in the front step. Then, the degradation or breaking-down of the circuit is not invited. For example, since an (n)=2<m> number of decode outputs 13 can be obtained from an (m)-number of dummy failure setting signals 10 by a decodes means 12, it is enough to provide the small number (m) of input pins 11 in order to set the pseudo failure to an (n)-number of circuits 8 to be tested.

Description

[Detailed Description of the Invention] [Summary] Regarding the pseudo fault setting method for testing package circuits such as integrated circuits or checking software functions during the operation of the circuits, shortening or destroying the package circuit under test. The purpose of this method is to enable the setting of pseudo-faults with a large degree of freedom in the same circuit, without the need for simulative faults. An input pin corresponding to each pseudo fault setting signal into which the pseudo fault setting signal is input, a decoding circuit that decodes the pseudo fault setting signal and obtains a number of decoded outputs greater than that number, and each of the decoded outputs of the decoding circuit. and pseudo fault setting means corresponding to each input signal for setting a pseudo fault to each of the input signals.

[Industrial application field]

The present invention relates to a pseudo failure setting method for testing package circuits such as integrated circuits or checking software functions during operation of the circuits.

[Conventional technology]

In order to test a package circuit such as an integrated circuit or to check software functions during operation of the circuit, it is conceivable to set a pseudo failure in the package circuit and check whether an abnormality occurs. That is, if a pseudo fault occurs and an abnormality appears in the output of the package circuit, it means that the circuit is operating normally.

A general example of a package circuit is shown in FIG.

In the figure, a circuit is configured in a package circuit 1 in which the output of an AND circuit 2 is connected to the D input terminal of a D flip-flop 3, and the output of the AND circuit 2 is connected to a pin 4. Suppose it is connected. It is also assumed that the positive logic output terminal Q of the D flip-flop 3 is connected to the pin 5. It is assumed that a clock (not particularly shown) is input to the clock terminal CK of the D flip-flop 3, and that the reset terminal R is pulled up to +5 volts via the resistor 6.

In this circuit configuration example, when the output of the AND circuit 2 goes high, a high level also appears at the pin 5 via the positive logic output terminal Q of the D flip-flop 3.

[Problem to be solved by the invention]

In the above package circuit 1, for example, when testing the D flip-flop 3, conventionally, a high level voltage of +5 volts was forcibly applied to pin 4 as shown in the figure, or it was connected to ground. A possible method is to generate a pseudo fault and observe the logic state appearing at pin 5. That is, by observing how the logic state of pin 5, which is the output of D flip-flop 3, changes according to the logic state of pin 4, it is tested whether the D flip-flop 3 operates normally. It is possible that

Here, the AND circuit 2 and D constituting the package circuit 1 are
The flip-flop 3 and the like usually have a circuit configuration in which the input impedance is large and the output impedance is small.

Therefore, if +5 volts is directly applied to pin 5 or it is connected to ground as in the conventional example, there will be no problem since the input impedance is large on the D input terminal side of D flip-flop 3, but the AND circuit 2 Since the output impedance on the output terminal side is small, a large current flows through the AND circuit 2 through the pin 4.

However, such a large current as described above has a problem in that if it is passed for even a few seconds, the life of the AND circuit 2 will be shortened, and in the worst case, it will be destroyed.

Additionally, if another package circuit is connected to pin 4, there is a problem that if the output impedance on the connection side of that package circuit is small, that package circuit may be destroyed. are doing.

Furthermore, there is a problem in that only the portion that is pulled out as the pin 4 can be set as a fault.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to set pseudo-faults with a large degree of freedom in a package circuit under test without shortening the lifespan or destroying the circuit.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention.

The present invention is based on a pseudo-failure setting method for a plurality of input signals 9 that are respectively input to a plurality of circuits under test 8 in a package circuit 7 .

Input pins 11 (#i) to 11 (#m) are pins corresponding to each pseudo fault setting signal into which at least one pseudo fault setting signal 10 (#1) to (#m) is input.

The decoding circuit 12 receives the m pseudo fault setting signals 10.
This circuit decodes the number m and obtains a number n of decode outputs 13 (#1) to 13 (#n). The means is, for example, a binary decoder, where n=2''.

The pseudo-failure setting means 14 sets #1 to # of the decoding circuit 12.
Input each decode output 13 of #1 to #n.
This is means for setting a pseudo fault to each input signal 9, and is provided corresponding to each input signal 9. The means may include, for example, the first
This is an OR circuit in which the input signal 9 is input to the input of the circuit, the decode output crab 3 is input to the second input, and the output is connected to the circuit under test 8.

On the other hand, although not shown in FIG.
It is also possible to have a pseudo-failure setting package circuit which is connected to the connector via the input pin 11 and arbitrarily sets the logic state of the pseudo-fault setting signal 10.

[For production]

When setting a pseudo fault to the input signals 9 ('#1) to 9 (#n), a pseudo fault setting means 14 such as an OR circuit, etc.
(#1) to l 4 (#n), so even if the output impedance of the previous stage circuit to which input signals 9 (#1) to 9 (#n) are output is small, the decode output 13 (#1) to 13 (#n) There is no possibility of current flowing between the output side of the preceding stage circuit, and there is no risk of deterioration or destruction of the circuit.

For example, since n=21 decoded outputs 13 are obtained by the decoding means 12 from m pseudo-fault setting signals 10, in order to set pseudo-faults to n circuits under test 8, a small number of m Only the input pin 11 needs to be provided.

Furthermore, since the decoding means 12 such as a binary decoder can usually be constructed of an element with high input impedance, there is no problem even if a voltage is directly applied to the input pin 11 or it is grounded.

Note that the pseudo-fault setting package circuit that can arbitrarily set the logic state of the pseudo-fault setting signal 10 is called the package circuit 7.
By connecting the connector to the connector, it is possible to efficiently set up a pseudo failure.9 [Example] The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

The package circuit under test 16 is a pan-cage circuit that is about to be tested, and has an AND circuit 2, a D flip-flop 3, etc. similar to the conventional example shown in FIG. The circuit configuration is such that the output is connected to the D input terminal of the D flip-flop 3.

In this case, the output of AND circuit 2 is OR circuit 23 (#1)
The output of the OR circuit 23 (#i) is connected to the D input terminal of the D flip-flop 3.

The second input terminal of the OR circuit 23 (#1) is
The decoded output XO from the decoder 22 is input. The decoder 22 also outputs decoded outputs of X1 to X3, and OR circuits 23 (#2) to 23 (#4), respectively.
).

Regarding the OR circuits 23 (#2) to 23 (#4), although not particularly shown in the figure, there is a case where the other circuit to be tested in the package circuit under test 16 is the OR circuit 23 (#1). Connected similarly.

Tri-state buffers 21 (#1) to 21 (#3) whose control input terminals are grounded are connected to setting input terminals A, B and gate input terminal G of the decoder 22, and the input side thereof is connected to a resistor 1B ( It is pulled up to +5 volts via #1) to (#3). A 2-bit setting signal 30 (
#1) and 30 (#2) are input, and the pseudo failure instruction signal 29 is input to the gate input terminal G.

The setting signals 30 (#1) and 30 (#2) and the pseudo fault instruction signal 29 are supplied from the pseudo fault setting package circuit 15 connected to the package circuit under test 16 by the pin connector 17.

The pseudo fault setting package circuit 15 has a pseudo fault setting switch section 26 . One side of the switch section 26 is grounded, and the other side is pulled up to +5 volts via a resistor 27. The switch SW1 in the switch section 26
and 2 are connected to tristate buffers 28 (#l) and 28 (#2) whose control input terminals are grounded, respectively.
The setting signals 30 (#1) and 30 as their outputs
(#2) is obtained. In addition, the switch SW3 is a tri-state buffer 28 (#3) whose control input terminal is grounded.
is connected to the pseudo failure indication signal 29 as its output.
is obtained.

The operation of the embodiment having the above configuration will be explained below.

First, in this embodiment, OR circuits 23 (#1) to 23 (#
4) allows pseudo faults to be set in the circuit under test at four locations within the package circuit under test 16. The pseudo-fault setting is performed from the one-pseudo-fault setting package circuit 15 side.

First, when it is desired to set a pseudo fault to the package circuit under test 16, the switch SW3 of the pseudo fault setting switch section 26 in the pseudo fault setting package circuit 15 is turned on. As a result, a signal of logic 0 as the pseudo failure instruction signal 29 is input to the gate input terminal G of the decoder 22 in the package circuit under test 16, and the decoder 22 becomes operable.

Along with this, the switch S of the pseudo failure setting switch unit 26
By WI and 2, the decoded output XO of the decoder 22
- Set where in X3 the pseudo failure is to occur. For example, if the switch SW1 is turned on and the switch SW2 is turned off, the setting signal 30 (#1) becomes logic O1, and the setting signal 30 (#2) becomes logic 1.
For example, only the decoded output XO becomes logic 1.

Now, if D flip-flop 3 is normal, AND circuit 2
If the input signal 24 from the D flip-flop 3 is a logic O, the positive logic output Q of the D flip-flop 3 is also a logic O, and conversely, if it is a logic 1, it becomes a logic 1. Therefore, when the input signal 24 from the AND circuit 2 is logic O, when the decoded output XO is set to logic 1 and a pseudo fault logic 1 is generated at the output 25 of the OR circuit 23 (#1), If the positive logic output Q becomes logic 1, it is understood that the D flip-flop 3 is normal. By confirming this, the D flip-flop 3 can be tested. In addition, positive logic output Q
It is assumed that this can be observed by some method (for example, it is output from a pin, etc. not particularly shown, see FIG. 3).

In this case, if the output impedance of the AND circuit 2 is very small, no current will flow to the input signal 24 side even if the output 25 of the OR circuit 23 (#1) is set to logic 1, which is a pseudo fault. The circuit 2 will not be destroyed or the like. In this way, in the package circuit under test 16,
It is possible to safely set up pseudo-faults in the circuit part you want to test.

In the case of the OR circuits 23 (#1) to (#4), pseudo faults can be set in exactly the same way.

Here, in the above embodiment, the setting signals 30 (#1) and 30
According to (#2), four types of pseudo failures can be generated, so if, for example, n pins are prepared as the number of pins for generating pseudo failures, 2m types of pseudo failures can be set. In addition, in the package circuit under test 16, OR circuits 23 (#1) to 2
3 and #4), the area occupied by the decoder 22, tri-state buffers 21 (#1) to (#2), etc. becomes almost no problem due to integration.

In addition, after the test is completed, simulated fault setting package circuit 1
5 can be removed from the pin connector 17.

〔Effect of the invention〕

According to the present invention, even in a configuration where the output of a circuit with low output impedance is connected to the input side of the circuit under test, it is possible to safely set a pseudo fault without causing destruction or deterioration of this circuit. becomes.

Furthermore, for example, since n=21 decoded outputs are obtained by the decoding means from m pseudo fault setting signals,
In order to set pseudo faults in a plurality of circuits under test, it is possible to set them by simply providing a small number of input pins.

Furthermore, by connecting a pseudo-fault setting package circuit that can arbitrarily set the logic state of the pseudo-fault setting signal to the package circuit, efficient pseudo-fault setting becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. 7...Package circuit, 8(#1) to (#n)...Circuit under test, 9(#1) to
(#n)...Input signal, 10 (#1) to (4m)...
- Pseudo failure setting signal 1 11 (#1) to (4m)...Manual pin, 12...Decoding means, 13(#1) to (#n)...Decoding output, 14(#
1) to (#n)...Reversal obstacle setting means.

Claims (1)

[Claims] In a pseudo fault setting method for a plurality of input signals (9) respectively input to a plurality of circuits under test (8) in a package circuit (7), at least one pseudo fault setting signal (10) is provided. An input pin (11) corresponding to each pseudo-fault setting signal to be input, and a decoding circuit that decodes the pseudo-fault setting signal (10) and obtains a number (n) of decoded outputs (13) greater than the number (m) of the input pin (11). (12) and each decode output (13) of the decode circuit (12).
A pseudo-failure setting method, characterized in that it has a pseudo-fault setting means (14) corresponding to each input signal, which inputs each input signal (9) and sets a pseudo-fault to each of the input signals (9).