JPH02123430A - Pseudo fault generating system - Google Patents

Abstract

PURPOSE:To set up many pseudo fault positions and to debag or evaluate various fault processing by connecting FFs in a circuit by scan path constitution and setting up an FF on a position intended to generate a pseudo fault by using the scan path. CONSTITUTION:Scan-in is set up in the FFs 3-1 to 3-n by a fault processor 10 at the time of initializing for the rise of a central processor 20. When the generation of a fault in a certain register in a circuit block is intended, scan data are scanned in so that '1' is set up only in the FF corresponding to the register and '0' is set up in all the other FFs. When a start signal is generated at a prescribed timing from a pseudo fault starting circuit 1, all AND gates 4-1 to 4-n are turned on at the timing, all the outputs of respective FFs are made effective and an error is generated form the output of the register corresponding to the FF in which '1' is set up. Thereby, various faults can be continuously and automatically generated by changing a bit to be set up in the FF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pseudo failure generation method, and more particularly to a pseudo failure generation method for evaluating failure processing in a data processing device.

Ryomai Gen 1 Conventionally, this type of pseudo-failure generation method involves either manually fixing the signal line to 0 or 1 from the outside to create a pseudo-failure, or using a service processor to create a pseudo-failure inside the device. There is a method of activating a pseudo-failure occurrence signal that is connected to the system.

With the recent trend toward higher integration, it has become difficult to prepare signal lines that can be manually accessed from the outside, and it is therefore becoming impossible to create a pseudo failure manually from the outside. .

In addition, it is difficult to route signals inside the circuit in advance to generate a pseudo fault, as the integration becomes higher, and therefore it is only possible to generate a pseudo fault in a limited number of locations. There are drawbacks.

Therefore, the present invention has been made to solve the drawbacks of the prior art. It is an object of the present invention to provide a pseudo-failure generation method that does not require routing signal lines and allows setting of a large number of pseudo-fault locations.

The pseudo-failure generating method according to the present invention is composed of a scan canvas and a plurality of flip-flops for specifying the location where a pseudo-fault should be generated, and a method for generating these flip-flops using the scan canvas. A scan controller 1 for selectively setting a pseudo-fault generation pin 1- for a flip-flop, and a pseudo-fault activation means for validating all outputs of the flip-flops. The control means selectively sets the pseudo-failure generation phase P1~ for the flip-flop, and then the pseudo-fault activation means makes all the outputs of the clip W-J valid.
Pseudo lI1. It is characterized by causing harm.

fire! Embodiments of the present invention will be described in detail below with reference to the drawings.

The figure is a block diagram of an embodiment of the present invention, in which the medium heat processing device 20 is a data processing unit that performs depacking and evaluation of various fault processing, and the fault processing device 10 issues an instruction to generate a pseudo fault. This fault processing device 10 includes a pseudo-fault activation circuit 1 for activating the occurrence of a pseudo-fault, and a scan control circuit 7 for a scan canvas to be described later.

The central processing unit 20 consists of a plurality of circuit blocks 21 and 22, and a specific circuit example is shown for only one circuit block 21 among them, and the other circuit blocks have a similar configuration. shall be taken as a thing.

FF (flip-flops) 3-1- to 3-11 are for specifying locations in the circuit block 21 where pseudo-faults should not occur, such as T-'r"3
-1, 3-11 constitute a scan canvas by being cascade-connected to forces. This scan canvas can perform scan-in and scan-out operations in response to scan-in and scan-out control instructions from the scan control circuit 7.

A two-person computer game t-4-1-4-n is set up corresponding to each Fl''3-1 to 3-11, respectively, and the output of each FF is set to each of the corresponding anime game 1. The activation signal from the pseudo-failure activation circuit 1 is applied to all other inputs of these computer games 1 in common. Well, FF3
-1~. 3-n each output to corresponding anime game 1 4-1
~+1−n.

The outputs of the computer games 1 to 4-1 are output from predetermined pins (in this example, 2 pins) of a certain register 5 in the circuit block D21.
6 is input to exclusive OR game 1 which inverts Therefore, when the content of FF3-1 indicates "Pa1", if the anime game-1-4-1 is on, then t
;'The second bit of star 5 is inverted, and the result is l,
An error will be detected in the output signal of p3/star 5 by parity check. As a result, the occurrence of a pseudo fault is equivalent to the occurrence of a pseudo fault in the register 5 concerned.

It is assumed that the outputs of the other FFs are similarly configured so that errors occur with respect to the contents of the corresponding registers.

In such a configuration, the FFs 3-1 to 3-n are activated by the failure processing device 10 during the initial setting when the central processing unit 20 is turned off.
The scan-in is set by . At this time, when it is desired to cause a failure in a certain register in the circuit block 21, Il i Il is set to only the FF corresponding to that register, and 0'' is set to all other FF's. Various programs will be scanned in.

After that, if the pseudo-failure starting circuit 1 generates a starting signal at a predetermined timing, the AND gates 4-1 to 4-n are all turned on at that timing, and all the outputs of each Fp become valid. An error will occur in the register output corresponding to the FF set to 1''. If the activation signal at this time is a pulse, an intermittent fault will occur, and if it is at a continuous "1" level, a fixed fault will occur.

When a failure occurs, processing such as instruction retry is performed, but by changing the bits set in the FFs 3-1 to 3-n at this time, various failures can automatically occur successively.

In the conventional technology, the fault processing device 10 sends the type of pseudo fault directly or in code to the central processing unit 20, and the central processing unit sends the signal as is or after decoding to each unit or pseudo fault circuit. However, in the present invention, the signal from the fault processing device 10 is the activation signal 1.
Only a book is required, and pseudo failure points can be set as long as the number of FFs allows.

According to the present invention, by setting the FFs inside the circuit in a scan canvas configuration, it is sufficient to use this scan canvas to select the FF corresponding to the location where the pseudo fault is to be caused. Therefore, there is no need to route a pseudo-failure generation signal in the device, and a large number of pseudo-fault locations can be set. This has the effect of making it possible to debug and evaluate various failure processes.

[Brief explanation of the drawing]

The figure is a system block diagram of an embodiment of the present invention. Explanation of the symbols of the main parts 1... Pseudo-fault starting circuits 3-1 to 3-n ・=-FF 4-1 to 4-n ・...And Gate 5...
・Register 6...Exclusive OR circuit 7...Scan control circuit 10...Fault processing device 20...Central processing unit

Claims (1)

[Claims] (1) A plurality of flip-flops configured in a scan canvas for specifying locations where a pseudo fault should occur, and using the scan canvas to selectively set pseudo fault occurrence bits for these flip-flops. A scan control means and a pseudo-failure activation means for validating all outputs of the flip-flops are provided, the scan control means selectively sets a pseudo-failure occurrence bit for the flip-flops, and then the A pseudo fault occurrence characterized in that all outputs of the flip-flop are enabled by a pseudo fault activation means and a pseudo fault is generated at a location corresponding to the output of the flip-flop to which the pseudo fault generation bit is set. method.