JPH02183346A - Pseudo fault generating system - Google Patents

Abstract

PURPOSE:To easily execute the debugging of fault processing by generating a pseudo fault when a memory writing address, which is executed from another device, is coincident with the contents of a pseudo fault address register. CONSTITUTION:A pseudo fault address register 10 holds an address value as a condition to activate pseudo fault generation and an output is compared with the memory writing address value from the other device by a comparator 30. When the coincidence is detected, an address coincidence signal is informed as '1'. When the value of an allowance flag 20 is in a pseudo fault generation allowable state, the address coincidence signal passes through an AND circuit 31 and a decoder 50 generates a pseudo fault signal. This signal is ORed with the fault detection signal of a real hardware register by an OR circuit 51 and a fault detection flag 60 is set to '1'. Then, the output of the flag 60 is informed of a fault processor as an error informing signal. Thus, the pseudo fault can be generated asynchronously with the self-device and the debugging of the fault processing function can be enough evaluated without man power.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of generating a pseudo fault in a data processing device that performs fault processing, and particularly to a method of generating a pseudo fault randomly on a time axis.

[Prior Art] Conventionally, known methods of this type include a method of manually fixing the pins of an arbitrary chip to zero, and a method of generating a false failure using a specific software command.

[Problem to be solved by the invention] However, the conventional manual method described above has drawbacks such as low efficiency and lack of reproducibility, and the method using software instructions has perfect reproducibility, but it is difficult to simulate. There was a drawback that there was no degree of freedom (randomness) in the failure time.

Particularly in recent data processing apparatuses, failure handling functions are becoming more and more enhanced, and inspection means have become important. Among these inspection means, there is a lack of easy means for checking the operation for irregularities on the time axis.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, a technical object of the present invention is to provide a pseudo-fault generation method that allows easy debugging of fault processing.

[Means for Solving the Problems] According to the present invention, a pseudo-failure address register that holds an address that defines a pseudo-fault condition, a memory write address executed from another device, and the contents of the pseudo-fault address register are configured. It has a comparator that detects whether or not they match, and a permission flag that allows the occurrence of a pseudo fault, and by setting a desired address in the pseudo fault address register and keeping the permission flag on, other A pseudo-failure generating method is obtained, which is characterized in that when the device executes memory writing to the desired address, the comparator detects a match and generates a pseudo-fault.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The pseudo-fault address register 10 holds an address value as a condition for starting the pseudo-fault occurrence, and its output (connection 101) is compared by the comparator 30 with the memory write address value from another device supplied via the connection 701. . As a result of the comparison, if a match is detected, the address match signal is set to “1” on the connection 301.
”.The address match signal is notified when the value of the permission flag 20, which indicates whether pseudo-fault occurrence is permitted, is “1”.
“In other words, if the simulated fault generation is permitted, the signal passes through the AND circuit 31 and is sent to the connection 311. This is a circuit that decodes fault codes.Specifically, in arithmetic processing units, faults that depend on the architecture, such as cache memory faults, software registers (general-purpose registers, etc.), hardware registers, etc. A code is prepared.In the embodiment, a pseudo failure signal of a hardware register is shown as a connection 501.

This number (i) is logically summed with the failure detection signal (connection 905) of the actual hardware register in the OR circuit 51, and the failure detection flag 60 is set to "1".The output of the failure detection flag 60 is the error notification signal ( The fault processing device is notified as connection 601).

Although not described in this embodiment, failure processing is mainly executed by a diagnostic device, a service processor, and the like.

Next, the settings of the pseudo-failure address register 10 and the like will be explained.

False fault address register 10. The allowable nJ flag 20° false fault code register 40 can be set by a micro program and can also be set by a software instruction. It is also possible to control and set the microprogram through the service processor, and since the service processor has a means of notifying the microprogram of operator (human) instructions, the microprogram can be set manually from the console. method is also possible. The permission flag 20 in the microprogram is “
When set to 1", the pseudo fault generation mechanism is enabled. However, in this embodiment, depending on the value of the pseudo fault code register 40, the pseudo fault generation mechanism may be enabled even if the connection 311 does not become l". Sometimes I do.

Figure 2 shows the memory write address (connection 70) from another device.
1) is a block diagram of a generation unit. Own device 900 is the first
It is an arithmetic processing unit including the block diagram of the figure, and the memory 92
0 is a main memory section, which is accessed from each device via a system bus 930. Other equipment 91
0 indicates the same arithmetic processing device, transfer device, or diagnostic device as the own device. It is connected to an input/output device via a transfer device, and to a service processor via a diagnostic device.

When a memory write is executed from Jibukuro M910, the command indicating the write and the memory write address are sent to the system bus 9.
30. By monitoring the system bus, the own device 900 learns that another device 910 is writing to the memory 920 by decoding the command indicating writing with the decoder 71, and sets the write address in the address register 70. . The contents of this address register 70 are transferred to the comparator 30 in FIG.
connected to.

Decode 71 and address register 70 shown in this figure
is a circuit necessary to execute invalidation processing of the cache memory of the own device, and does not particularly need to be added to implement the present invention.

Next, explanation will be given using the time chart shown in FIG.

As described above, the microprogram instructs to set the false fault address register 0 at tl (timing) and sets N' at t2.

At t2, an instruction is further given to set the false fault code register 40, and at t3, "9" is set. Further allowance at t3
11 flag 20 is instructed to be set, and at t4, the opening J flag becomes "1", and after t4, the address match signal (connection 301 in FIG. 1) becomes valid.

When preparations for the occurrence of a pseudo fault are completed as described above, the microprogram instructs to start or restart the program.

After t4, the write address is checked every time another device writes to the memory. If the memory write address of the other device executed at t is "N", ("N" is set in the address register 70 at n+]), the comparator 30 matches and the detection flag 60 is set to t. The error becomes "1" and an error n+2 notification is performed.

[Effects of the Invention] As explained above, the present invention generates a false fault when another device executes memory writing and the address matches a preset false fault address, thereby preventing the self-device from writing to the own device. It is possible to generate a pseudo fault asynchronously, and this has the effect of making it possible to fully evaluate the debugging of the fault handling function without manual intervention.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the present invention, and FIG. 3 is a time chart of the present invention. 10.40.70...Register, 20.60...Flip-flop, 30...Comparator, 50.71...
Decoder, 31...AND circuit, 51...OR circuit.

Claims (1)

[Scope of Claims] 1) Detecting whether or not a pseudo-fault address register that holds an address that defines a pseudo-fault condition matches a memory write address executed from another device and the contents of the pseudo-fault address register. The device has a comparator that performs a pseudo-failure, and a permission flag that allows the occurrence of a pseudo-fault, and by setting a desired address in the pseudo-fault address register and keeping the permission flag on, other devices can access the desired address. A pseudo-failure generation method characterized in that when a memory write is executed for a memory, the comparator detects a match and generates a pseudo-fault.