JPH02113345A - Pseudo machine error generation system - Google Patents

Abstract

PURPOSE:To generate a pseudo machine error at irregular time on a time base by generating an pseudo machine error when a program generates the same address as an optionally settable value. CONSTITUTION:An pseudo machine error address register 10 holds an address value as a condition for causing pseudo machine error generation and its output is compared by a comparator 30 with the program generation address value which is supplied from a connection 904, so that when they are coincident, an address coincidence signal '1' is sent onto a connection 301. The address coincidence signal is sent to a connection 311 through an AND circuit 31 when a permit flag 20 indicating whether the pseudo machine error generation is allowed or not is '1', i.e. when the pseudo machine error generation is allowed. A decoder 50 decodes an pseudo machine error code stored in an pseudo machine error code register 40 and outputs an pseudo machine error signal to a connection 501. Consequently, the pseudo machine error generation time is given the degree of freedom (random).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of generating a pseudo fault in a data processing device that performs fault processing, and particularly to a method of generating a pseudo fault randomly on a time axis.

[Prior Art] Conventionally, as this type of pseudo-failure generating method, methods are known such as manually fixing the bin of an arbitrary chip to zero, and generating a pseudo-failure using a specific software command. .

[Problems to be Solved by the Invention] 'The conventional manual methods described above have drawbacks such as low efficiency and lack of reproducibility. Furthermore, although the method using software instructions has perfect reproducibility, it has the disadvantage that there is no degree of freedom (randomness) in the time at which a false failure occurs.

Particularly in recent data processing apparatuses, failure handling functions are becoming more and more enhanced, and inspection means have become important. Among these inspection means, there is a lack of means for easily checking the operation of failures that occur irregularly on the time axis.

Means for Solving Section C Notification] The pseudo failure occurrence method according to the present invention includes a data processing device that has a failure detection means and executes processing according to a predetermined method when a failure is detected by the failure detection means. , a pseudo-fault address register that holds an address that defines a pseudo-fault condition; a comparator that detects whether an effective address generated during program execution matches the contents of the pseudo-fault address register; In the first step, a desired address is set in the pseudo-fault address register and the permission flag is turned on, and then the program is restarted. The present invention is characterized in that when an address is generated, the comparator detects a match, thereby generating a false fault.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The pseudo-fault address register 10 holds an address value as a condition for activating the pseudo-fault occurrence, and its output (connection 101) is compared by the comparator 30 with the program-generated address value supplied from the connection 904.

If a match is detected as a result of the comparison, an address match signal of "1" is notified on the connection 301. The address match signal passes through the AND circuit 31 and is sent to the connection 311 when the value of the permission flag 20 indicating whether or not pseudo-fault occurrence is permitted is "1", that is, the pseudo-fault occurrence is permitted. The decoder 50 is a circuit that decodes the pseudo fault code stored in the pseudo fault code register 40 which holds a code specifying the type of pseudo fault to be generated.

Specifically, in arithmetic processing units, cache memory pseudo failures, software registers (general purpose registers, etc.)
We have prepared architecture-dependent pseudo-failure codes, such as pseudo-failures for hardware registers and hardware registers. In this embodiment, the connection 501 is a false fault signal of the /1-doware register.

This pseudo-failure signal is converted into an actual hardware signal by an OR circuit 51.
A logical OR is taken with the failure detection signal of the register (connection 905), and the failure detection flag 60 is set to "1". The failure detection flag 60 output is notified to the failure processing device as an error notification signal (connection 601). Although not described in this embodiment, failure processing is mainly carried out by a diagnostic device, a service processor, or the like.

Next, the settings of the pseudo-failure address register 10 and the like will be explained.

Setting of the pseudo-fault address register 10, permission flag 20, and pseudo-fault code register 40 can be executed from a microprogram, and can also be set from a software instruction. It is also possible to control and set the microprogram through the service processor, and since the service processor has a means of notifying the microprogram of operator (human) instructions, it is possible to set the microprogram manually from the console. It is also possible. In any case, it is the microprogram that issues the direct set instruction. When the permission flag 20 is set to "1" by the microprogram, the false failure generation mechanism becomes effective. However, in this embodiment, depending on the value of the pseudo fault code register 4o, the occurrence of a pseudo fault may be valid even if the connection 311 does not become "1'."

Next, the operation of this embodiment will be explained using FIG. 2.

As mentioned above, at timing t1, the pseudo fault occurrence address 'N' is set in the pseudo fault address register 1o by the micro program, and at timing t'2, the pseudo fault code "a" (hardware register) is set in the pseudo fault code register 40. pseudo fault) is set, and the permission flag is set to 20 at timing t.
” is set to “1”, the address match signal (output from the comparator 30 in FIG. 1) becomes valid from timing t onwards.

When preparations for pseudo-failure generation are completed, the microprogram instructs to start or restart the program. As a result, in FIG. 2, instructions on the program start running at timing t4, and when an instruction requiring memory access is executed, a memory address is generated by hardware. This memory address is called a program generation address, and its value will be checked by comparator 30 in FIG.

In FIG. 2, timing 1. When the program generation address becomes "N" upon execution of instruction X, the detection flag 60 is set at the next timing (t), and the error occurrence due to the pseudo fault is completed.

The output of the detection flag 60 is logically ORed with the outputs of other detection flags, and the appropriate device within the system is notified and fault handling is activated, but this is beyond the scope of the present invention and will not be described here. In terms of timing, if the programs running after 4 are the same, the pseudo fault will occur at the same timing, but with different programs, the pseudo fault can occur at different timings.

[Effects of the Invention] As explained above, the present invention generates a pseudo fault when a program generates an address that is the same as an arbitrarily settable value, thereby causing a pseudo fault to occur at an irregular time on the time axis. It can cause problems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the present invention in detail. 10.40...Register, 20,60...Flip/70 tube, 30...Comparator, 50...Decoder,
31...AND circuit, 51...OR circuit.

Claims (1)

[Claims] 1. In a data processing device that has a failure detection means and executes processing according to a predetermined method when a failure is detected by the failure detection means, an address that defines a false failure condition is held. A comparator for detecting whether an effective address generated during program execution matches the contents of the pseudo fault address register, and a flag for permitting the occurrence of a pseudo fault. In the first step, the desired address is set in the false fault address register and the permission flag is turned on, and then the program is restarted. When the program generates the desired address, the comparator detects a match. A pseudo-failure generation method that is characterized by generating a pseudo-fault by detecting it.