JPH04332996A - Troubleshooting system - Google Patents

Abstract

PURPOSE:To troubleshoot quickly when the error occurs in read-out data in a RAM decoder. CONSTITUTION:The same data pattern as the decode pattern which is written in an originally used area is written in advance in the unused area of a RAM decoder 20 in the address direction. When an error occurs in the decode pattern in the originally used area and a parity check circuit 21 detects the error, the read address of a RAM is switched and the decode pattern previously written in the unused area is read out under the control of a control section 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault handling system, and more particularly to a RAM that provides an input data pattern to be decoded as a read address and performs decoding by reading out a decoded data pattern written in advance corresponding to the read address. This relates to a decoder failure handling method.

0002

[Prior Art] Conventionally, when an error is detected in a decoded data pattern read from a RAM, a fault processing unit is notified of the error and a microprogram for fault processing is started, thereby causing the data to be decoded again into the RAM. A data pattern is written, and then the data is read out again later.

[0003] Since the above-mentioned conventional fault handling method is processed by software, it takes a very large number of machine cycles to complete reading and retrying the decoding pattern from the RMA decoder. There are drawbacks.

[0004] Furthermore, as the degree of integration of RAM increases, the unused data writing area in the address direction tends to increase. The disadvantage is that the used portion is not used effectively.

[0005]

OBJECTS OF THE INVENTION It is an object of the present invention to provide a failure handling system that can perform failure handling at high speed when a data error occurs in a RAM decoder and can effectively utilize the RAM area.

[0006]

According to the present invention, a RAM decoder provides an input data pattern to be decoded as a read address and performs decoding by reading out a decode data pattern written in advance corresponding to the read address. The failure handling system divides a storage area into a first and a second area in the address direction of the RAM, and
means for writing the same decoded data into each corresponding address section of the second area; means for error checking the read data from the first area; and when an error is detected by the error check, the and means for controlling reading of data from the second area.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the present invention. In the figure, reference numeral 10 denotes a control unit that writes a decode pattern to the RAM decoder 20 and performs control when a soft error occurs in the RAM decoder 20.

Reference numeral 11 denotes a logic circuit for controlling the register 18 that holds the most significant bit of the write/read address of the RAM decoder 20 to be set to "0" or "1", and includes an AND gate 11a and an OR gate 11b. It consists of

Reference numeral 12 is a register that holds write enable for the RAM 20, and reference numeral 13 is a NAND gate for inverting the scan mode signal sent from the control unit 10 via the signal line 52. 14, the value of register 12 is “1” and the output of NAND gate 13 is “1”
This is an AND gate for sending a write enable signal "1" to the RAM 20 via the signal line 62 when the write enable signal "1" is selected (that is, when not in the scan mode).

Reference numeral 16 is a register for holding write data to the RAM 20, and register 17 is a register for holding write data to the RAM 20.
This is a register for holding a write address for RAM 20 and a lower address excluding the most significant bit of a read address from RAM 20. Register 18 is a register for holding the most significant bit of an address.

The AND gate 19 inputs the value of the register 18, that is, the value "1" of the most significant bit of the write address of the RAM 20.
” and the signal “1” indicating that there is a soft error in the read data from the RAM 20 sent via the signal line 67, the signal “1” indicating that retry is not possible due to hardware. ” to the control unit 1 via the signal line 68.
This is an AND gate for notifying 0.

Reference numeral 20 denotes a RAM decoder, in which a necessary decoding pattern can be written in the main decoder shown in the figure, and it is also possible to write exactly the same decoding pattern in the sub-decoder. 21 is a RAM decoder 20
This is a parity check circuit for sending a detection signal "1" to the signal line 67, which indicates that a soft error exists in the data read from the parity line 67.

53 to 57 are registers 12, 16, 17 when writing a decode pattern to the RAM decoder 20.
and 18 are scan paths for setting write enable, write data, lower address excluding the most significant bit of the write address, and most significant bit of the write address, respectively.

Reference numeral 59 is a signal line for notifying the logic circuit 11 of a signal "1" instructing the logic circuit 11 to write the decode pattern into the sub-decoder side of the RAM 20. 60 is a signal “1” indicating to the logic circuit 11 that the writing operation of the decode pattern to the RAM decoder 20 has been completed;
This is a signal line for notifying.

52 is a signal line for sending a signal "1" indicating scan mode to the registers 12, 16, 17, 18 and NAND gate 13; 50 is a signal line when the RAM decoder is used (normal operation); This is a data line for setting an address in the address register 17 at the same time. 51 is a strobe signal for setting the address sent via the data line 50 in the register 17.
This is a signal line for sending out 1".

72, 64, and 65 are address data lines for write and read addresses of the RAM decoder 20;
Reference numeral 66 is a signal line for sending the decoding result to the arithmetic unit. Further, 71 is an RA output via the signal line 66.
This is a signal line for notifying the calculation unit that the decoding result by the M decoder is valid.

Next, the actual operation will be explained. First, the operation of writing a decode pattern into the RAM decoder 20 will be explained.

A scan mode signal “1” is sent from the control unit 10 to the registers 12, 16, 17, 18 via the signal line 52.
Each register enters the scan mode, starting with the data to be set in the register 18 via the signal line 53, and is scanned in from the register 12 in synchronization with the clock. At this time, if the total number of bits in each register is n, the number of machine cycles or clocks required to complete the scan-in operation is n machine cycles or n.

Upon completion of the scan operation, the value of the signal line 52 changes from "1" to "0", and each register is no longer in scan mode. At this time, the value of register 18 is "0", the value of register 17 is all 0 (the number of bits is arbitrary), the register 16 is the decode pattern (the number of bits is arbitrary), and the value of register 12 is "1". do.

At the same time as the scan mode ends, the output of the AND gate 14 becomes "1" because the output of the NAND gate 13 is "1" and the register 12 is "1".
The write enable of the RAM decoder 20 becomes "1". Therefore, with the next clock n+1, the first decode pattern is written to the most significant word of the main decoder.

[0022] Also, at this time, the output of the logic circuit 11 is "1".
was set in the register 18 before the input of the clock n+1, so the register 18 becomes "1" by the input of the clock n+1.

Now, to explain the logic of the logic circuit 11, there is a signal sent from the control unit 10 via the signal line 59 instructing to switch writing of the decode pattern to the RAM decoder from the main decoder to the sub-decoder. “1” is lit, or the signal “1” sent via the signal line 60 indicating that all decoding pattern writing operations to the RAM decoder have been completed is lit, and the signal line 67 is lit. When the signal indicating that there is a soft error in the read data from the RAM decoder sent via the RAM decoder is lit as "1", the output of the logic circuit 11 becomes "1". The above logic is realized by AND gate 11a and OR gate 11b.

Therefore, it is assumed that the decode pattern write instruction signal "1" is turned on from the control section 10 via the signal line 59 to the sub-decoder before clock n+1 is input.
As mentioned above, register 18 is input by clock n+1.
is "1".

When clock n+2 is input, the register 18 is “
1", and the value of the write address signal line 65 of the RAM 20 indicates the most significant word of the sub-decoder. Also, since the register 18 is "1" and the signal line 52 is "0", the write enable signal of the RAM 20 is also The value of line 62 is "1". Therefore, the decode pattern in register 16 is written to the most significant word of the subdecoder.

As a result of the above, the same decode pattern is written in the most significant word of each of the main decoder and sub-decoder. It is assumed that each register is held when the strobe is not lit.

Thereafter, similar operations are repeated to write decode patterns in all words of the main decoder and sub-decoder, thereby realizing two identical decoders. Compared to the number of clocks required to write a conventional decode pattern,
Assuming that the number of words of the decode pattern is a, the number of clocks required to write the decode pattern according to the present invention is at most an additional clock.

Next, the operation when a soft error is detected in the data (decode pattern) read from the RAM 20 will be explained. During normal operation, it is assumed that the scan mode signal line 52 is set to "0" and the registers 12 and 16 are set to "0".

When the address given by the read address line 50 is output from the register 17, the register 18
is "0", the corresponding decode pattern is read out from the main decoder via the signal line 66.

Here, if there is a soft error in the read decode pattern, the parity check circuit 21
This is detected, and the logic circuit 11 is notified of this via the signal line 67, and the control unit 10 is also notified. At this time, a signal "1" indicating that the write operation of the decode pattern to the RAM decoder has been completed is input from the control unit 10 to the logic circuit 11 via the signal line 60.

Therefore, according to the logic described above, logic circuit 1
The output of the OR gate 11b, which is the output of 1, becomes "1", and the register 18 is set to "1". Also, the control unit 1
0 to the RAM decoder reference side via the signal line 69,
In the next machine cycle as well, a signal "1" indicating that the RAM decoder is referred to at the same address is output, and the strobe signal of the register 17 to be sent via the signal line 51 is suppressed to "0". The next clock is input under the above conditions.

With the next clock input, register 18 is set to "1" and register 17 remains unchanged.
A desired decode pattern is read from the sub-decoder side. If no soft error is detected at this time, the read decode pattern is a signal indicating that the read data from the RAM is valid, which is output from the parity check circuit 21 via the data line 66 via the signal line 71. It is sent to the arithmetic unit together with "1".

Further, a signal "0" indicating that there is no soft error in the read data from the RAM decoder is sent from the parity check circuit 21 via the signal line 67 to the control unit 1.
RA from the control unit 10 via the signal line 69.
The M decoder reference side is notified of a signal "0" indicating that reference to the RAM decoder is permitted at a new address in the next machine cycle. Accordingly, the strobe signal "1" of the register 17 is sent from the RAM decoder reference side via the signal line 51.

Thereafter, since the register 18 remains unchanged at "1", the read operation from the sub-decoder side continues.

While the read operation from the sub-decoder side continues, if a soft error is detected again in the read data, the parity check circuit 21 outputs a soft error detection signal "1" via the signal line 67. and gate 1
9, and the signal "1" indicating that the sub-decoder side is currently in use is input from the register 18 to the AND gate 19 via the signal line 64, so that the output signal "1" of the AND gate 19 ”, that is, a signal indicating that a hardware retry of the read operation from the RAM decoder is impossible is notified to the control unit 10 via the signal line 68. Therefore, within the control unit 10, a microprogram dedicated to retry is started, and desired software processing is started.

[0036]

[Effects of the Invention] As explained above, according to the present invention, R
If an error is detected in the decode pattern read from the AM decoder, the RAM read address is switched by hardware control and the correct decode pattern written in advance is read from another area within the RAM decoder. This has the advantage that the read retry process of the RAM decoder can be completed in at most one machine cycle.

Furthermore, according to the present invention, whereas conventionally used ECC can only repair up to 1 bit error, it is also possible to repair errors of 2 or more bits.

Furthermore, when implementing conventional duplication of data in RAM, duplication in the bit direction is highly likely to actually lead to an increase in RAM, that is, an increase in hardware; It used to be difficult, but now that the degree of integration of RAM in the address direction is increasing, and the unused area in the address direction in RAM is increasing, it is now possible to easily duplicate by making effective use of the unused area. The effect is that it can be realized.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

[Explanation of symbols]

10 Control section 11 Logic circuit section 12 Write enable register 16 Write data register 17 Write address register 1 18 Write address register 0 20 RAM decoder 21 Parity check circuit

Claims (1)

[Claims] 1. A failure handling system for a RAM decoder, which provides an input data pattern to be decoded as a read address and performs decoding by reading out a decode data pattern written in advance corresponding to the read address. means for dividing a storage area of the RAM into a first and a second area in the address direction, and writing the same decoded data into corresponding address portions of the first and second areas; A failure processing system comprising means for error checking data read from the second area, and means for controlling reading data from the second area when an error is detected by the error check. .