JPH0675810A - Verifying method for access processing function to input/ output device - Google Patents

Abstract

PURPOSE:To verify a function of an access processing function of an input/ output device in an unmanned state by executing an artificial fault in various states of the input/output device by only an issue processing of an artificial fault instruction from a processor. CONSTITUTION:A processor P prepares in advance flags corresponding to input/ output device T1-Tn and data of a result of artificial access, and issues an artificial instruction 1 to an adaptor A. Also, an artificial fault instruction processing part K sets artificial access result data informed from the processor P to artificial access result registers S1-Sn. Subsequently, the processor P issues an input/output instruction 2 to the input/output devices T1-Tn, and the inside of the adaptor A which receives its instruction calls designated input/output device access processing functions C1-Cn. In such a way, when the input/output instruction 2 is issued, the contents of the artificial access result resistors S1-Sn are sent back to the input/output device access processing functions C1-Cn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying an access processing function for an input / output device of a processor system in which various input / output devices are connected to a processor via an adapter.

Due to the recent diversification of data processing by computer systems, the types of input / output devices and the number of connected devices have increased, and the intelligence of each input / output device has also increased. When setting, for example, because there are some things that require manual operation, such as a write-protect error on a floppy disk, and those that are difficult to operate manually, when testing a large number of input / output devices of the computer system at the factory or on site. There is a need for test methods that can be tested as effectively as possible.

[0003]

2. Description of the Related Art FIG. 3 is a diagram for explaining a conventional input / output device access processing function verification method. FIG. 3 shows an example of a processor system in which various input / output devices (T1, T2, ...) 3 are connected to a processor (P) 1 via an adapter (A) 2.

The processor (P) 1 is connected to an adapter (A) 2 via a bus (B) 4, and the adapter (A) 2 is connected to input / output devices (T1, T2 to) 3. Adapter (A) 2
Random access memory (not shown)
The instruction judgment processing unit (J) 22, the input / output device access processing functions (C1, C2, ...) 20, and each input / output device are on the RAM.
(T1, T2, ...) Driver (D
1, D2, ~) 23 and a completion processing section (E) 24 are placed.

The processor (P) 1 is an input / output device (T1, T2,
~) Processor 3 (P) 1, Adapter when accessing 3
(A) Issue an I / O command to 2. Adapter (A) 2 is
Upon receiving the input / output command, the command determination processing unit (J) 22
Determine which I / O device (T1, T2, ...) 3 is the instruction, and process the corresponding I / O device access processing function (C1, C2, ...)
Give instructions to 20.

The specified input / output device access processing function
The (C1, C2, ...) 20 gives an instruction to the driver (D1, D2, ...) 23. The drivers (D1, D2, ...) 23 are actually input / output devices (T1,
T2, ...) 3 is accessed and the result is notified to the I / O device access processing function (C1, C2, ...) 20.

Input / output device access processing function (C1, C2, ...)
The 20 notifies the processor (P) 1 of completion via the completion processing unit (E) 24.

[0008]

The I / O device access processing functions (C1, C1) that occupy most of the functions of the adapter (A) 2
C2, ...) When verifying the functions of 20 I / O devices (T1, T
2, ~) 3 are set to various states, including the abnormal state, and then the processor (P) 1 issues an I / O command and the corresponding I / O device access processing function (C1, C2, ... ) 20
It was necessary to confirm the operation of.

However, when setting the states of the input / output devices (T1, T2, ...) 3, as described above, there are some which require a manual operation such as a write-protect error of the floppy disk, and all state setting It was impossible to do unattended. In addition, there are some that are difficult to set, especially in an abnormal state.

In view of the above drawbacks of the prior art, the present invention provides an input / output device of a processor system in which various input / output devices (T1, T2, ...) are connected to a processor (P) via an adapter (A). Access processing functions (C1, C2, ...) for (T1, T2, ...)
〜), The function of the corresponding I / O device access processing function (C1, C2, 〜) is verified without artificially operating the I / O device (T1, T2, 〜). The purpose is to provide a method capable of doing so.

[0011]

FIG. 1 is a block diagram of the principle of the present invention, in which various input / output devices (T1, T2, ...) 3 are adapters.
In the processor system configured to connect to the processor (P) 1 via (A) 2, each input / output device (T1, T2, ...)
3 shows the test method of the I / O device access processing function (C1, C2, ...) 20 provided corresponding to 3. The above problems are solved by the testing method of the input / output device access processing function configured as follows.

Input / output devices (T1, T2, ...) of the processor system in which various input / output devices (T1, T2, ...) 3 are connected to the processor (P) 1 via the adapter (A) 2. This is a verification method of the I / O device access processing function (C1, C2, ...) 20 for 3, and the I / O devices (T1, T2, ~) As a mechanism for setting the pseudo state of the access result of 3, the pseudo fault setting instruction and the pseudo access result set by the pseudo fault setting instruction in the input / output processing access processing function (C1, C2, ...) 20 units A register (S1, S2, ...) 21 and a flag 210 for instructing whether the pseudo access result register (S1, S2, ...) 21 are valid or invalid are provided, and the pseudo access result register ( S1, S2, ~) 21,
After setting the pseudo state for the input / output device (T1, T2, ...) 3, an input / output command is issued to the input / output device (T1, T2, ...) 3, and the flag 210 is in the "on" state. Then, by returning the pseudo state set in the pseudo access result register (S1, S2, ...) 21 as an access result,
In the I / O device access processing function (C1, C2, ...) 20, processing for the pseudo access result is executed, and a completion notification indicating that the hardware abnormality has occurred is sent to the processor.
(P) 1 is notified, and the normality of the abnormal processing of the I / O device access processing function (C1, C2, ...) 20 is compared with the expected value prepared in advance and whether or not they match. Configure to check.

[0013]

That is, in the verification method of the input / output device access processing functions (C1, C2, ...) According to the present invention, the pseudo instruction processing unit (K) and the pseudo instruction processing are provided on the RAM of the adapter (A). Department
The pseudo access result registers (S1, S2, ...) set by the process in (K) are provided.

The pseudo access result register (S1, S2, ...)
Is composed of a flag and pseudo access result data, and the flag indicates whether the pseudo access result data is valid or invalid.

When the flag is valid, the drivers (D1, D2, ...) are irrespective of the states of the input / output devices (T1, T2, ...).
~) Refers to this pseudo access result register (S1, S2, ...) as an access result, and outputs the pseudo access result data set in the pseudo access result register (S1, S2, ...) to the corresponding input / output. Device access processing function (C1, C2, ~)
To notify.

Further, the instruction determination processing unit (J) is added with a process of calling the pseudo-disorder instruction processing unit (K) when the received instruction is a pseudo-disorder instruction. Hereinafter, the procedure of the pseudo obstacle process will be described with reference to FIG.

The processor (P) has an input / output device (T1,
Prepare the flag corresponding to T2, ...) and the data of the pseudo access result, and issue the pseudo failure instruction to the adapter (A). This pseudo instruction is sent from the processor (P) to the adapter.
(A) has a function to notify this pseudo access result data. Inside the adapter (A) that received the imitation command,
The instruction determination processing unit (J) determines that the instruction is a pseudo obstacle instruction and calls the pseudo instruction instruction processing unit (K).

The pseudo failure instruction processing unit (K) sets the pseudo access result data notified from the processor (P) in the pseudo access result registers (S1, S2, ...). This completes the preparation for imitation.

Next, the processor (P) is the input / output device (T1, T
I / O commands are issued to (2, ...). Inside the adapter (A) that has received the input / output instruction, the instruction determination processing unit (J) determines that it is an input / output instruction and calls the designated input / output device access processing function (C1, C2, ...). .

Further, the input / output device access processing function (C1, C
2, ~) calls the corresponding driver (D1, D2 ~). The corresponding driver (D1, D2, ...) refers to the flag of the pseudo access result data of the corresponding pseudo access result register (S1, S2, ...), and if it indicates invalid, performs the conventional processing. .

However, when the flag is valid, the value of the pseudo access result register (S1, S2, ...) is used as the access result of the input / output device (T1, T2, ...) and the input / output device access processing function ( Notify C1, C2, ...) and disable the above flag.

This makes it possible to simulate various states of the input / output devices (T1, T2, ...) Only by issuing the pseudo-disorder instruction from the processor (P). The contents of the pseudo access result registers (S1, S2, ...) are returned to the I / O device access processing functions (C1, C2, ...), and the input corresponding to each I / O device (T1, T2, ...) is unattended. The effect that the function of the output device access processing function (C1, C2, ...) can be verified can be obtained.

[0023]

Embodiments of the present invention will be described in detail below with reference to the drawings. The above-mentioned FIG. 1 is a block diagram of the principle of the present invention.
FIG. 4 is a diagram showing an example of the present invention.

In the present invention, various input / output devices (T1,
T2, ~) 3 via adapter (A) 2 to processor (P)
The input / output device of the processor system connected to 1.
(T1, T2, ...) 3 I / O device access processing function (C
1, C2, ...) 20 to verify each I / O device (T) inside the adapter (A) 2 according to the instruction from the processor (P) 1.
1, T2, ...) As a mechanism for setting the pseudo state of the access result of 3, the pseudo fault setting instruction and the I / O processing access processing function (C1, C2, ...) 20
Pseudo access result register (S1, S2,
~) 21 and the pseudo access result register (S1, S2, ~) 21
And a flag 210 for instructing whether the flag is valid or invalid, and when the I / O instruction is issued to the I / O device (T1, T2, ...) 3 set in the pseudo access result register by the pseudo fault setting instruction, the flag 210 Is on, the corresponding I / O device access processing function (C1, C2, ...) is set as the access result using the pseudo state set in the above pseudo access result register (S1, S2, ...) 21. Means to notify
It is a necessary means for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

A method of verifying the input / output device access processing function of the present invention will be described below with reference to FIG. 2 while referring to FIG. In this embodiment, a case of verifying the function of the input / output device access processing function (C2) 20 when a hardware abnormality occurs in the input / output device (T2) 3 will be described.

The processor (P) 1 has an input / output device (T
2) The expected value of the completion notification of the input / output instruction when a hardware error occurs in 3 is prepared internally, and the pseudo access result register (S1, S2, ...) 21 of the present invention is set to the pseudo access result. A pseudo fault setting instruction (sometimes called a pseudo fault instruction) that transfers and sets data and flags is provided.

The pseudo access result data in this case is converted into the pseudo access result registers (S1, S2, ...) Of the present invention.
21 and the flag 210 of the pseudo access result register (S1, S2, ...) 21 to set the flag 2 of the pseudo access result register (S2) 21 for the corresponding input / output device (T2) 3.
Only 10 is enabled and the pseudo access result register (S2)
Prepare pseudo access result data and a flag for setting "hard error" in 21 pseudo access results, and issue the above pseudo failure instruction.

In the adapter (A) 2 that has received the pseudo-instruction command, the instruction determination processing unit (J) 22 determines that it is a pseudo-instruction instruction and calls the pseudo-instruction processing unit (K) 22a. The pseudo failure instruction processing unit (K) 22a sets the pseudo access result data and flag data notified from the processor (P) 1 in the pseudo access result register (S1, S2, ...) 21 of the present invention. .

At this point, the pseudo access result register
In (S1, S2, ...) 21, the flag 210 of the pseudo access result register (S2) 21 corresponding to the input / output device (T2) 3 is valid, and "hard error" is set in the pseudo access result.

Next, the processor (P) 1 is an input / output device (T2).
Issue an I / O command to 3. Inside the adapter (A) 2 that has received the input / output command, the command determination processing unit
It is determined that (J) 22 is an input / output instruction, and the corresponding input / output device access processing function (C2) 20 is called.

The called input / output device access processing function (C
2) 20 calls the driver (D2) 23. Driver (D2) 23
Refers to the flag of the pseudo access result register (S2) 21, and since this is valid, the pseudo access result register (S2)
2) Notify the I / O device access processing function (C2) 20 of the "hard error" set in 21, and invalidate the above flag 210.

The input / output device access processing function (C2) 20 executes the processing when a hardware abnormality occurs in the input / output device (T2) 3, and the hardware abnormality is detected via the completion processing unit (E) 24. The processor (P) 1 is notified of the completion notification (information that the hardware error is converted into a predetermined code) that the error occurred.

The processor (P) 1 uses the value of this completion notification.
(Code) is compared with the expected value (Code) of the completion notification of the I / O command when a hardware error occurs in the I / O device (T2) 3 prepared in advance, and it is determined whether they match. The normality of the abnormal processing of the input / output device access processing function (C2) 20 is confirmed.

[0034]

According to the present invention, the input / output devices (T1, T2, ...) Are only required to issue pseudo-instruction instructions from the processor (P).
It becomes possible to imitate various states of, and it becomes possible to verify the functions of the input / output device access processing functions (C1, C2, ...) unattended. Also, on the processor (P) side, I / O devices (T1, T2,
By preparing the access result data of (~) (pseudo access result data: hardware abnormality data), it is possible to perform an abnormality test that is difficult to actually occur, thus reducing the test time and improving the quality. effective.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram illustrating a conventional method of verifying an access processing function of an input / output device.

[Explanation of symbols]

1 Processor (P) 2 Adapter
(A) 20 I / O device access processing function (C1, C2, ...) 21 Pseudo access result register 210 Flag 22 Instruction judgment processing section (J) 22a Pseudo-obstruction instruction processing section (K) 23 Driver (D1, D2, ...) 24 Completion processing section (E) 3 I / O device (T1, T2, ...) Pseudo-fault setting command (pseudo-fault command) I / O command completion notification

Claims (1)

[Claims] 1. An input / output device access processing function (20) for an input / output device (3) of a processor system in which various input / output devices (3) are connected to a processor (1) through an adapter (2). ), The pseudo fault setting instruction () and the pseudo fault setting instruction () are set as a mechanism for setting the pseudo state of the access result of each I / O device (3) in the adapter (2) according to the instruction from the processor (1). , The pseudo fault setting instruction ()
Pseudo access result register (21) set to 0) unit,
A flag (210) for instructing whether the pseudo access result register (21) is valid or invalid is provided, and the pseudo access result register (21) is set to the input / output device (3) by the pseudo fault setting instruction (). After setting the pseudo state, input / output command () to the input / output device (3).
Is issued and the flag (210) is in the "on" state, the pseudo state set in the pseudo access result register (21) is returned as an access result, and the input / output device access processing function In (20), the process for the pseudo access result is executed, the completion notification () indicating that the hardware abnormality has occurred is notified to the processor (1), and the expected value prepared in advance is compared with A method of verifying an access processing function for an input / output device, characterized by confirming the normality of abnormal processing of the input / output device access processing function (20) depending on whether or not it is done.