JPS63254501A - Sequence controller - Google Patents

Abstract

PURPOSE:To ensure the hitherto execution of a normal memory part by noticing a fact that all programs of a processor of a sequencer are carried out in a total, cyclic, simple and sequential way and skipping only the block of a sequence program part that is under execution at time point when the abnormality occurs. CONSTITUTION:A sequence controller contains a sequence program memory 2 which stores a sequence program divided into blocks completed with each other and a program counter replacement mechanism 6 which reads the contents of a program counter 5 and gives an access to the memory 2 to read out the corresponding instruction. Then the mechanism 6 checks whether said instruction in equal to the head instruction of a block or not and then replaces of addresses if no coincidence is obtained between both instructions. Thus it is possible to ensure a continuous operation despite the temporary abnormality occurring to a sequencer processor. Furthermore the working can be locally interrupted only at a faulty area even in case a parity error occurs to a memory, etc., as a constant error. Thus a continuous operation is ensured for a system as a whole.

Description

[Detailed description of the invention] [Industrial application field] The present invention is a programmable sequence control device.

In particular, the present invention relates to a sequence control device that performs processing when an abnormality occurs in a processing device.

[Conventional technology]

With conventional programmable controllers, when an abnormality such as a parity error occurs in the processing device, (1) the method of immediately stopping the processing device (2) re-executing the instruction word that was being executed when the abnormality occurred, and even if the abnormal state still remains If this continues, this abnormality is considered to be a permanent solid error, and the processing device is immediately stopped. If you run it again and it works normally, you can continue processing as if this is just a temporary malfunction.

etc. are being carried out. The sequence is described in JP-A-61-40605, JP-A-61-11805, and JP-A-61-145605.

[Problems that the invention attempts to solve]

The above conventional technology is permissible for general-purpose computers that perform batch processing, etc., but when controlling production equipment online and in real time, production equipment operation is interrupted when an abnormality occurs, so it is difficult to restart operation. requires extensive restart operations.

Therefore, online real-time control computers are operated using a multiple redundant computer system, typically a dual system, and when an abnormality occurs, operation is immediately transferred to the normal system, and the system is constructed in such a way that equipment operation is not interrupted as much as possible. .

However, in the field of sequencers, low prices are required, and measures to improve system reliability by creating a redundant multiplex system as described above are not taken in principle. There is a need for a means to minimize interruptions in operation even if an abnormality occurs in the processing equipment.

The purpose of the present invention is, of course, to enable operation to continue even if a temporary abnormality occurs in a sequencer processing device, and even if a parity error occurs as a permanent error in a memory or the like.

The present invention provides a sequence control device that allows the operation of the entire system to continue by locally interrupting the operation of only the part where the abnormality has occurred.

[Means for solving problems]

The present invention has a sequence program memory in which a sequence program is stored separately for each complete block, and a sequence program memory that reads the contents of a program counter when an abnormality occurs, reads out the corresponding instruction, and reads out the corresponding instruction. It consists of means for checking whether or not it is the first instruction of the block, and updating the address if it is not the first instruction.

[Effect]

According to the present invention, the program execution of the processing device of the sequencer takes into account the fact that the entire program is executed cyclically and simply sequentially, and only the block of the sequence program part that was being executed when the abnormality occurred is executed. It can be skipped and the normal memory part can be executed as is.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1, 2, and 3. The processing device 1 of the sequencer has a program memory 2
Sequence instructions 301, 302, etc. stored in
... are executed sequentially. Specifically, to execute an instruction, the program start address stored in the program start address storage register 4 is set in the program counter 5, and the sequence instruction indicated by the contents of the program counter 5 is executed. When the instruction is correctly executed, the program counter update mechanism 6 operates to update the contents of the program counter 5 by one address, and as a result, the number of sequence instructions is executed. In this way, the sequence program has sequence instructions 301, 302...
. . . The commands are executed one by one one after another.

Then, when the processing device executes a sequence program end instruction 309 indicating the end of the sequence program, the contents of the program start address storage register 4 are transferred to the program counter 5, and the operation is repeated again from the start instruction 301 of the sequence program. In this way, from the sequence program first command 301, the sequence program final command (the last command corresponding to the relay circuit) 308 and the sequence program end command (all equivalent to relay sequence commands have been completed, so return to the beginning of the program. The sequence program up to 309 (instruction 309) is repeatedly executed.

Next, consider a case where a processing device abnormality such as a memory parity error occurs during program execution.

Devices such as sequencers that are used on-site with extremely high electrical noise levels are likely to malfunction due to transient electrical noise. However, in the case of such a temporary noise, it is possible to avoid a run-down by retrying the instruction word that caused the abnormal operation and continuing the process if the retry result is normal.

However, the problem is that when an abnormality occurs due to permanent destruction of internal components of a processing device or the like, it is generally assumed that the processing contents cannot be guaranteed and the processing is stopped and the system is brought down. However, in the present invention, when an abnormality occurs, only the abnormal part is removed from the processing and the operation is continued by making the most of it.

Therefore, when a processing device error occurs during the execution of a sequence program, let us consider the range over which the result of the sequence operation becomes undefined. As shown in Figure 3, a sequence circuit generally has a common line on the voltage application side and a common line on the ground side, and various input/output contacts and output coils can be connected between the two common lines as appropriate by ORing or ANDing. A desired sequence control logic is constructed by combining them. At this time, as shown in the circuit part surrounded by the broken line in Figure 3, a sequence circuit block is one in which there are no connection wires other than two common wires between the symbols of various contacts/output coils, and the minimum number of connection wires is the same. I'll call you. In this sequence block, the first instruction is always a new instruction generated from the common line, and the final instruction is always completed with an output coil instruction that outputs the calculation result, and there is no wiring connection with other sequence circuit blocks.

Therefore, it can be said that the sequence calculation is completed for each sequence circuit block, and that the sequence calculation process is initialized each time the calculation of each block is started.

An example of a sequence circuit block is shown in FIG. Block B
l, B2. B3 is a sequence block. Each block is independently connected to the voltage application side common line and the ground side common line. Figure 2 shows each of the above blocks Bl and B2.
．． The contents of the sequence command in B3 are shown.

In other words, when a hardware abnormality such as a parity error occurs in a certain sequence circuit block, the calculation result becomes undefined only in the corresponding sequence circuit block where the hardware abnormality occurred, and in the next block. The sequence circuit block can return to normal operation again.

Note that in the sequencer, a sequence program is repeatedly executed at a fixed period (sequence cycle). Therefore, when the program execution of one sequence cycle is completed and the program moves to the next sequence cycle, the instruction words that were skipped in the previous sequence cycle are executed again without any conditions. If the trouble that occurred in the previous sequence cycle is temporary, the current program execution will be executed normally (this can be considered as a de facto retry process in the past). In addition, if the travel is permanent, skip processing will be performed in the same way as the program in the abnormal part was skipped in the previous sequence cycle, and only programs without problems will be executed.

This will be explained in more detail. Suppose that a processing device abnormality such as a memory parity error occurs during a program. At the same time as the error occurs, the processing device 1 notifies the next sequence circuit block start address detection mechanism 7 of the occurrence of the abnormality. The next sequence circuit block first address detection mechanism 7 learns the abnormality occurrence address from the program counter 5, and sequentially reads out the sequence programs stored after that address, and checks whether the instruction word is the first instruction of the next sequence circuit block. Check whether or not. If it is the first instruction of the next sequence circuit block, the address is set in the program counter 4 and execution of the processing device 1 is restarted. With such an abnormality processing method, most of the system can continue to operate normally by simply skipping local processing related to the defective part.

Next, a specific example of the configuration and operation of the sequence circuit block head address detection mechanism will be described.

Prior to that, a program creation method using the sequence ladder circuit diagram method to which the present invention is applied will be explained. When creating a sequence ladder program using a programming device, make sure that the breaks in sequence circuit blocks can be easily identified for future reasons. In the embodiment of the present invention, the most significant bit MSB of the first instruction sequence end instruction of one sequence circuit block is set to 1.

For other instruction words, the MSB is set to O so that it is possible to determine the break in the sequence circuit block. As a result, only one sequence circuit block is read out from the entire sequence program by the name of the output relay in that sequence circuit block, these sequence instructions are converted into a ladder circuit diagram format, and this is displayed on the display device. However, it is convenient if there is a break between the sequence circuit blocks when modifying the program or monitoring the operation of each contact/output ON10FF state of the circuit. This sequence circuit block break mark is the CPU
It is also effective in identifying how many sequence operations are undefined when a problem occurs in the main unit.

The next sequence circuit block head address detection mechanism 7 is shown in FIG.

In FIG. 4, the next sequence circuit block head address detection mechanism 7 is the processing device 1. It is created by a microcomputer that is directly connected to the program counter 5 and the like via a bus, and the program shown in FIG. 4 is stored as firmware. When the processing device 1 discovers an abnormality, it stops executing the program, issues an abnormality interrupt, and starts the program shown in FIG. 4. When the execution of the program starts, the contents of the program counter 5 are first retrieved (step 7).
01). This indicates the next address of the instruction in which the abnormality has occurred, and the contents of this address are read and the next instruction word is taken out from the sequence program memory 2 (step 70).
2). The most significant pit MSB of the next extracted instruction word is 11
``'' and determines whether it is a start address instruction (step 703).In the case of a block start address instruction or a sequence program end instruction, the most significant bit is "1"; in other cases, it is "0". Yes.If it is not the first address instruction as a result of the determination, step 701
After incrementing the contents of the program counter fetched in step 704 by one instruction and updating the address of the next instruction word in step 704, the program returns to step 702 and checks again.

If it is the first address, the program counter is written (step 705), the program execution is restarted in step 706, and the process ends.

As described above, steps 702, 703, and 704 are sequentially repeated to search for the first instruction of the next block, and when the first instruction of the first block is found, the address of the sequence program memory 2 where the first instruction is stored is sent to the program counter 5. After setting, the processing device 1 is restarted and the processing is terminated (steps 705 and 706).

FIG. 2 shows an example in which an abnormality occurs in the middle of block B2. For up to three steps counting from the occurrence of this abnormality, the MSB is "0" and is skipped one after another.Then, at the fourth step, the MSB becomes "1", indicating that the next new block has appeared.

In the figure, this new block is block B3.

〔Effect of the invention〕

According to the present invention, when an abnormality occurs in a sequence program, only the part where the abnormality occurs can be isolated and the remaining normal parts can be executed as is, without bringing down the entire system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the contents of the sequence program memory of the present invention, FIG. 3 is a diagram showing a sequence block of the present invention, and FIG. 4 is a diagram showing the next example of the present invention. FIG. 3 is a processing flow diagram of a sequence circuit block head address detection mechanism. 1... Processing device, 2... Sequence program memory.

Claims (1)

[Claims] 1. A sequence program memory that stores a sequence program divided into mutually complete blocks;
The program counter specifies the address of the program, and if an error occurs during sequence program processing,
The first step is to read the contents (address) of the program counter.
a second means for accessing the address of the sequence program memory specified by the counter; and a second means for accessing the address of the sequence program memory specified by the counter, and determining that the instruction word at the time of the occurrence of the abnormality is the beginning of the divided block by looking at the corresponding instruction word obtained from the memory by the access. a third means for determining whether or not the instruction is an instruction; and as a result of the determination, if it is not the first instruction, the access address is updated and the updated address is used in the sequence program within the second means in place of the contents of the program counter. A sequence control device comprising a fourth means used as a memory address, and a fifth means for writing a program counter and restarting program execution when it is determined that the instruction is the first instruction.