JPS5988830A - 化合物半導体基板表面上にパッシベーション層を形成する方法 - Google Patents
化合物半導体基板表面上にパッシベーション層を形成する方法Info
- Publication number
- JPS5988830A JPS5988830A JP58146793A JP14679383A JPS5988830A JP S5988830 A JPS5988830 A JP S5988830A JP 58146793 A JP58146793 A JP 58146793A JP 14679383 A JP14679383 A JP 14679383A JP S5988830 A JPS5988830 A JP S5988830A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- substrate
- arsenic
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Weting (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44065482A | 1982-11-10 | 1982-11-10 | |
| US440654 | 1982-11-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5988830A true JPS5988830A (ja) | 1984-05-22 |
| JPH0218579B2 JPH0218579B2 (enExample) | 1990-04-26 |
Family
ID=23749634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58146793A Granted JPS5988830A (ja) | 1982-11-10 | 1983-08-12 | 化合物半導体基板表面上にパッシベーション層を形成する方法 |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0108910B1 (enExample) |
| JP (1) | JPS5988830A (enExample) |
| DE (1) | DE3379701D1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247349A (en) * | 1982-11-16 | 1993-09-21 | Stauffer Chemical Company | Passivation and insulation of III-V devices with pnictides, particularly amorphous pnictides having a layer-like structure |
| AU2992784A (en) * | 1983-06-29 | 1985-01-03 | Stauffer Chemical Company | Passivation and insulation of iii-v devices with pnictides |
| DE19900052A1 (de) * | 1999-01-04 | 2000-07-13 | Siemens Ag | Halbleiterchip und Verfahren zur Herstellung |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3959098A (en) * | 1973-03-12 | 1976-05-25 | Bell Telephone Laboratories, Incorporated | Electrolytic etching of III - V compound semiconductors |
-
1983
- 1983-08-12 JP JP58146793A patent/JPS5988830A/ja active Granted
- 1983-10-05 DE DE8383109942T patent/DE3379701D1/de not_active Expired
- 1983-10-05 EP EP83109942A patent/EP0108910B1/en not_active Expired
Non-Patent Citations (1)
| Title |
|---|
| J.VAC SCI TECHNOL * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0108910A3 (en) | 1986-09-10 |
| JPH0218579B2 (enExample) | 1990-04-26 |
| DE3379701D1 (en) | 1989-05-24 |
| EP0108910B1 (en) | 1989-04-19 |
| EP0108910A2 (en) | 1984-05-23 |
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