DE3379701D1 - Method of forming a passivated compound semiconductor substrate - Google Patents
Method of forming a passivated compound semiconductor substrateInfo
- Publication number
- DE3379701D1 DE3379701D1 DE8383109942T DE3379701T DE3379701D1 DE 3379701 D1 DE3379701 D1 DE 3379701D1 DE 8383109942 T DE8383109942 T DE 8383109942T DE 3379701 T DE3379701 T DE 3379701T DE 3379701 D1 DE3379701 D1 DE 3379701D1
- Authority
- DE
- Germany
- Prior art keywords
- forming
- semiconductor substrate
- compound semiconductor
- passivated
- passivated compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10W74/43—
-
- H10W74/137—
-
- H10W74/481—
-
- H10P14/6306—
-
- H10P14/68—
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44065482A | 1982-11-10 | 1982-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3379701D1 true DE3379701D1 (en) | 1989-05-24 |
Family
ID=23749634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8383109942T Expired DE3379701D1 (en) | 1982-11-10 | 1983-10-05 | Method of forming a passivated compound semiconductor substrate |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0108910B1 (enExample) |
| JP (1) | JPS5988830A (enExample) |
| DE (1) | DE3379701D1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247349A (en) * | 1982-11-16 | 1993-09-21 | Stauffer Chemical Company | Passivation and insulation of III-V devices with pnictides, particularly amorphous pnictides having a layer-like structure |
| IL72244A (en) * | 1983-06-29 | 1988-03-31 | Stauffer Chemical Co | Passivation and insulation of iii-v semiconductor devices with pnictides |
| DE19900052A1 (de) * | 1999-01-04 | 2000-07-13 | Siemens Ag | Halbleiterchip und Verfahren zur Herstellung |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3959098A (en) * | 1973-03-12 | 1976-05-25 | Bell Telephone Laboratories, Incorporated | Electrolytic etching of III - V compound semiconductors |
-
1983
- 1983-08-12 JP JP58146793A patent/JPS5988830A/ja active Granted
- 1983-10-05 DE DE8383109942T patent/DE3379701D1/de not_active Expired
- 1983-10-05 EP EP83109942A patent/EP0108910B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0218579B2 (enExample) | 1990-04-26 |
| EP0108910B1 (en) | 1989-04-19 |
| EP0108910A2 (en) | 1984-05-23 |
| EP0108910A3 (en) | 1986-09-10 |
| JPS5988830A (ja) | 1984-05-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |