JPS5984459A - Gate turn off thyristor module - Google Patents

Gate turn off thyristor module

Info

Publication number
JPS5984459A
JPS5984459A JP57194823A JP19482382A JPS5984459A JP S5984459 A JPS5984459 A JP S5984459A JP 57194823 A JP57194823 A JP 57194823A JP 19482382 A JP19482382 A JP 19482382A JP S5984459 A JPS5984459 A JP S5984459A
Authority
JP
Japan
Prior art keywords
terminal
gate
gto
cathode
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57194823A
Other languages
Japanese (ja)
Inventor
Toshihiro Nakajima
中嶋　利廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57194823A priority Critical patent/JPS5984459A/en
Publication of JPS5984459A publication Critical patent/JPS5984459A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To prevent the decrease of a controllable current except the unbalance between two devices by a method wherein cathode and gate terminals of two GTOSCR's contained in a package are provided close to each GTO chip. CONSTITUTION:On the package 1 with built-in GTO1 and GTO2, an A1 anode terminal 2, a K1 cathode terminal 3, and an A2-K1 common main electrode terminal 4 are arranged on a straight line, a K1 cathode terminal 5 and a G1 gate terminal 6 are arranged at the end part on the side of the terminal 2 as gate trigger terminals of the GTO1, and a K2 cathode terminal 7 and a G2 gate terminal 8 for the GTO2 are likewise arranged on the side of the terminal 4. Thereby, wiring strengths from the GTO2 to the K2 terminal 7 and the G2 terminal 8 are shortened, and the decrease of the controllable current or the unbalance of characteristics can be prevented. Besides, in case of mounting a flywheel diode and a snubber circuit outside, the length of a connection lead wire can be shortened, and then power loss can be reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はゲートターンオフサイリスタ（ＧＴＯ）モジ
ュールのゲートトリガ一端子の位置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the position of a gate trigger terminal of a gate turn-off thyristor (GTO) module.

〔従来技術〕[Prior art]

一般に、ゲート信号によってターンオン、ターンオフす
る機能をもつ半導体装置としてゲートターンオアサイリ
スタ（Ｇａｔｅ−Ｔｕｒｎ−Ｏｆｆ−Ｔｈｙｒｉｓｔｏ
ｒ　：ＧＴＯ）がある。近年ＧＴＯは新たな電力半導体
装置として注目をあびており、２ＯＡから現在では１０
０ＯＡの陽極電流を制御可能なものが開発されている。In general, a gate-turn-off-thyristor is a semiconductor device that has the function of turning on and turning off by a gate signal.
r :GTO). In recent years, GTO has attracted attention as a new power semiconductor device, and from 2OA to 10A today.
A device capable of controlling anode current of 0OA has been developed.

また、ＧＴＯは省エネルギに対しても有効であり、可制
御電流が３００Ａ以下のものに対しては特にモジュール
化による小形パッケージ化が進められている。Furthermore, GTO is also effective for energy saving, and compact packaging through modularization is being promoted especially for those with a controllable current of 300 A or less.

第１図は従来のＧＴＯモジュールの一例の概略外観を示
す斜視図で、この例ではＧＴＯチップを２個内蔵したパ
ッケージ〔１１に、第１のＧＴＯのアノード（ＡＩアノ
ードという）端子（２）と第２のＧＴＯのカソード（Ｋ
２カソードという）端子（３）と第２０ＧＴＯのアノー
ド（Ａ２アノードという）及び第１のＧＴＯのカソード
（Ｋｌカソードという）を結んだ共通主電極端子（４１
とが一直線上に配列され、Ａｌアノード端子（２）側の
パッケージ【１１の上端部に第１のＧＴＯのカソード（
Ｋｌカソードという）端子（５）および第１のＧＴＯの
ゲー１−　（Ｇｌゲートという）端子（６）が第１のＧ
ＴＯのゲートトリガー用として、また第２７７）　Ｇ’
ＩＩ：のカソード（Ｋ２カソードという）端子（７）お
よび第２０ＧＴＯのゲート（Ｇ２ゲートという）端子（
８）が第２のＧＴＯのゲー））リガー用♂して配列され
ている。第２図はこのパッケージ（月の中に内蔵された
ＭｌのＧＴＯ（ＧＴＯＩ）と第２のＧＴＯ（ＧＴＯ２）
　七ノ結線配置図である。FIG. 1 is a perspective view showing the general appearance of an example of a conventional GTO module. Cathode of the second GTO (K
A common main electrode terminal (41
are arranged in a straight line, and the first GTO cathode (
A terminal (5) (referred to as Kl cathode) and a terminal (6) (referred to as Gl gate) of the first GTO
For the gate trigger of TO, also No. 277) G'
II:'s cathode (referred to as K2 cathode) terminal (7) and the gate (referred to as G2 gate) terminal of the 20th GTO (
8) is arranged as a male for the second GTO game)) rigger. Figure 2 shows this package (Ml's GTO (GTOI) built into the moon and the second GTO (GTO2)).
It is a seven connection arrangement diagram.

従来のＧＴＯモジュールは以上のように構成されており
、第２図に示すＧＴＯ２をターンオン及びターンオフす
るリード線が非常に長く配線されており、リード線のイ
ンダクタンスが大きくなることによって、ターンオフ時
の特性が悪くなり、可制御電流が低下するようなことが
しばしば生じた。また、ＧＴＯＩとＧＴＯ２とのリード
線長の差異による特性のアンバランスを生じたりした。The conventional GTO module is configured as described above, and the lead wires for turning on and turning off the GTO2 shown in Figure 2 are wired very long, and the inductance of the lead wires becomes large, resulting in poor characteristics at turn-off. It often happened that the controllable current deteriorated and the controllable current decreased. Furthermore, an imbalance in characteristics occurred due to the difference in lead wire length between GTOI and GTO2.

まに２組立上においでも、ＧＴＯのゲート電流が大きく
なるにつれてリード線径を太くする必要があり、特に第
２図にと３） 示すＧＴＯ２から０２ダ一ト端子ｍ　、に２カソード端
子（′ρ 藤−へ結線するリード線が長く、リード線径が大きいと
曲りにくくなる。また、リード線の配置が所定の位置に
保持することも非常に難かしく、その上に経済性に欠け
る等の欠点があった。Even when assembling GTO2, it is necessary to increase the diameter of the lead wire as the gate current of the GTO increases. If the lead wire connected to ρ Fuji- is long and the diameter of the lead wire is large, it becomes difficult to bend.In addition, the arrangement of the lead wire makes it very difficult to hold it in a predetermined position, and on top of that, it is not economical. There were drawbacks.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するこ
とを目的とし、パッケージの上面の両端にカンード端子
、ゲート端子を配置することにより、２個のＧＴＯチッ
プの各々の近い位置にカソード端子、ゲート端子の配列
が可能となり、電気的特性がすぐれ、しかもリード線の
配線が容易で、リード線の経済性にもすぐれたＧＴＯモ
ジュールを提案するものである。The purpose of this invention is to eliminate the above-mentioned drawbacks of the conventional device, and by arranging the cando terminal and the gate terminal at both ends of the top surface of the package, the cathode terminal and the gate terminal are placed close to each of the two GTO chips. The present invention proposes a GTO module that allows gate terminals to be arranged, has excellent electrical characteristics, is easy to wire lead wires, and is economical for lead wires.

〔発明の実施例〕[Embodiments of the invention]

第３図はこの発明の一実施例の概略外観を示す斜視図で
、第４図はそのパッケージの中に内蔵された２つのＧＴ
Ｏチップの結線配置図である。第１図、第２図の従来例
と同等部分は同一符号で示す。FIG. 3 is a perspective view showing a schematic appearance of an embodiment of the present invention, and FIG. 4 shows two GTs built into the package.
It is a wiring arrangement diagram of an O chip. Components equivalent to those of the conventional example shown in FIGS. 1 and 2 are designated by the same reference numerals.

２つのＧＴＯテップＧＴＯＩおよびＧＴＯ２ｉ内蔵した
パッケージ＋１１　Ｋ　Ａｌアノード端子（２１、Ｋ２
カンード端子（３１およびＡ２アノードとＫｌカソード
との共通主市極端子（４１が一直線上に配列され、パッ
ケージ（１］のＡ１アノード端子（２）側の端部にＧＴ
ＯＩのゲートトリガ用端子としてに１カソード端子（５
）およびＧ１ゲート端子（６）が配置されており、パッ
ケージ（１）の上記共通主電極端子ｆ４１側の端部にＦ
ｉＧＴＯ２のゲートトリガ端子としてに２カンード端子
（７１およびＧ２ゲート端子＋８１が配置されている。Package with built-in two GTO tips GTOI and GTO2i + 11K Al anode terminal (21, K2
The cando terminal (31 and the common main terminal (41) of the A2 anode and Kl cathode are arranged in a straight line, and the GT
One cathode terminal (5
) and G1 gate terminal (6) are arranged, and F is located at the end of the package (1) on the common main electrode terminal f41 side.
Two cando terminals (71 and G2 gate terminal +81) are arranged as gate trigger terminals of iGTO2.

この実施例のＧＴＯモジュールは以上のように構成され
ているので、第４図に示すように、ＧＴＯ２からに２カ
ンード端子（７１およびＧ２ゲート端子（８１へのリー
ド線の配線長力（従来のモジュールにおける該リード線
の配線長に比して極めて短かくなり、前述の従来装置の
欠点は除去される。Since the GTO module of this embodiment is configured as described above, as shown in FIG. The wiring length of the lead wire in the module is extremely short, and the above-mentioned drawbacks of the conventional device are eliminated.

また、ＧＴＯモジュールにはＧＴＯの電力損失を減少さ
せる目的で、第５図に示すようなフライホイルダイオー
ドＤＦ　、およびコンデンサＣ８と抵抗Ｒ８とダイオー
ドＤＳとからなるスナバ回路を外部に接続する必要があ
る。このような場合にもフライホイルダイオードおよび
スナバ回路の接続のリード線の配線長を短くすることに
よって電力損失の少ないＧＴＯモジュールが得られ、こ
の発明になるモジュールのカソード端子（５１、（７１
の配置はこれに適している。Furthermore, in order to reduce the power loss of the GTO, it is necessary to externally connect a flywheel diode DF as shown in Figure 5, and a snubber circuit consisting of a capacitor C8, a resistor R8, and a diode DS to the GTO module. . Even in such a case, a GTO module with low power loss can be obtained by shortening the wiring length of the lead wire for connecting the flywheel diode and the snubber circuit.
The arrangement is suitable for this.

また、上記実施例ではパッケージ内に２個のＧＴＯチッ
プのみを収容した場合を示したが、ＧＴＯチップのみで
なく、ダイオード、抵抗、コンデンサなとの電子部品を
一緒に収容し友場合にも、この発明になる電極配置は効
果を奏する。In addition, although the above embodiment shows the case where only two GTO chips are housed in the package, it is also possible to house not only the GTO chips but also electronic components such as diodes, resistors, and capacitors together. The electrode arrangement according to this invention is effective.

第６図（ａ）　、　（ｂ）はこの発明の他の実施例を示
す配線配置図で、第３図、第４図の実施例と同様の効果
を有することは明らかであろう。FIGS. 6(a) and 6(b) are wiring layout diagrams showing another embodiment of the present invention, and it is clear that it has the same effects as the embodiment of FIGS. 3 and 4.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明になるＧＴＯモジュール
では１つのパッケージに収容し定２つのＧＴｏのカソー
ド端子およびゲート端子をそれぞれのＧＴＯチップの近
くに位置させたので、両ＧＴＯの間でのアンバランスは
なくなり、可制御゛電流の低下も防止でき、パッケージ
内配線も容易となり、経済性を向上できる。As explained above, the GTO module according to the present invention is housed in one package and the cathode terminal and gate terminal of the two GTOs are located close to each GTO chip, so there is no imbalance between the two GTO chips. This eliminates the problem of controllability, prevents a drop in current, and facilitates wiring within the package, improving economic efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＧＴ’Ｏモジュールの外形斜視図、第２
図はこのパッケージ内の結線配置図、第３図ほこの発明
の一実施例の外形斜視図、第４図はこの実施例における
パッケージ内の結線配置図、第５図はＧＴＯＫフライホ
イルグイオードおよびスナバ回路を接続した場合の回路
図、第６図はこの発明の他の実施例におけるパッケージ
内の結線配置図である。 図において、（１）はパッケージ、（２）は第１のＧＴ
Ｏのアンード主電路端子、（３）け第２のＧＴＯのカソ
ード主電路端子、（４）は第２のＧＴＯのアノードと第
１のＧＴＯの′カソードと？結んだ共通主准路端子、（
５］は第１のＧＴＯの補助回路用カソード端子、（ｂ）
は第１のＧＴＯのゲート端子、＋７１は第２のＧＴＯの
補助回路用カソード端子、（８）は第２のＧＴＯのケー
ト端子である。 なお、図中同一符号は同一または相当部分を示す。 代理人　葛　野　信　−（外１名） 第１図 第２図 第３図 第４図 第５図 Ｆ 第６図 （（Figure 1 is a perspective view of the conventional GT'O module;
3 is an external perspective view of one embodiment of the invention, FIG. 4 is a wiring arrangement diagram inside the package in this embodiment, and FIG. 5 is a diagram of the GTOK flywheel guide and A circuit diagram when a snubber circuit is connected, and FIG. 6 is a wiring arrangement diagram inside a package in another embodiment of the present invention. In the figure, (1) is the package, (2) is the first GT
(3) is the cathode main circuit terminal of the second GTO, and (4) is the anode of the second GTO and the 'cathode of the first GTO. Connected common main junction terminals, (
5] is the cathode terminal for the auxiliary circuit of the first GTO, (b)
is the gate terminal of the first GTO, +71 is the auxiliary circuit cathode terminal of the second GTO, and (8) is the gate terminal of the second GTO. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 F Figure 6 ((

Claims (1)

【特許請求の範囲】[Claims] （１）１つのパッケージ内に２個のゲートターンオフサ
イリスタを収容してなるものにおいて、主電流路用の主
電極端子を上記パッケージの中央部に配設し、ゲート制
御回路などの補助回路用のゲート端子およびカソード端
子をそれぞれの上記ゲートターンオアサイリスタの収容
位置に近い上記パッケージの両端部に設けたことを特徴
とするゲートターンオフサイリスタモジュール。(1) In a device in which two gate turn-off thyristors are housed in one package, the main electrode terminal for the main current path is arranged in the center of the package, and the main electrode terminal for the main current path is arranged in the center of the package, and the A gate turn-off thyristor module, characterized in that a gate terminal and a cathode terminal are provided at both ends of the package near the accommodation position of each gate turn-off thyristor.
JP57194823A 1982-11-04 1982-11-04 Gate turn off thyristor module Pending JPS5984459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57194823A JPS5984459A (en) 1982-11-04 1982-11-04 Gate turn off thyristor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57194823A JPS5984459A (en) 1982-11-04 1982-11-04 Gate turn off thyristor module

Publications (1)

Publication Number Publication Date
JPS5984459A true JPS5984459A (en) 1984-05-16

Family

ID=16330841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57194823A Pending JPS5984459A (en) 1982-11-04 1982-11-04 Gate turn off thyristor module

Country Status (1)

Country Link
JP (1) JPS5984459A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63318147A (en) * 1987-06-19 1988-12-27 Mitsubishi Electric Corp Semiconductor device
US5350946A (en) * 1992-06-29 1994-09-27 Fuji Electric Co., Ltd. Semiconductor device with correct case placement feature

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130958A (en) * 1980-02-13 1981-10-14 Semikron Gleichrichterbau Semiconductor forming unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130958A (en) * 1980-02-13 1981-10-14 Semikron Gleichrichterbau Semiconductor forming unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63318147A (en) * 1987-06-19 1988-12-27 Mitsubishi Electric Corp Semiconductor device
US5350946A (en) * 1992-06-29 1994-09-27 Fuji Electric Co., Ltd. Semiconductor device with correct case placement feature

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