JP2536099B2 - MOS gate type bipolar transistor - Google Patents
MOS gate type bipolar transistorInfo
- Publication number
- JP2536099B2 JP2536099B2 JP63280758A JP28075888A JP2536099B2 JP 2536099 B2 JP2536099 B2 JP 2536099B2 JP 63280758 A JP63280758 A JP 63280758A JP 28075888 A JP28075888 A JP 28075888A JP 2536099 B2 JP2536099 B2 JP 2536099B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- bipolar transistor
- emitter
- external lead
- mos gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、たて形バイポーラトランジスタにそのベー
ス電流を供給するMOSFETを集積するMOSゲート形バイポ
ーラトランジスタ(IGBTとも称するが、本願では以下MB
Tと略記する。)とそれに流れる過渡的な電流を抑制す
るバイパスコンデンサを備えたMOSゲート形バイポーラ
トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a MOS gate type bipolar transistor (also referred to as an IGBT, which integrates a MOSFET for supplying its base current to a vertical type bipolar transistor.
Abbreviated as T. ) And a MOS-gate bipolar transistor with a bypass capacitor that suppresses the transient current that flows through it.
バイポーラトランジスタのスイッチング速度を早める
ため、そのベース電流を供給するMOSFETのMOS構造を表
面部に形成したMBTを電力変換装置に用いたとき、負荷
側に事故が発生すると、定格電流の数倍の短絡電流が流
れる。第2図はMBT1のエミッタ・コレクタに電源21を接
続し、ゲート回路22によりゲートに電圧を印加すると電
流ICがコレクタ・エミッタ間に流れるが、短絡電流が流
れるとコレクタ・エミッタ間電圧の急しゅんな変動、す
なわちdv/dtが大きくなり、第2図に破線23で示すよう
にコレクタからゲートへ抜ける電流が流れる。この電流
によりゲート電位が上昇し、事故発生時のピーク電流が
増大し、素子の劣化が生じるという問題点がある。この
問題の解決のために第3図に示すようにゲート・エミッ
タ間にコンデンサ2を接続すると、負荷側の事故発生時
のdv/dtによる電流23を、ゲート・エミッタ間容量と接
続したコンデンサ容量の比で24,25に分流する。これに
より、素子1に流れ込む電流が減少し、ピーク電流が抑
制でき、事故発生時の素子の発生損失を小さくできる。In order to speed up the switching speed of a bipolar transistor, when an MBT with the MOS structure of the MOSFET that supplies its base current formed on the surface is used in a power converter, if an accident occurs on the load side, a short circuit of several times the rated current will occur. An electric current flows. In Fig. 2, when the power supply 21 is connected to the emitter-collector of the MBT1 and a voltage is applied to the gate by the gate circuit 22, a current I C flows between the collector and the emitter, but when a short-circuit current flows, the collector-emitter voltage suddenly increases. A drastic fluctuation, that is, dv / dt becomes large, and a current flowing from the collector to the gate flows as shown by a broken line 23 in FIG. This current causes a problem that the gate potential rises, the peak current at the time of an accident increases, and the element deteriorates. To solve this problem, connect a capacitor 2 between the gate and emitter as shown in Fig. 3, and connect the current 23 due to dv / dt at the time of an accident on the load side with the capacitance between the gate and emitter. The ratio is divided into 24 and 25. As a result, the current flowing into the element 1 is reduced, the peak current can be suppressed, and the loss generated in the element when an accident occurs can be reduced.
第3図に示したようなバイパスコンデンサ2を素子と
同一容器に内蔵する場合、従来は基板配線を利用して、
あるいはワイヤー配線を用いて接続されるのが一般的で
あった。しかし、この時配線長に依るインダクタンスが
大きくなり、過渡的インピーダンスが増大し、事故発生
時に充分な対応がとれなかった。When the bypass capacitor 2 as shown in FIG. 3 is built in the same container as the element, conventionally, using the board wiring,
Or it was common to connect using wire wiring. However, at this time, the inductance depending on the wiring length was increased, the transient impedance was increased, and a sufficient response could not be taken when an accident occurred.
本発明の課題は、上述の欠点を除き、MBTの負荷側の
事故発生時におけるピーク電流を抑制するためのバイパ
スコンデンサの接続によるインダクタンスの増大を防止
したMOSゲート形バイポーラトランジスタを提供するこ
とにある。An object of the present invention is to provide a MOS gate type bipolar transistor which eliminates the above-mentioned drawbacks and which prevents an increase in inductance due to the connection of a bypass capacitor for suppressing the peak current at the time of an accident on the load side of the MBT. .
上記の課題の解決のために、本発明は、MBTとそのゲ
ート・エミッタ間に接続されるバイパスコンデンサを備
えたMOSゲート形バイポーラトランジスタにおいて、MBT
の半導体素体の一側に近接して該MOSゲート形バイポー
ラトランジスタのゲート電極にワイヤを介して接続され
るゲート外部導出端子導体とエミッタ電極にワイヤを介
して接続されるエミッタ外部導出端子導体とが互いに絶
縁して平行に配置され、バイパスコンデンサがゲート外
部導出端子導体とエミッタ外部導出端子導体との間に固
着されたものとする。In order to solve the above problems, the present invention provides an MBT-type bipolar transistor including a MBT and a bypass capacitor connected between its gate and emitter.
A gate external lead-out terminal conductor connected to the gate electrode of the MOS gate type bipolar transistor via a wire in the vicinity of one side of the semiconductor body, and an emitter external lead-out terminal conductor connected to the emitter electrode via a wire. Are insulated from each other and arranged in parallel, and a bypass capacitor is fixed between the gate external lead-out terminal conductor and the emitter external lead-out terminal conductor.
バイパスコンデンサの両電極が、MBTのゲート外部導
出端子導体およびエミッタ外部導出端子導体に直接固着
され、コンデンサ接続のための配線が用いられないた
め、配線長によるインダクタンスが生じず、過渡的イン
ピーダンスの増大が防止される。Both electrodes of the bypass capacitor are directly fixed to the gate external lead terminal conductor and the emitter external lead terminal conductor of the MBT, and wiring for connecting the capacitor is not used, so inductance does not occur due to the wiring length and transient impedance increases. Is prevented.
第1図は本発明の一実施例を示し、図示しない基板上
に固着されたMBTのチップ1の近くにゲート外部導出端
子導体3とエミッタ外部導出端子導体4が絶縁間隙6を
介して平行配置されている。両端子導体はMBTの基板と
も絶縁されていることはもちろんである。MBTチップ1
のゲート電極11は端子導体3と、エミッタ電極12は端子
導体4とそれぞれワイヤ5により接続されている。コン
デンサ2は、両端の電極が端子導体3および端子導体4
にそれぞれ固着されている。これによりコンデンサ2は
MBTのゲート電極11とエミッタ電極12をバイパスする。
バイパスのための接続によるインダクタンスはワイヤ5
によって生ずるものに限定される。FIG. 1 shows an embodiment of the present invention, in which a gate external lead-out terminal conductor 3 and an emitter external lead-out terminal conductor 4 are arranged in parallel with each other near an MBT chip 1 fixed on a substrate (not shown) with an insulating gap 6 interposed therebetween. Has been done. Of course, both terminal conductors are also insulated from the MBT board. MBT chip 1
The gate electrode 11 is connected to the terminal conductor 3 and the emitter electrode 12 is connected to the terminal conductor 4 by wires 5, respectively. The electrodes of both ends of the capacitor 2 are the terminal conductor 3 and the terminal conductor 4.
Respectively. As a result, the capacitor 2
Bypasses the gate electrode 11 and the emitter electrode 12 of the MBT.
Inductance due to connection for bypass is wire 5
Are limited to those generated by.
第4図は別の実施例で、ゲート外部導出端子導体3と
エミッタ外部導出端子導体4とは二つの絶縁体7を介し
て上下に重ねて配置され、バイパスコンデンサ2は両絶
縁体7の中間の空間内に存在し、両面の電極が両端子導
体3,4に直接固着されている。この構造はコンデンサ2
が端子導体により保護されること、ならびに端子の占有
面積が第1図の場合に比して少なくなる利点がある。ま
た、コンデンサ2の固着は両端子導体3,4の絶縁体7を
介しての固定と同一組立工程でできる利点もある。更に
両端子導体3,4間に絶縁体7を介しているため、両端子
導体3,4間に容量が形成される。この両端子導体3,4間の
容量がゲート・エミッタ間バイパスコンデンサと並列接
続の形となり同様の機能を果たすこととなる。従って、
第1図の実施例に比してコンデンサ2を小型のものを用
いることができ、端子のみならずコンデンサの占有面積
をも少なくすることができる。FIG. 4 shows another embodiment, in which the gate external lead-out terminal conductor 3 and the emitter external lead-out terminal conductor 4 are vertically stacked with the two insulators 7 interposed therebetween, and the bypass capacitor 2 is located between the two insulators 7. The electrodes on both sides are directly fixed to both the terminal conductors 3 and 4. This structure is the capacitor 2
Is protected by the terminal conductor, and the area occupied by the terminal is reduced as compared with the case of FIG. Further, there is an advantage that the fixing of the capacitor 2 can be performed in the same assembly process as the fixing of the both terminal conductors 3 and 4 via the insulator 7. Further, since the insulator 7 is interposed between the two terminal conductors 3 and 4, a capacitance is formed between the two terminal conductors 3 and 4. The capacitance between the two terminal conductors 3 and 4 forms a parallel connection with the gate-emitter bypass capacitor and performs the same function. Therefore,
Compared with the embodiment shown in FIG. 1, a small capacitor 2 can be used, and not only the terminals but also the occupied area of the capacitor can be reduced.
本発明によれば、MBTの負荷側の事故発生時における
ピーク電流を抑制するためのゲート・エミッタ間バイパ
スコンデンサをゲートおよびエミッタ外部導出端子導体
に直接固着することにより接続のための配線が省略で
き、配線長によるインダクタンスが小さくなり、過渡イ
ンピーダンスが抑制できる。According to the present invention, the wiring for connection can be omitted by directly fixing the gate-emitter bypass capacitor for suppressing the peak current at the time of occurrence of an accident on the load side of the MBT to the gate and emitter external lead-out terminal conductors. In addition, the inductance due to the wiring length is reduced, and transient impedance can be suppressed.
第1図は本発明の一実施例の要部を示す斜視図、第2図
はバイパスコンデンサなしのMBTの回路図、第3図はバ
イパスコンデンサを挿入したMBTの回路図、第4図は本
発明の別の実施例の要部を示す斜視図である。 1:MOSゲート形バイポーラトランジスタ(チップ)、2:
バイパスコンデンサ、3:ゲート外部導出端子導体、4:エ
ミッタ外部導出端子導体、7:絶縁体。FIG. 1 is a perspective view showing an essential part of an embodiment of the present invention, FIG. 2 is a circuit diagram of an MBT without a bypass capacitor, FIG. 3 is a circuit diagram of an MBT with a bypass capacitor inserted, and FIG. It is a perspective view which shows the principal part of another Example of invention. 1: MOS gate type bipolar transistor (chip), 2:
Bypass capacitor, 3: Gate external lead terminal conductor, 4: Emitter external lead terminal conductor, 7: Insulator.
Claims (1)
のゲート・エミッタ間に接続されるバイパスコンデンサ
を備えたものにおいて、MOSゲート形バイポーラトラン
ジスタの半導体素体の一側に近接して該MOSゲート形バ
イポーラトランジスタのゲート電極にワイヤを介して接
続されるゲート外部導出端子導体とエミッタ電極にワイ
ヤを介して接続されるエミッタ外部導出端子導体とが互
いに絶縁して平行に配置され、バイパスコンデンサがゲ
ート外部導出端子導体とエミッタ外部導出端子導体との
間に固着されたことを特徴とするMOSゲート形バイポー
ラトランジスタ。1. A MOS gate bipolar transistor comprising a MOS gate bipolar transistor and a bypass capacitor connected between its gate and emitter, the MOS gate bipolar transistor being close to one side of a semiconductor body of the MOS gate bipolar transistor. The gate external lead-out terminal conductor connected to the gate electrode of the above through the wire and the emitter external lead-out terminal conductor connected to the emitter electrode through the wire are arranged in parallel and insulated from each other, and the bypass capacitor is connected to the gate external lead-out terminal. A MOS gate type bipolar transistor characterized in that it is fixed between a conductor and an external lead terminal conductor of the emitter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63280758A JP2536099B2 (en) | 1988-11-07 | 1988-11-07 | MOS gate type bipolar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63280758A JP2536099B2 (en) | 1988-11-07 | 1988-11-07 | MOS gate type bipolar transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02126663A JPH02126663A (en) | 1990-05-15 |
JP2536099B2 true JP2536099B2 (en) | 1996-09-18 |
Family
ID=17629544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63280758A Expired - Lifetime JP2536099B2 (en) | 1988-11-07 | 1988-11-07 | MOS gate type bipolar transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2536099B2 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6151846A (en) * | 1984-08-21 | 1986-03-14 | Toshiba Corp | Electronic circuit |
-
1988
- 1988-11-07 JP JP63280758A patent/JP2536099B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02126663A (en) | 1990-05-15 |
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