JPH1141909A - Semiconductor module and power conversion device - Google Patents
Semiconductor module and power conversion deviceInfo
- Publication number
- JPH1141909A JPH1141909A JP9187987A JP18798797A JPH1141909A JP H1141909 A JPH1141909 A JP H1141909A JP 9187987 A JP9187987 A JP 9187987A JP 18798797 A JP18798797 A JP 18798797A JP H1141909 A JPH1141909 A JP H1141909A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- igbt
- semiconductor module
- voltage
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の電力用半導
体素子が内部で並列接続されている半導体モジュール及
びこの半導体モジュールを含む電力変換装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module in which a plurality of power semiconductor devices are internally connected in parallel, and a power converter including the semiconductor module.
【０００２】[0002]
【従来の技術】大容量の電力用半導体モジュ−ルは、モ
ジュ−ル内に複数の電力用半導体素子が並列に接続され
ている。半導体素子の一例としてＩＧＢＴに関しては、
2000V500A High Power IGBT Module 、A.Tanaka et.a
l、ISPSD'95 日立などに記載が見られる。2. Description of the Related Art A large-capacity power semiconductor module has a plurality of power semiconductor elements connected in parallel in the module. As for an IGBT as an example of a semiconductor device,
2000V500A High Power IGBT Module, A.Tanaka et.a
l, ISPSD'95 Hitachi, etc. have descriptions.
【０００３】図７は、ＩＧＢＴモジュ−ルを用いた電力
変換装置である。モジュ−ル内でＩＧＢＴが４並列され
る例を示している。同図において、１は直流電圧源、２
はＩＧＢＴモジュ−ル、３は負荷、４はゲ−トドライブ
回路、５はゲ−ト抵抗、６Ａ〜６ＤはＩＧＢＴ、７はコ
レクタ端子、８はエミッタ端子、９はゲ−ト端子、１０
は信号用エミッタ端子である。FIG. 7 shows a power converter using an IGBT module. An example is shown in which four IGBTs are arranged in parallel in a module. In the figure, 1 is a DC voltage source, 2
Is an IGBT module, 3 is a load, 4 is a gate drive circuit, 5 is a gate resistor, 6A to 6D are IGBTs, 7 is a collector terminal, 8 is an emitter terminal, 9 is a gate terminal, 10 is
Is a signal emitter terminal.
【０００４】図示してはいないが、各ＩＧＢＴには、Ｇ
端子とＥ端子の間に、入力容量が存在する。それぞれの
ＩＧＢＴ６Ａ〜６Ｄは、それぞれのＧ端子とＥ端子の端
子間の電圧ＶGEにより、コレクタに流せる電流ＩC を増
減できる。このＩC −ＶGE特性は、ＩＧＢＴデ−タブッ
ク（たとえば、東芝ＩＧＢＴデ−タブック1996）などに
示されている。ここで、特定のＩC に対するＶGEをしき
い値と呼ぶこととする。 図７は以下のように作用す
る。Although not shown, each IGBT has a G
An input capacitance exists between the terminal and the E terminal. Each of the IGBTs 6A to 6D can increase or decrease the current IC that can flow through the collector by the voltage VGE between the G terminal and the E terminal. This IC-VGE characteristic is shown in an IGBT data book (for example, Toshiba IGBT data book 1996). Here, VGE for a specific IC is called a threshold. FIG. 7 operates as follows.
【０００５】ゲ−トドライブ回路４から−１５Ｖを出力
した状態では、ゲ−ト端子９と信号用エミッタ端子１０
の間に−１５Ｖが印加され、ＩＧＢＴがオフ状態とな
る。ＩＧＢＴをオフ状態からオンするときは、ゲ−トド
ライブ回路の出力を＋１５Ｖにする。このとき、ゲ−ト
抵抗に電流が流れ、図示しないＩＧＢＴ６Ａ〜６ＤのＧ
Ｅ端子間の入力容量を充電する。この結果、各ＩＧＢＴ
６Ａ〜６ＤのＧＥ端子間電圧が徐々に上昇する。そし
て、各ＩＧＢＴのＧＥ端子間電圧が、しきい値を超える
と、ＩＧＢＴがオンする。When -15 V is output from the gate drive circuit 4, the gate terminal 9 and the signal emitter terminal 10 are output.
-15 V is applied during this time, and the IGBT is turned off. When turning on the IGBT from the off state, the output of the gate drive circuit is set to + 15V. At this time, a current flows through the gate resistor, and the G of the IGBTs 6A to 6D (not shown)
The input capacitance between the E terminals is charged. As a result, each IGBT
The voltage between the GE terminals of 6A to 6D gradually increases. When the voltage between the GE terminals of each IGBT exceeds the threshold value, the IGBT is turned on.
【０００６】ＩＧＢＴをオン状態からオフするときは、
ゲ−トドライブ回路の出力を−１５Ｖにする。このと
き、同様にゲ−ト抵抗に電流が流れ、ＩＧＢＴ６Ａ〜６
ＤのＧＥ端子間の電圧が徐々に下降し、この電圧がしき
い値以下になるとＩＧＢＴがオフする。When the IGBT is turned off from the on state,
The output of the gate drive circuit is set to -15V. At this time, similarly, a current flows through the gate resistance, and the IGBTs 6A to 6A
The voltage between the GE terminals of D gradually decreases, and when this voltage falls below the threshold, the IGBT turns off.
【０００７】図８は、複数のＩＧＢＴチップを内蔵す
る、圧接形ＩＧＢＴモジュ−ルの構造を示すものであ
る。圧接形ＩＧＢＴについては、例えば、2.5kV/1kA Po
wer Pack( 平型逆導通ＩＧＢＴ) 、吉川ほか、平成８年
電気学会全国大会７５０によって紹介されている。同図
において、１０１はエミッタポスト、１０２はコレクタ
ポスト、１０３はＩＧＢＴチップ、１０４はＭｏ基板、
１０５はコンタクト端子、１０６は位置決めガイドであ
る。それぞれのＩＧＢＴチップ１０３には、ゲ−ト端子
があるが、図では省略している。この場合、エミッタポ
スト１０１がエミッタ端子と信号用エミッタ端子を兼
ね、コレクタポスト１０２がコレクタ端子に置き換える
と、作用は図７のＩＧＢＴモジュ−ル２と同じである。FIG. 8 shows the structure of a press-contact type IGBT module having a plurality of IGBT chips. For a press-contact IGBT, for example, 2.5 kV / 1 kA Po
wer Pack (Flat-type reverse conducting IGBT), Yoshikawa et al., are introduced in the 1996 IEEJ National Conference 750. In the figure, 101 is an emitter post, 102 is a collector post, 103 is an IGBT chip, 104 is a Mo substrate,
105 is a contact terminal, and 106 is a positioning guide. Although each IGBT chip 103 has a gate terminal, it is omitted in the figure. In this case, when the emitter post 101 serves as an emitter terminal and a signal emitter terminal and the collector post 102 is replaced with a collector terminal, the operation is the same as that of the IGBT module 2 in FIG.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、従来の
半導体モジュ−ル及び電力変換装置では、並列に接続さ
れた半導体素子のしきい値にばらつきがあると、各半導
体素子のコレクタ電流にばらつきが生じるという問題点
が生じる。たとえば、図７の構成で、ある半導体素子素
子のしきい値が他に比べて低い場合、タ−ンオン時のＧ
Ｅ間電圧が上昇中に、この半導体素子が先にタ−ンオン
してしまい、全電流がこの半導体素子に流れることとな
る。さらに、タ−ンオフにおいても、ＧＥ間電圧が下降
中に、この半導体素子以外の素子が先にオフしてしまう
という問題が生じる。このように、しきい値にばらつき
があると、しきい値の低い半導体素子の負担が大きくな
り、信頼性が低下する。However, in the conventional semiconductor module and power converter, if the threshold values of the semiconductor elements connected in parallel vary, the collector current of each semiconductor element varies. The problem arises. For example, in the configuration of FIG. 7, when the threshold value of a certain semiconductor device is lower than that of another semiconductor device, the G at the time of turn-on is reduced.
While the voltage between E rises, this semiconductor element turns on first, and all the current flows to this semiconductor element. Further, also in the turn-off, there is a problem that elements other than the semiconductor element are turned off first while the voltage between GEs is falling. As described above, when the threshold value varies, the load on the semiconductor element having a low threshold value increases, and the reliability decreases.
【０００９】そこで、本発明は、上記問題点を鑑み、し
きい値にばらつきのある半導体素子を並列接続しても、
過渡時の電流バランスを改善できる半導体モジュール及
び電力変換装置を提供することを目的とする。Therefore, the present invention has been made in view of the above problems, and even if semiconductor elements having a variation in threshold value are connected in parallel,
It is an object of the present invention to provide a semiconductor module and a power converter that can improve a current balance during a transition.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、請求項１記載の発明は、並列接続される複数の半導
体素子と、前記半導体素子のエミッタ側に直列接続され
るインダクタンス手段と、前記半導体素子及び前記イン
ダクタンス手段とを収納する収納手段とを具備すること
を特徴とすし、並列に接続された半導体素子の特定の素
子に電流が多く流れたとき、インダクタンス導体の電圧
降下によって、半導体素子のゲ−トとエミッタ間の電圧
が下がるので、電流がバランスが均一化される。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a plurality of semiconductor devices connected in parallel; an inductance device connected in series to an emitter side of the semiconductor device; A semiconductor device and storage means for storing the inductance means, wherein when a large amount of current flows in a specific element of the semiconductor elements connected in parallel, the voltage drop of the inductance conductor causes Since the voltage between the gate and the emitter is lowered, the current is balanced.
【００１１】請求項２記載の発明は、並列接続される複
数の半導体素子と、前記半導体素子のエミッタ側に直列
接続される第１のインダクタンス手段と、前記第１のイ
ンダクタンス手段のうちいずれか複数の第１のインダク
タンス手段の並列接続点に直列接続される第２のインダ
クタンス手段と、前記半導体素子及び前記第１及び第２
のインダクタンス手段とを収納する収納手段とを具備す
ることを特徴とする。According to a second aspect of the present invention, there is provided a semiconductor device comprising: a plurality of semiconductor elements connected in parallel; a first inductance means connected in series to an emitter of the semiconductor element; and a plurality of the first inductance means. Second inductance means connected in series to the parallel connection point of the first inductance means, and the semiconductor element and the first and second inductance means.
And storage means for storing the inductance means.
【００１２】請求項３記載の発明は、前記半導体素子の
ゲ−ト−エミッタ間に、過電圧防止素子を接続したこと
を特徴とし、過電圧防止素子の作用により、半導体素子
のゲ−ト破壊を防ぐことができる。According to a third aspect of the present invention, an overvoltage protection element is connected between the gate and the emitter of the semiconductor element, and the gate of the semiconductor element is prevented from being destroyed by the action of the overvoltage protection element. be able to.
【００１３】請求項４記載の発明は、複数の電力用半導
体素子が並列に接続され、共通の電極体で圧接する圧接
形半導体モジュ−ルにおいて、前記半導体素子と前記電
極体との間に、インダクタンス手段を挟み、半導体素子
と同時に圧接することを特徴とする。According to a fourth aspect of the present invention, there is provided a press-contact type semiconductor module in which a plurality of power semiconductor elements are connected in parallel and press-contacted by a common electrode body. It is characterized in that it presses simultaneously with the semiconductor element with the inductance means interposed therebetween.
【００１４】請求項５記載の発明は、請求項１乃至４記
載のいずれかの半導体モジュールと、前記半導体モジュ
ールに電力を供給する電源と、前記半導体モジュ−ルに
おける半導体素子にゲート信号を供給するゲート供給回
路とを具備することを特徴とする。According to a fifth aspect of the present invention, there is provided the semiconductor module according to any one of the first to fourth aspects, a power supply for supplying power to the semiconductor module, and a gate signal for supplying a semiconductor element in the semiconductor module. And a gate supply circuit.
【００１５】このように、並列に接続された半導体素子
のエミッタ端子が、インダクタンス導体に発生する電圧
降下により変動することを利用して、電流の大きな素子
のゲ−トとエミッタ間の電圧を低く、電流の小さな素子
のゲ−トとエミッタ間の電圧を高くすることができるの
で、各半導体素子の電流のバランスを得ることができ
る。By utilizing the fact that the emitter terminals of the semiconductor elements connected in parallel fluctuate due to the voltage drop generated in the inductance conductor, the voltage between the gate and the emitter of the element having a large current is reduced. Since the voltage between the gate and the emitter of the element having a small current can be increased, the current of each semiconductor element can be balanced.
【００１６】[0016]
【発明の実施の形態】本発明の第１の実施の形態につい
て図１、図２を用いて説明する。図１において、１１Ａ
〜１１Ｄはリアクトル、１２は共通エミッタ端子であ
り、そのほかの要素は、図７の同一番号に対応する。図
１は、半導体モジュ−ルの構成を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, 11A
11D is a reactor, 12 is a common emitter terminal, and the other elements correspond to the same numbers in FIG. FIG. 1 shows the configuration of the semiconductor module.
【００１７】例えば、ＩＧＢＴ６Ａのしきい値が、他の
ＩＧＢＴに比べて低い場合を考える。ゲ−トドライブ回
路の出力を−１５Ｖから＋１５Ｖにすると、ゲ−ト端子
９の電位が上昇する。ゲ−ト端子電位が、ＩＧＢＴ６Ａ
のしきい値を超えると、ＩＧＢＴ６Ａに電流Ｉ6Aが流れ
る。このとき、リアクトル１１Ａに、以下の電圧ＶＬ
（＝Ｌ＊微分（Ｉ6A））が発生する。ただし、Ｌはリア
クトル１１Ａのインダクタンス値である。For example, consider a case where the threshold value of the IGBT 6A is lower than other IGBTs. When the output of the gate drive circuit is changed from -15V to + 15V, the potential of the gate terminal 9 rises. Gate terminal potential is IGBT6A
Exceeds the threshold value, the current I6A flows through the IGBT 6A. At this time, the following voltage VL is applied to reactor 11A.
(= L * differential (I6A)) occurs. Here, L is the inductance value of the reactor 11A.
【００１８】このＶＬは、ゲ−ト端子−エミッタ端子間
電圧に対して、ＩＧＢＴ６ＡのＧＥ間電圧を下げる方向
にかかる。そのため、しきい値の低いＩＧＢＴ６Ａの
み、ＧＥ間電圧が低くなり、タ−ンオンを遅らせ、電流
のアンバランスが大きくなるのを防ぐ。このＶＬは、Ｉ
ＧＢＴ６Ａに電流が集中するほど大きな値になる。This VL is applied in a direction to lower the voltage between GE of the IGBT 6A with respect to the voltage between the gate terminal and the emitter terminal. Therefore, only the IGBT 6A having a low threshold value has a low GE voltage, delays turn-on, and prevents an increase in current imbalance. This VL is I
The value increases as the current concentrates on the GBT 6A.
【００１９】タ−ンオフでは、逆にしきい値の高いＩＧ
ＢＴ６Ｂ〜６Ｃが先にオフ動作に入ろうとするが、この
ときに、ＩＧＢＴ６Ａに電流が集中すると、タ−ンオン
時と同様に、ＩＧＢＴ６ＡのＧ−Ｅ間電圧がほかのＩＧ
ＢＴより下がるため、電流が均一化され、同時にオフす
るようになる。In the turn-off, on the contrary, the IG having a high threshold
When the currents concentrate on the IGBT 6A at this time, when the BTs 6B to 6C attempt to turn off first, the voltage between the GE of the IGBT 6A and the IGBT 6A becomes lower than the other IGs.
Since the current is lower than the BT, the current is uniformed and turned off at the same time.
【００２０】つまり、それぞれのＩＧＢＴのＥ電位が、
リアクトルにかかる電流変化率に応じて変動することに
より、ＩＧＢＴのＧＥ間電圧に差が生じる。これによ
り、タ−ンオン時・タ−ンオフ時の各ＩＧＢＴ間の電流
のバランスが良くなる。That is, the E potential of each IGBT becomes
When the IGBT fluctuates according to the current change rate applied to the reactor, a difference occurs between the GE voltages of the IGBTs. As a result, the current balance between the IGBTs at the time of turn-on / turn-off is improved.
【００２１】このように、先にタ−ンオンまたはタ−ン
オフ動作に移行したＩＧＢＴのＧＥ間電圧を制御するこ
とになり、過渡時の電流のバランスが良くすることが可
能となる。なお、リアクトル１１Ａ〜１１Ｄは数１０ｎ
Ｈ程度で十分な効果が得られるため、数ｃｍの長さの導
体でリアクトルを構成することもできる。As described above, the voltage between the GEs of the IGBT which has been shifted to the turn-on or turn-off operation is controlled, and the current balance during the transition can be improved. The reactors 11A to 11D are several tens of n
Since a sufficient effect can be obtained with about H, the reactor can be constituted by a conductor having a length of several cm.
【００２２】また、それぞれのＩＧＢＴのＧ端子に直列
に抵抗を入れても、同様の作用効果を得ることができ
る。さらに、図２のように、２ｉｎ１タイプのモジュ−
ルに適用することも可能である。Similar effects can be obtained even if a resistor is inserted in series with the G terminal of each IGBT. Further, as shown in FIG.
It is also possible to apply to files.
【００２３】本発明の第２の実施の形態について図３を
用いて説明する。本実施の形態は、第１の実施の形態に
比し、２つのＩＧＢＴをまとめた点に特徴を有する。リ
アクトル１１Ｅが、リアクトル１１Ａ、１１Ｂのバラン
スを取り、リアクトル１１Ｆが、リアクトル１１Ｃ、１
１Ｄのバランスをとっている。A second embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in that two IGBTs are combined, as compared with the first embodiment. Reactor 11E balances reactors 11A and 11B, and reactor 11F adjusts reactors 11C and 1B.
1D balance.
【００２４】このように、いくつかのＩＧＢＴをまとめ
ることにより、並列数が多くなっても複雑にならずに、
電流バランスを改善することができる。本発明の第３の
実施の形態について図４を用いて説明する。As described above, by combining several IGBTs, even if the number of parallel IGBTs increases, the IGBTs do not become complicated,
The current balance can be improved. A third embodiment of the present invention will be described with reference to FIG.
【００２５】本実施の形態は、構成要素に、ツェナダイ
オ−ド１３を付加した点に特徴を有する。ツェナダイオ
−ドを設けた結果、過電圧がＧＥ間にかからなくなる。
このように、ＩＧＢＴのＧＥ間にツェナダイオ−ドを入
れることにより、ＩＧＢＴの入力容量とリアクトルの共
振などが原因で発生する過電圧を防止することができ
る。This embodiment is characterized in that a zener diode 13 is added to the components. As a result of providing the Zener diode, the overvoltage is not applied between the GEs.
As described above, by inserting a Zener diode between the GEs of the IGBT, it is possible to prevent an overvoltage generated due to the resonance of the input capacitance of the IGBT and the reactor, and the like.
【００２６】本発明の第４の実施の形態について図５を
用いて説明する。本実施の形態は、圧接形モジュ−ルに
適用した場合を示すものである。図５において、１０７
は誘導体ブロックであり、その外の構成要素は図８と同
一番号に対応する。なお、ＩＧＢＴ１０３は上面がエミ
ッタである。回路構成は図１と同じになる。誘電体ブロ
ックは、たとえば、導電体と絶縁物を積層させることに
より作成する。このように、誘電体ブロックを挿入する
ことにより、電流のばらつきが発生したときに第１の実
施の形態と同様に各ＩＧＢＴのエミッタ電位を変動さ
せ、ＧＥ間電圧に差を生じさせ、過渡時の電流バランス
を良好にする。A fourth embodiment of the present invention will be described with reference to FIG. This embodiment shows a case where the present invention is applied to a press-contact type module. In FIG.
Is a derivative block, and the other constituent elements correspond to the same numbers as in FIG. The upper surface of the IGBT 103 is an emitter. The circuit configuration is the same as in FIG. The dielectric block is formed, for example, by laminating a conductor and an insulator. In this way, by inserting the dielectric block, the emitter potential of each IGBT fluctuates in the same manner as in the first embodiment when a current variation occurs, causing a difference in the voltage between GEs. The current balance.
【００２７】本発明の第５の実施の形態について図６を
用いて説明する。本実施の形態は、第１乃至第４のいず
れかの実施の形態に、直流電圧源１やＩＧＢＴ６にゲ−
ト信号を供給するゲートドライブ回路４を付加し、電力
変換装置として構成したものである。このように、第１
乃至第４のいずれかの実施の形態に示す半導体モジュー
ルを、電力変換装置として構成したことにより、ＩＧＢ
Ｔの破損が生じにくくなり、電力変換装置の信頼性が向
上する。A fifth embodiment of the present invention will be described with reference to FIG. This embodiment is different from any of the first to fourth embodiments in that the DC voltage source 1 and the IGBT 6 have a gate.
A gate drive circuit 4 for supplying a power signal is added to configure a power conversion device. Thus, the first
The semiconductor module shown in any one of the fourth to fourth embodiments is configured as a power converter, so that the IGB
T is hardly damaged, and the reliability of the power converter is improved.
【００２８】[0028]
【発明の効果】以上述べたように本発明によれば、モジ
ュ−ル内で並列に接続されたＩＧＢＴのエミッタ電位が
変動させることにより、ＩＧＢＴ間の電流にアンバラン
スが発生したときに、それぞれのＩＧＢＴのＧＥ間電圧
がバランスする方向に作用し、電流のアンバランスを押
さえることができる。As described above, according to the present invention, when the emitter potential of the IGBTs connected in parallel in the module fluctuates, when the current between the IGBTs becomes unbalanced, Acts in a direction in which the GE voltage of the IGBT is balanced, thereby suppressing imbalance in current.
【００２９】さらに、この半導体モジュールを電力変換
装置として構成すれば、特定のＩＧＢＴに電気的なスト
レスが生じなくなるので、電力変換装置としての信頼性
が向上する。Further, when this semiconductor module is configured as a power converter, electric stress is not generated in a specific IGBT, so that the reliability of the power converter is improved.
【図１】本発明の第１の実施の形態における半導体モジ
ュ−ルの回路図。FIG. 1 is a circuit diagram of a semiconductor module according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態における半導体モジ
ュ−ルの回路図。FIG. 2 is a circuit diagram of the semiconductor module according to the first embodiment of the present invention.
【図３】本発明の第２の実施の形態における半導体モジ
ュ−ルの回路図。FIG. 3 is a circuit diagram of a semiconductor module according to a second embodiment of the present invention.
【図４】本発明の第３の実施の形態における半導体モジ
ュ−ルの回路図。FIG. 4 is a circuit diagram of a semiconductor module according to a third embodiment of the present invention.
【図５】本発明の第４の実施の形態における圧接形半導
体モジュ−ルの構成図。FIG. 5 is a configuration diagram of a press-contact type semiconductor module according to a fourth embodiment of the present invention.
【図６】本発明の第５の実施の形態における電力変換装
置の回路図。FIG. 6 is a circuit diagram of a power conversion device according to a fifth embodiment of the present invention.
【図７】従来の電力変換装置の回路図。FIG. 7 is a circuit diagram of a conventional power converter.
【図８】従来の圧接形半導体モジュ−ルの構成図。FIG. 8 is a configuration diagram of a conventional pressure contact type semiconductor module.
１ 直流電圧源 ２ ＩＧＢＴモジュ−ル ３ 負荷 ４ ゲ−トドライブ回路 ５ ゲ−ト抵抗 ６ ＩＧＢＴ ７ コレクタ端子 ８ エミッタ端子 ９ ゲ−ト端子 １０ 信号用エミッタ端子 １１ リアクトル １２、１４ 共通エミッタ端子 １３ ツェナダイオ−ド １０１ エミッタポスト １０２ コレクタポスト 103 ＩＧＢＴチップ １０４ Ｍｏ基板 １０５ コンタクト端子 １０６ 位置決めガイド １０７ 誘導対ブロック DESCRIPTION OF SYMBOLS 1 DC voltage source 2 IGBT module 3 Load 4 Gate drive circuit 5 Gate resistor 6 IGBT 7 Collector terminal 8 Emitter terminal 9 Gate terminal 10 Signal emitter terminal 11 Reactor 12, 14 Common emitter terminal 13 Zener diode −dod 101 emitter post 102 collector post 103 IGBT chip 104 Mo substrate 105 contact terminal 106 positioning guide 107 induction pair block
Claims (5)
タンス手段と、 前記半導体素子及び前記インダクタンス手段とを収納す
る収納手段と、 を具備することを特徴とする半導体モジュール。1. A semiconductor device comprising: a plurality of semiconductor elements connected in parallel; an inductance means connected in series on an emitter side of the semiconductor element; and a storage means for storing the semiconductor element and the inductance means. Characteristic semiconductor module.
ンダクタンス手段と、 前記第１のインダクタンス手段のうちいずれか複数の第
１のインダクタンス手段の並列接続点に直列接続される
第２のインダクタンス手段と、 前記半導体素子及び前記第１及び第２のインダクタンス
手段とを収納する収納手段と、 を具備することを特徴とする半導体モジュール。2. A plurality of semiconductor elements connected in parallel; a first inductance means connected in series to an emitter side of the semiconductor element; and a plurality of first inductance means of the first inductance means. A semiconductor module comprising: a second inductance unit connected in series to the parallel connection point; and a storage unit configured to store the semiconductor element and the first and second inductance units.
過電圧防止素子を接続したことを特徴とする請求項１ま
たは請求項２記載の半導体モジュ−ル。3. The semiconductor device according to claim 1, wherein:
3. The semiconductor module according to claim 1, wherein an overvoltage protection element is connected.
れ、共通の電極体で圧接する圧接形半導体モジュ−ルに
おいて、 前記半導体素子と前記電極体との間に、インダクタンス
手段を挟み、半導体素子と同時に圧接することを特徴と
する圧接形半導体モジュ−ル。4. A pressure-contact type semiconductor module in which a plurality of power semiconductor elements are connected in parallel and press-contacted by a common electrode body, wherein an inductance means is sandwiched between said semiconductor element and said electrode body. A pressure-contact type semiconductor module characterized by being pressed simultaneously with an element.
ジュールと、 前記半導体モジュールに電力を供給する電源と、 前記半導体モジュ−ルにおける半導体素子にゲート信号
を供給するゲート供給回路と、 を具備することを特徴とする電力変換装置。5. The semiconductor module according to claim 1, further comprising: a power supply for supplying power to said semiconductor module; and a gate supply circuit for supplying a gate signal to a semiconductor element in said semiconductor module. A power converter, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18798797A JP3421544B2 (en) | 1997-07-14 | 1997-07-14 | Semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18798797A JP3421544B2 (en) | 1997-07-14 | 1997-07-14 | Semiconductor module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1141909A true JPH1141909A (en) | 1999-02-12 |
| JP3421544B2 JP3421544B2 (en) | 2003-06-30 |
Family
ID=16215644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18798797A Expired - Fee Related JP3421544B2 (en) | 1997-07-14 | 1997-07-14 | Semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3421544B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023769A (en) * | 2001-07-06 | 2003-01-24 | Sansha Electric Mfg Co Ltd | Semiconductor module for power |
| JP2010514397A (en) * | 2006-12-21 | 2010-04-30 | シーメンス アクチエンゲゼルシヤフト | Converter having short-circuit current limiting unit |
| JP2011211784A (en) * | 2010-03-29 | 2011-10-20 | Kitashiba Electric Co Ltd | Power conversion device |
| CN103633820A (en) * | 2013-11-28 | 2014-03-12 | 电子科技大学 | IGBT (insulated gate bipolar transistor) parallel current sharing circuit |
| CN106059269A (en) * | 2016-06-22 | 2016-10-26 | 杭州飞仕得科技有限公司 | Drive circuit applicable to multi-parallel IGBTs |
| JP2017163016A (en) * | 2016-03-10 | 2017-09-14 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
| KR20180002736A (en) | 2015-05-22 | 2018-01-08 | 닛산 지도우샤 가부시키가이샤 | Power conversion device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021125946A (en) | 2020-02-04 | 2021-08-30 | オムロン株式会社 | Semiconductor circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4920265Y1 (en) * | 1969-02-05 | 1974-05-30 | ||
| JPS5322018U (en) * | 1976-08-04 | 1978-02-24 | ||
| JPH04229079A (en) * | 1990-12-27 | 1992-08-18 | Hitachi Ltd | Parallel connecting method for semiconductor, switch circuit and inverter |
| JPH0884483A (en) * | 1994-09-13 | 1996-03-26 | Fuji Electric Co Ltd | Inverter unit and inverter |
| JPH08330338A (en) * | 1995-05-31 | 1996-12-13 | Toshiba Corp | Pressure welded type semiconductor device |
-
1997
- 1997-07-14 JP JP18798797A patent/JP3421544B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4920265Y1 (en) * | 1969-02-05 | 1974-05-30 | ||
| JPS5322018U (en) * | 1976-08-04 | 1978-02-24 | ||
| JPH04229079A (en) * | 1990-12-27 | 1992-08-18 | Hitachi Ltd | Parallel connecting method for semiconductor, switch circuit and inverter |
| JPH0884483A (en) * | 1994-09-13 | 1996-03-26 | Fuji Electric Co Ltd | Inverter unit and inverter |
| JPH08330338A (en) * | 1995-05-31 | 1996-12-13 | Toshiba Corp | Pressure welded type semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023769A (en) * | 2001-07-06 | 2003-01-24 | Sansha Electric Mfg Co Ltd | Semiconductor module for power |
| JP2010514397A (en) * | 2006-12-21 | 2010-04-30 | シーメンス アクチエンゲゼルシヤフト | Converter having short-circuit current limiting unit |
| US8462530B2 (en) | 2006-12-21 | 2013-06-11 | Siemens Aktiengesellschaft | Converter with short-circuit current limiting |
| JP2011211784A (en) * | 2010-03-29 | 2011-10-20 | Kitashiba Electric Co Ltd | Power conversion device |
| CN103633820A (en) * | 2013-11-28 | 2014-03-12 | 电子科技大学 | IGBT (insulated gate bipolar transistor) parallel current sharing circuit |
| KR20180002736A (en) | 2015-05-22 | 2018-01-08 | 닛산 지도우샤 가부시키가이샤 | Power conversion device |
| US10230294B2 (en) | 2015-05-22 | 2019-03-12 | Nissan Motor Co., Ltd. | Power conversion device with gate drive circuit |
| JP2017163016A (en) * | 2016-03-10 | 2017-09-14 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN106059269A (en) * | 2016-06-22 | 2016-10-26 | 杭州飞仕得科技有限公司 | Drive circuit applicable to multi-parallel IGBTs |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3421544B2 (en) | 2003-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10277112B2 (en) | Physical topology for a power converter | |
| CN103051312B (en) | Low impedance gate control method and equipment | |
| US20150357935A1 (en) | Tnpc inverter device and method for detecting short-circuit thereof | |
| JPH10144863A (en) | Power module | |
| KR100337035B1 (en) | Passive auxiliary circuit for series connection of IGBTs | |
| CN102195502A (en) | Semiconductor device | |
| CN106972849A (en) | The gate driving circuit of thyristor | |
| CN107317461A (en) | Power inverter | |
| JP7438021B2 (en) | semiconductor equipment | |
| JPH1141909A (en) | Semiconductor module and power conversion device | |
| JP2002153079A (en) | Semiconductor device | |
| US6727516B2 (en) | Semiconductor power conversion apparatus | |
| EP0455322B1 (en) | Semiconductor device | |
| KR940008343B1 (en) | Module-type semiconductor device high power capacity | |
| US6445068B1 (en) | Semiconductor module | |
| JPS61227661A (en) | Parallel device of gate turn-off thyristors | |
| CN101946412B (en) | Method for limiting an un-mirrored current and circuit therefor | |
| JP3512426B2 (en) | Power conversion device using MOS gate type semiconductor element | |
| US20050006750A1 (en) | Integrated semiconductor power device for multiple battery systems | |
| JP3277524B2 (en) | Semiconductor switch circuit and inverter device | |
| JP2005175054A (en) | Semiconductor device and method for manufacturing the same | |
| JP2004311901A (en) | Semiconductor device | |
| JP7301243B2 (en) | Gate drive circuit and power converter | |
| US11387174B2 (en) | Semiconductor device | |
| JP2000091897A (en) | Semiconductor switch for power, semiconductor switch device for power and power converting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080418 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090418 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100418 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100418 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110418 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130418 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |