JPS62150871A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62150871A JPS62150871A JP60290611A JP29061185A JPS62150871A JP S62150871 A JPS62150871 A JP S62150871A JP 60290611 A JP60290611 A JP 60290611A JP 29061185 A JP29061185 A JP 29061185A JP S62150871 A JPS62150871 A JP S62150871A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- gto
- parallel
- chips
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は自己消弧機能を有する高速スイッチング素子の
チップ直接並列接続に係り、特に、ＧＴＯサイリスタ、
パワートランジスタ、パワーＭＯ５ＦＥＴ、ＳＩサイク
スタ等の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a chip direct parallel connection of high-speed switching elements having a self-extinguishing function, and in particular to a GTO thyristor,
The present invention relates to semiconductor devices such as power transistors, power MO5FETs, and SI CYCSTARS.
ｌパッケージ内チップ直接並列接続において、直接並列
接続される主回路素子チップ数が４個の場合の従来例に
ついて、内部配線、主回路素子チップ、外部引き出シリ
ードの配置関係を第５図に示す。又その等価回路を第６
図に示す。主回路素子チップは自己消弧機能を有する素
子でこの例ではＧＴＯサイリスタで示す。Figure 5 shows the arrangement of internal wiring, main circuit element chips, and external lead series in a conventional example in which the number of main circuit element chips directly connected in parallel is 4 in direct parallel connection of chips within a package. . Also, the equivalent circuit is shown in the sixth
As shown in the figure. The main circuit element chip is an element having a self-extinguishing function, and is shown as a GTO thyristor in this example.
この従来例においては、外部端子から各々のＧＴＯチッ
プに到るまでの配線長が異なるため、第６図の等価回路
におけるＧＴＯチップを含む閉回路ループ内の回路要素
が、各ＧＴＯチップによって異なっている。各素子が並
列動作を行なう場合、上述した各回路要素の非等価性が
並列動作時の電流アンバランス発生要因となる。回路要
素としては抵抗成分でμΩオーダー、リアクタンス成分
でｎＨオーダーであるが、このレベルの回路要素子バラ
ツキで、理想的に電流バランスした時の電流値に対し、
０〜２０％のアンバランスが発生することを実験にて確
認している。In this conventional example, since the wiring length from the external terminal to each GTO chip is different, the circuit elements in the closed circuit loop including the GTO chip in the equivalent circuit of Fig. 6 are different for each GTO chip. There is. When each element operates in parallel, the above-mentioned non-equivalence of each circuit element becomes a cause of current imbalance during parallel operation. As a circuit element, the resistance component is on the μΩ order, and the reactance component is on the nH order, but with this level of circuit element variation, the current value when ideally balanced,
It has been confirmed through experiments that an imbalance of 0 to 20% occurs.
上述した様に、従来の１パツゲ内チップ直接並列接続構
成においては、ＧＴＯチップを含むパッケージ内配線に
対構性がない。このため、パッケージ内開回路の回路要
素にバラツキが発生し、この回路要素のバラツキが原因
で発生する電流アンバランスが並列動作の効率を低下さ
せるという欠点がある。As described above, in the conventional direct parallel connection configuration of chips within one package, there is no symmetry in the wiring within the package including the GTO chip. Therefore, there is a drawback that variations occur in the circuit elements of the open circuit within the package, and current imbalance caused by the variations in the circuit elements reduces the efficiency of parallel operation.
高速スイッチング素子の直接並列接続を実施した従来装
置には、特願昭５７−１０６８７２号、特願昭５７−１
１０３３９号等があるが、制御回路を含む直接並列接続
全体の回路要素のバラツキを抑える事については充分な
配慮がなされていなかった。Conventional devices that implement direct parallel connection of high-speed switching elements include Japanese Patent Application No. 57-106872 and Japanese Patent Application No. 57-1.
No. 10339, etc., but sufficient consideration was not given to suppressing variations in circuit elements of the entire direct parallel connection including the control circuit.
このため、並列動作時の電流アンバランスによる効率低
下は、１パツケ一ジ内チツプ直接並列接続構造による大
電流化において大きな問題点となっている。For this reason, the reduction in efficiency due to current imbalance during parallel operation is a major problem when increasing current by using a structure in which chips are directly connected in parallel within one package.
本発明の目的は、自己消弧機能を有する高速スイッチン
グ素子の大電流化を可能とする。An object of the present invention is to enable a high-speed switching element having a self-extinguishing function to operate at a large current.
安価で、高性能の大電流高速スイッチングモジュールの
半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device for a high-current, high-speed switching module that is inexpensive and has high performance.
本発明は、自己消弧機能を有する半導体素子のシリコン
チップが複数個電気的に並列接続された状態で搭載され
るパッケージ型モジュールにおいて、電気的に並列接続
される各々の前記シリコンチップがそれぞれ同心円上に
幾何学的対称に配置されており、電気的に並列接続され
た前記シリコンチップの同種の電極を集中接続した内部
電極と。The present invention provides a packaged module in which a plurality of silicon chips of semiconductor elements having a self-arc extinguishing function are mounted in a state in which they are electrically connected in parallel, in which each of the silicon chips electrically connected in parallel is arranged in a concentric circle. and internal electrodes arranged geometrically symmetrically on the top, in which similar electrodes of the silicon chip electrically connected in parallel are collectively connected.
パッケージ外部での外部接続用端子とを結ぶ外部引出し
リードが、同心円の中心線近傍に配置され。External lead leads that connect to external connection terminals outside the package are placed near the center line of the concentric circles.
前記シリコンチップの有する電極部の数だけある前記外
部引出しリードが、同軸ケーブル上に集中配置されてな
ることを特徴とする。The present invention is characterized in that the number of external lead leads equal to the number of electrode portions of the silicon chip are centrally arranged on a coaxial cable.
そのためには、ｌパッケージ内チップ直接並列接続にお
いては。For this purpose, in the direct parallel connection of the chips within the l package.
■ 各々のＧＴＯを含む内部配線が各外部電極端子（Ａ
、に、Ｇ、ＫＧ）に対して幾可学的に対称配置となって
いること。■ Internal wiring including each GTO connects to each external electrode terminal (A
, G, KG).
■ 各々のＧＴＯのオン電圧特性をそろえることが必要
となる。■ It is necessary to match the on-voltage characteristics of each GTO.
上記■が、従来例で述べた電流アンバランスを防止する
対策となる。実際の完全対称配置としては、各々のＧＴ
Ｏの同心円配置が好適である。The above item (2) is a measure to prevent the current imbalance described in the conventional example. In an actual completely symmetrical arrangement, each GT
A concentric arrangement of O is preferred.
各々のＧＴＯを同心円配置した場合のＧＴＯの位置と外
部引出しリードとの関係を、並列接続されるＧＴＯの数
が４個、６個、８個の場合について第７図に示す。FIG. 7 shows the relationship between the position of each GTO and the external lead-out lead when the GTOs are arranged in a concentric circle when the number of GTOs connected in parallel is 4, 6, and 8.
本発明は上述した考え方に沿って、１パツケージ内の主
回路素子（上述の場合はＧＴＯ）チップの直接並列接続
で、主回路素子チップを同心円に配置し、その中心線上
もしくはその近傍上にチップ電極と外部端子とを接続す
る外部引出しリードを同軸ケーブル状に集中配置するパ
ッケージ構造に関するものである。In line with the above-mentioned idea, the present invention is a direct parallel connection of main circuit element (GTO in the above case) chips in one package, in which the main circuit element chips are arranged in concentric circles, and the chips are placed on or near the center line of the main circuit element chips. This invention relates to a package structure in which external leads connecting electrodes and external terminals are centrally arranged in the form of a coaxial cable.
以下本発明の一実施例を、主回路素子チップをＧＴＯと
し、１パツケ一ジ内８並列接続の場合を例にとり構造お
よび組立プロセスについて説明する。第１図に上述の場
合のチップ平面配置例を示す。ヒートシンク（１）上に
ろう付された絶縁板（４）があり絶縁板（４）の上面は
第３図の如く斜線部に金属メタライズが施されており、
ＧＴＯチップ（２）、ダイオードチップ（３）がアノー
ド電極板上（８）へろう付されている。又円筒状のカソ
ードリード（６）のカソード電極部（６′）が、該絶縁
板（４）のカソード電極上（１６）へ、円筒状のゲート
リード（５）のゲート電極部（５′）が、該絶縁板（４
）のゲート電極部（１５）へ、円柱状のアノードリード
（７）が該絶縁板上のアノード電極（１７）上へそれぞ
れろう付されている。ＧＴＯチップ（２）上のカソード
電極と該絶縁板（４）上にろう付されたカソード電極（
６′）との間、ＧＴＯ（２）チップ（２）上のゲート電
極（５）と該絶縁板（４）にろう付されたゲート電極と
の間、ダイオードチップの表面電極と該カソード電極（
５°）との間はそれぞれＡＱワイヤ（９）で配線されて
いる。第７図は見易くするためにＡＱ線を各々１本で表
現しているが、ＡＱ線（９）の本数は、該ＧＴＯチップ
（２）の電流容量にて設定すれば良い。又ここでのダイ
オードチップ（３）はフリ
ーホイーリングダイオードと呼ばれ、ＧＴＯ（２）チッ
プと逆並列に接続されている。このダイオードの実装時
の機能は公知であるので、詳細説明は省略する。The structure and assembly process of an embodiment of the present invention will be described below, taking as an example the case where the main circuit element chip is a GTO and 8 parallel connections are made in one package. FIG. 1 shows an example of the planar arrangement of chips in the above case. There is an insulating plate (4) brazed on the heat sink (1), and the upper surface of the insulating plate (4) is metallized in the shaded area as shown in Figure 3.
A GTO chip (2) and a diode chip (3) are soldered onto the anode electrode plate (8). Further, the cathode electrode part (6') of the cylindrical cathode lead (6) is placed on the cathode electrode (16) of the insulating plate (4), and the gate electrode part (5') of the cylindrical gate lead (5) is placed on the cathode electrode (16) of the insulating plate (4). However, the insulating plate (4
), and a cylindrical anode lead (7) is brazed onto the anode electrode (17) on the insulating plate. The cathode electrode on the GTO chip (2) and the cathode electrode brazed on the insulating plate (4)
6'), between the gate electrode (5) on the GTO (2) chip (2) and the gate electrode brazed to the insulating plate (4), and between the surface electrode of the diode chip and the cathode electrode (
5°) are connected with AQ wires (9). In FIG. 7, each AQ line is shown as one for ease of viewing, but the number of AQ lines (9) may be set based on the current capacity of the GTO chip (2). Also, the diode chip (3) here is called a freewheeling diode, and is connected antiparallel to the GTO (2) chip. Since the function of this diode when mounted is well known, detailed explanation will be omitted.
上述した、各種リードとチップのろう付の状況を第２図
に示す。この方法でのろう付は半田付が一般であり容易
にろう付可能であり、ろう付後アノードリード（７）、
カソードリード（６）、ゲートリード（５）が、同軸ケ
ーブル状に同心円配置された格好となる。FIG. 2 shows the state of brazing the various leads and chips described above. Brazing by this method is generally soldered and can be easily brazed, and after brazing, the anode lead (7),
The cathode lead (6) and gate lead (5) are arranged in concentric circles like a coaxial cable.
その結果、該ＧＴ○チップを含む各々の内部配線が幾可
学的に完全対称配置となるためアノード、カソード、ゲ
ートの各配線の抵抗成分、リアクタンス成分が全く等し
くなる。As a result, each internal wiring including the GT○ chip has a geometrically completely symmetrical arrangement, so that the resistance and reactance components of the anode, cathode, and gate wirings are completely equal.
この同軸ケーブル状リードが前記した外部引き出し端子
となり、外部端子と接続されることになる。主電流の流
れるアノードリード（７）、カソードリード（６）は電
流の方向が逆数、各々の電流変化による磁界を互いに相
殺する機能を有している。このため、配線におけるＬ成
分を非常に小さく出来る。又、アノードリード（７）と
カソードリード（６）にはさまれたゲートリード（５）
も同様の効果で、主電流の変化による磁界の影響を受け
づらくなる。This coaxial cable-like lead becomes the above-mentioned external lead terminal and is connected to an external terminal. The anode lead (7) and cathode lead (6), through which the main current flows, have reciprocal current directions and have the function of canceling out magnetic fields caused by changes in each current. Therefore, the L component in the wiring can be made very small. Also, the gate lead (5) is sandwiched between the anode lead (7) and the cathode lead (6).
has a similar effect, making it less susceptible to the effects of magnetic fields caused by changes in the main current.
上述したプロセスで組立だサブアセンブリ構造にプラス
チックケース（ｌ Ｏ）を接着し、ＡＱワイヤ（９）を
保護するための低弾性率レジン（２１）、および外部と
の連間を目的としたハードレジン（１１）でモールドす
る。このモールド後の構造を第１図の断面図に示す。A plastic case (lO) is adhered to the subassembly structure assembled by the above process, a low elastic modulus resin (21) is used to protect the AQ wire (9), and a hard resin is used for connection with the outside. Mold in step (11). The structure after this molding is shown in the sectional view of FIG.
この時、各種リード間を絶縁するための絶縁リング（１
２，１３，１４）が必要である。この絶縁リング（１２
，１３，１４）はセラミック、エポキシ等の材質で、モ
ールド時に挿入しても良いし、リード状態で表面処理的
に装着する方法もあり、効率の良い装着法を選べば良い
。At this time, an insulating ring (1
2, 13, 14) are required. This insulation ring (12
, 13, 14) are made of a material such as ceramic or epoxy, and may be inserted during molding, or may be mounted in a lead state by surface treatment, and the most efficient mounting method may be selected.
又、ゲートリード、カソードリード、アノードリードの
形状についても円筒状、円柱状に限る必要はなく、並列
接続チップ数（ｎ）に応じた、正ｎ角形を用いても良い
。Furthermore, the shapes of the gate lead, cathode lead, and anode lead are not limited to cylindrical or cylindrical shapes, and regular n-gon shapes depending on the number (n) of chips connected in parallel may be used.
以上に述べて来たプロセス、および構造の物に外部端子
（１８，１９，２０）を装着したものを第４図に示す。FIG. 4 shows the process and structure described above with external terminals (18, 19, 20) attached.
第３図は、パッケージとしての完成図である。FIG. 3 is a diagram of the completed package.
カソードリード（６）にカソード端子（２０）がろう付
されアノードリード（７）にアノード端子（１８）が、
ろう付され、ゲートリード（５）にはゲート端子（１９
）がろう付されている。A cathode terminal (20) is brazed to the cathode lead (6), an anode terminal (18) is brazed to the anode lead (7),
The gate terminal (19) is soldered to the gate lead (5).
) are brazed.
本構造およびプロセスで製作されたパッケージ型モジュ
ールは、搭載するＧＴＯチップの各々のオン電圧特性の
みを合わせることにより、並列動作が良好となる。従っ
て、該パッケージ型モジュールは搭載した単品のＧＴＯ
チップの電流容量の７〜８倍の電流容量がとれる。この
該パッケージ型モジュールは大電流高速スイッチング機
能を有し、かつ安価に製造出来るという大きなメリット
を持つことになる。The packaged module manufactured using this structure and process has good parallel operation by matching only the on-voltage characteristics of each of the mounted GTO chips. Therefore, the packaged module is equipped with a single GTO.
The current capacity can be 7 to 8 times the current capacity of the chip. This package type module has the great advantage of having a large current high speed switching function and being able to be manufactured at low cost.
本発明によれば、自己消弧機能を有する高速スイッチン
グ素子の大電流化を可能とする。According to the present invention, it is possible to increase the current of a high-speed switching element having a self-extinguishing function.
安価で、高性能の大電流高速スイッチングモジュールの
半導体装置を提供することができる。It is possible to provide an inexpensive, high-performance, high-current, high-speed switching module semiconductor device.
第１図は本発明の一実施例のチップ平面配置とモールド
後のパッケージ断面の関係を示す説明図。
第２図は同軸ケーブルリード、チップのろう付性説明図
、第３図は絶縁板上面図、第４図は完成図、第５図は１
パツケ一ジ内チツプ直接並列接続状況模式図、第６図は
第５図の等価回路図、第７図はチップと外部引き出しリ
ードの配置関係図である。
ｌ・・・ヒートシング、２・・・ＧＴＯチップ、３・・
・ＦＷＤチップ、４・・・絶縁板、５・・・ゲートリー
ド、６・・・カソードリード、７・・・アノードリード
、８・・・アノード電極、９・・・ＡＱワイヤ、１０・
・・プラスチックケース、１１・・・ハードレジン、１
２，１３゜１４・・・絶縁リング、１５・・・ゲート電
極、１６・・・カソード電極、１７・・・アノード電極
、１８・・・アノード端子、１９・・・ゲート端子、２
０・・・カソード端子、２１・・・低弾性率レジン。FIG. 1 is an explanatory diagram showing the relationship between the planar layout of a chip and the cross section of a package after molding according to an embodiment of the present invention. Figure 2 is an explanatory diagram of coaxial cable lead and chip brazing properties, Figure 3 is a top view of the insulating plate, Figure 4 is a completed diagram, and Figure 5 is 1
FIG. 6 is an equivalent circuit diagram of FIG. 5, and FIG. 7 is a diagram showing the arrangement of chips and external lead leads. l...Heat sink, 2...GTO chip, 3...
・FWD chip, 4... Insulating plate, 5... Gate lead, 6... Cathode lead, 7... Anode lead, 8... Anode electrode, 9... AQ wire, 10.
...Plastic case, 11...Hard resin, 1
2,13゜14... Insulating ring, 15... Gate electrode, 16... Cathode electrode, 17... Anode electrode, 18... Anode terminal, 19... Gate terminal, 2
0...Cathode terminal, 21...Low modulus resin.
Claims (1)
が複数個電気的に並列接続された状態で搭載されるパッ
ケージ型モジュールにおいて、電気的に並列接続される
各々の前記シリコンチップがそれぞれ同心円上に幾何学
的対称に配置されており、電気的に並列接続された前記
シリコンチップの同種の電極を集中接続した内部電極と
、パッケージ外部での外部接続用端子とを結ぶ外部引出
しリードが、同心円の中心線近傍に配置され、前記シリ
コンチップの有する電極種の数だけある前記外部引出し
リードが、同軸ケーブル上に集中配置されてなることを
特徴とする半導体装置。1. In a packaged module in which a plurality of silicon chips of semiconductor elements having a self-arc extinguishing function are mounted electrically connected in parallel, each of the silicon chips electrically connected in parallel is arranged on a concentric circle. The external lead leads connect the internal electrodes, which are arranged geometrically symmetrically and electrically connected in parallel with the same type of electrodes of the silicon chip, and the external connection terminals outside the package. A semiconductor device characterized in that the external lead leads, which are arranged near a center line and whose number corresponds to the number of electrode types possessed by the silicon chip, are centrally arranged on a coaxial cable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60290611A JPS62150871A (en) | 1985-12-25 | 1985-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60290611A JPS62150871A (en) | 1985-12-25 | 1985-12-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62150871A true JPS62150871A (en) | 1987-07-04 |
Family
ID=17758237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60290611A Pending JPS62150871A (en) | 1985-12-25 | 1985-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62150871A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0328815A2 (en) * | 1988-02-16 | 1989-08-23 | Sierra Technologies Inc. | Method for packaging a microwave tube modulator |
| EP0431420A2 (en) * | 1989-12-08 | 1991-06-12 | Siemens Aktiengesellschaft | High current rectifier |
| EP0645815A3 (en) * | 1993-09-07 | 1995-09-06 | Delco Electronics Corp | High power semiconductor switch module. |
| EP0645814A3 (en) * | 1993-09-07 | 1995-09-20 | Delco Electronics Corp | Semiconductor power switching device module. |
| US5517059A (en) * | 1994-04-26 | 1996-05-14 | Delco Electronics Corp. | Electron and laser beam welding apparatus |
| CN102456635A (en) * | 2010-11-04 | 2012-05-16 | 赛米控电子股份有限公司 | Semiconductor module with a substrate with a number of identically designed conductor line groups |
| JP6352555B1 (en) * | 2017-06-19 | 2018-07-04 | 新電元工業株式会社 | Semiconductor device |
| JP6352556B1 (en) * | 2017-06-19 | 2018-07-04 | 新電元工業株式会社 | Semiconductor device |
-
1985
- 1985-12-25 JP JP60290611A patent/JPS62150871A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0328815A2 (en) * | 1988-02-16 | 1989-08-23 | Sierra Technologies Inc. | Method for packaging a microwave tube modulator |
| EP0431420A2 (en) * | 1989-12-08 | 1991-06-12 | Siemens Aktiengesellschaft | High current rectifier |
| EP0645815A3 (en) * | 1993-09-07 | 1995-09-06 | Delco Electronics Corp | High power semiconductor switch module. |
| EP0645814A3 (en) * | 1993-09-07 | 1995-09-20 | Delco Electronics Corp | Semiconductor power switching device module. |
| US5519253A (en) * | 1993-09-07 | 1996-05-21 | Delco Electronics Corp. | Coaxial switch module |
| US5563447A (en) * | 1993-09-07 | 1996-10-08 | Delco Electronics Corp. | High power semiconductor switch module |
| US5517059A (en) * | 1994-04-26 | 1996-05-14 | Delco Electronics Corp. | Electron and laser beam welding apparatus |
| EP2450952A3 (en) * | 2010-11-04 | 2014-02-19 | SEMIKRON Elektronik GmbH & Co. KG | Semiconductor module with a substrate with a number of identically designed conductor line groups |
| CN102456635A (en) * | 2010-11-04 | 2012-05-16 | 赛米控电子股份有限公司 | Semiconductor module with a substrate with a number of identically designed conductor line groups |
| JP6352555B1 (en) * | 2017-06-19 | 2018-07-04 | 新電元工業株式会社 | Semiconductor device |
| JP6352556B1 (en) * | 2017-06-19 | 2018-07-04 | 新電元工業株式会社 | Semiconductor device |
| WO2018235135A1 (en) * | 2017-06-19 | 2018-12-27 | 新電元工業株式会社 | Semiconductor device |
| WO2018235137A1 (en) * | 2017-06-19 | 2018-12-27 | 新電元工業株式会社 | Semiconductor device |
| US10199486B2 (en) | 2017-06-19 | 2019-02-05 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device |
| KR101950131B1 (en) * | 2017-06-19 | 2019-02-19 | 신덴겐코교 가부시키가이샤 | Semiconductor device |
| US10243477B2 (en) | 2017-06-19 | 2019-03-26 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device having a bypass capacitor |
| KR20190087686A (en) * | 2017-06-19 | 2019-07-25 | 신덴겐코교 가부시키가이샤 | Semiconductor device |
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