JPS61139051A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce electric effect on transistor chips, which are connected in parallel, by forming an emitter electrode taking out lead at the center between the parallel transistor chips or in such a manner the approximately equal distance is provided. CONSTITUTION:An external electrode taking out lead 13 of an emitter is arranged at the center between the positions on a metal relay plate 12, to which bonding wires from two transistor chips 1 and 2 are connected. The lead is separated from the positions at the approximately equal distance. Then, electric resistance and the inductance component of wiring can be made equal along the path from each transistor chip 1 or 2 to the external electrode taking out lead 13 through each bonding wire 51 formed by aluminum and the like and the metal relay plate 12. Thus the operations of the parallel transistor chips are made equal, and the breakdown strength can be improved.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device suitable for configuring a resin-sealed insulated Tenryu Quadrantistor module, and particularly for use in applications such as motor control that handles large currents. This is a transistor module that is used when a plurality of transistor chips are operated in parallel inside the module.

[Technical background of the invention and its problems]

Conventionally, there are some Tenryu quadrant transistor modules with a rated current of several hundred amperes. In general, these transistor modules that handle large currents have a plurality of transistor chips 1 and 2 arranged inside the module as shown in FIG. The relay metal plates 12, 22, 32 are extended as they are using thin wires, and the electrodes are led out of the sealing resin. Further, as shown in FIG. 14, another metal lead may be soldered to the relay metal plate to lead out the electrode outside the sealing resin. 11.21 in Figures 13 and 14
゜31 is an emitter, a lead for taking out the external electrode of the luctor, and a paste, 61 is a ceramic substrate, and 71 is a solder. Fig. 13 (b) is the electrical equivalent circuit diagram of Fig. 13 (a) and Fig. 14. be.

By the way, the reasons why chips are used in parallel are to prevent the area of a single transistor chip from becoming extremely large in terms of mass production of transistor chips, to reduce the external size of the module as much as possible, and to increase the versatility of transistor chips. It is considered an essential technology for

In order to operate multiple transistor chips in parallel and with good performance, the current amplification factor, Vc x (
a a t ) (collector-emitter saturation voltage),
It is important that there is almost no difference in the static characteristics such as V□(sat) (saturation voltage between emitters). For example, the 15th
As shown in the figure, when the power supply VCO is 500V and the load RL is ON, the Heas current I is 2A.

In a test in which a current with a pulse width of 30 μs was applied, the current amplification factor, I! If there is a difference between the two transistors, there will be a difference in the value of the IC flowing through the two transistors 1°2 for about 30μ8 after the collector current rises. However, Fig. 15 (,)
And A is the characteristic of transistor chip 1, hF! ! If it is large, B is the characteristic of the transistor chip 2 and it is the case if h0 is small.

On the other hand, in the conventional example shown in FIGS. 13 and 14, even if the current amplification factors are the same between both chips 1 and 2, as shown in FIG. There was a difference in the start-up time. For example, considering the safe operating area when a load is short-circuited, ■. It is thought that destruction occurs due to the instantaneous power generated when the voltage rises, and in the above example, the destruction occurs due to transistor 1. Also, in the case of an L (inductance) load, even if the current amplification factor is the same in the conventional parallel system, the pI is different from the transistor 1 side as shown in FIG. flows. At this time, power supply Vaa = 300 V,
I, -+2A/-4A was applied.

This means that even in the reverse bias safe operating region, destruction occurs due to transistor 1 being overloaded in the conventional example.

As described above, in the conventional parallel method, even when transistor chips 1 and 2 with matching current amplification factors are connected in parallel,
The current was not constant between each transistor, and a large amount of current flowed to the transistor chip 1 on the side closer to the externally leading electrode 11 of the emitter. For this reason, the safe operating area in both the forward and reverse directions was determined by the transistor that would be overloaded.

[Purpose of abolishing Ming]

The present invention has been made in view of the above-mentioned circumstances, and aims to equalize the operation of parallel transistor chips and improve breakdown resistance.

[Summary of the invention]

The present invention forms the emitter electrode lead at the center or approximately equidistant between the parallel transistor chips, equalizes the inductance component and resistance component due to the wiring, and minimizes the electrical influence on the transistor chips connected in parallel. It has been reduced.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example corresponding to FIG. 13 using a parallel connection method in the case of two transistor chips of the present invention, and FIG.
This is an example corresponding to FIG. Here, corresponding parts are given the same reference numerals, explanations are omitted, and characteristic points will be explained. The feature of this embodiment is that in both FIG. They are placed at equal distances. In this way, each transistor chip 1, 2 is made of aluminum or the like. Ending wire 51. The electrical resistance and wiring components of everything from the relay metal plate 12 to the external electrode lead 13 can be made the same. Although this embodiment shows a case in which only the emitter is improved, it is desirable that the external electrode leads of the pacer and collector be similarly placed in the center. However, the effects described below are highly dependent on the emitter external output electrode lead 13, and a satisfactory improvement to some extent can be achieved just by improving the emitter electrode lead.

Even when connecting three or more transistor chips in parallel,
Similarly, this can be achieved by designing the external electrode leads of the emitter to be completely equivalent in terms of wiring from each transistor chip.

FIG. 3 shows each transistor chip f1, corresponding to FIG.
FIG. 2 is an IC waveform diagram of No. 2. Figure 4 corresponds to Figure 17.
c is a waveform diagram. In either case, the current value flowing through each transistor chip 1.2 is transistor chip f1.2
Both are substantially the same, and the value is an intermediate value between the values of overload transistor chips 1 and 2 in FIGS. 16 and 17.

FIG. 5 is a comparison between the reverse direction safe operation area of a module based on the parallel connection method of two transistor chips according to the present invention and a conventional example, and each point indicates a breaking point.

Vclg z (S um ) is the CICXC messing voltage, and ICICX is the current flowing between the collector and emitter, and it can be seen that the one according to the present invention is more resistant to destruction. Figure 6 shows the transistor chip used in the above test. This figure shows the location of destruction in the reverse direction safe operation area in the case of a single unit.The measurement conditions at this time are the same as in the case of Fig. 17.However, I, = +IA/-2A.From these, the present invention When connected in parallel, the safety operating area in the reverse direction is twice as large as that of a single unit.

It can be seen that a safe operating area corresponding to the above is secured.

Figure 7 shows the breakdown caused by the load short circuit test.
A comparison is made based on the distribution of the number of occurrences for each c. Figure 7 (
, ) are based on the conventional example, and FIG. 7(b) is the case based on the embodiment of the present invention. FIG. 8 similarly shows the case of a single transistor chip. The measurement circuit is shown in FIG.

However, input ■.

is IA in the case of a single transistor chip, and two people in the case of parallel transistors. Even in this case, it can be confirmed that the parallel connection according to the present invention has the same ability as the load short-circuit safe operation area of a single unit. Figure 7,
It can be seen from FIG. 9 that even if transistor chips are connected in parallel according to the present invention, a breakdown strength corresponding to the breakdown strength of a single transistor chip can be obtained. Although the effects of the present invention have been described above, these effects become more noticeable when the resistance component and inductance component of the wiring portion are large.

As a circuit support substrate that forms the internal structure of a transistor module, a thermal sprayed substrate or a DBC (D
An ir@ct Bond Copp@r) substrate may be used. The former is a circuit constructed by thermally spraying Cu on the top surface of a ceramic insulator (1), and the latter is a circuit formed by bonding a thin Cu film to the top surface of a ceramic using hypoeutectic Cu.

The use of these members makes it easy to assemble transistor modules, so they are being actively used as circuit support substrates.

However, due to problems with the manufacturing technology of each substrate, the maximum thickness of the Cu that makes up the circuit is several thousand angstroms for the former and several hundred μm for the latter, which inevitably results in large values for both wiring impedance and inductance. Become. In such cases, the effects of the present invention are significant.

Furthermore, when using the above circuit board, an emitter is used.

Collector, pace external number electrode lead 13.21
．． 31 is desirably used in combination with a terminal holder (resin) 81 as shown in FIG. 11 which is pre-molded with resin. The ideal application of the invention in this case, namely the emitter.

If we try to equalize the wiring impedance and inductance for all semiconductor chips connected in parallel in all the external output electrode leads of the collector and pace, the shape as shown in Figure 11 will be obtained. Electrode lead 11.21.31 and relay metal plate 12゜2
When soldering with 2.32, the stability of the terminal holder part due to the resin 81 is sometimes extremely poor, resulting in a lack of mass productivity. Figure 12 is an example of a terminal holder shape that solves this problem, and stability is achieved by branching at least one of the external electrode leads for the emitter, collector, and pace into two as shown in the figure. It has gained. Although the present invention has been described above using a transistor as an example, the applicable elements are not limited to this.

〔Effect of the invention〕

As described above, according to the present invention, since the operation of the parallel transistor chips is made uniform, the electrical influence on each chip can be reduced, and a semiconductor device with improved breakdown resistance can be provided.

[Brief explanation of drawings]

Figures 1 and 2 are perspective views showing each embodiment of the present invention, and Figure 3 is a perspective view showing each embodiment of the present invention.
8 through 8 are characteristic diagrams for explaining the effects of the same embodiment, FIG. 9 is a characteristic test circuit diagram, and FIGS. 10 through 12.
The figure is a perspective view showing main parts of a different embodiment of the present invention.
Figure (a) is a perspective view showing an example of a conventional device, and Figure 13 (b) is a perspective view showing an example of a conventional device.
) is its equivalent circuit diagram, FIG. 14 is a perspective view showing another example of the conventional device, FIG. 15 (,) is a characteristic diagram of the conventional device, and FIG.
Figure (b) is the test circuit diagram, Figures 16 and 17 (,)
is a characteristic diagram of a conventional device, and FIG. 17(b) is a test circuit diagram thereof. - 1,2...transistor chip, 12.22°32.
・・Metal relay plate, 13, 21. 31・・External number electrode lead, 51・・Gendering wire, 61・・
・Ceramic substrate, 71...Solder, 81...Resin O Fig. 1 Fig. 2 Fig. 3 Fig. 5 Fig. 6 VJ Fig. 7 (a) (1)) Fig. 8 □ V mark s9 Fig. Fig. 10 Fig. 11 Fig. 12 Fig. 13 (a) (b) Fig. 14 Fig. 15 (a) (AIS) □ Fig. 16 Fig. 17 □

Claims (8)

[Claims] (1) A plurality of semiconductor chips having substantially the same characteristics are connected in parallel and sealed in one envelope, and at least the external electrode leads of the base, emitter, and collector of the semiconductor chips are outside the envelope. A semiconductor device characterized in that an emitter electrode lead led out to an emitter portion of the semiconductor chip connected in parallel is connected by substantially equivalent metal wiring. (2) The plurality of semiconductor chips are DBC (Direct
The method of the present invention is characterized in that it is arranged on a bond copper (bond copper) substrate, and has an emitter electrode external lead that is separately soldered to an emitter part of the semiconductor chip and a metal relay plate formed on the DBC substrate. The semiconductor device according to scope 1. (3) Claim 2, characterized in that the relay metal plate and the emitter electrode external lead are integrated.
The semiconductor device described in . (4) The external electrode lead of the base, emitter, and collector is formed separately from the relay metal plate of the lead, and is connected to the relay metal plate by soldering. The semiconductor device according to scope 1. (5) The semiconductor device according to claim 4, wherein the relay metal plate and the external electrode lead are integrated. (6) The external electrode lead of the base, emitter, and collector is a component that is integrated with resin in advance before being soldered to the relay metal plate of the lead. The semiconductor device described in . (7) At least one of the external electrode extraction leads is
2. The semiconductor device according to claim 1, wherein the semiconductor device has two or more branches and is soldered to the relay metal plate of the lead at at least two or more locations. (8) The semiconductor device according to claim 7, wherein the relay metal plate and the external electrode lead are integrated.