JP2693688B2 - Multi-input / low-loss voltage regulator - Google Patents
Multi-input / low-loss voltage regulatorInfo
- Publication number
- JP2693688B2 JP2693688B2 JP4140254A JP14025492A JP2693688B2 JP 2693688 B2 JP2693688 B2 JP 2693688B2 JP 4140254 A JP4140254 A JP 4140254A JP 14025492 A JP14025492 A JP 14025492A JP 2693688 B2 JP2693688 B2 JP 2693688B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- output
- chips
- pnp
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＰＮＰ型トランジスタ
チップとこれのベース電流を制御する出力制御用ＩＣチ
ップとを各々１個づつ１組として組み合わせ、これの複
数組をリードフレームの放熱フィン部として機能するチ
ップ搭載部に搭載し、これらをモールド樹脂で被覆封止
してなる多入出力低損失ボルテージレギュレータに関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention combines a PNP type transistor chip and an output control IC chip for controlling a base current of the PNP type transistor chip as a set, and a plurality of sets are combined to form a radiation fin portion of a lead frame. The present invention relates to a multi-input / low-loss voltage regulator that is mounted on a chip mounting portion that functions as, and is covered and sealed with a mold resin.
【０００２】[0002]
【従来の技術】一般に、低損失ボルテージレギュレータ
は、図４に示すように、ＰＮＰ形トランジスタチップ
（１）と、これのベース電流を制御する出力制御用ＩＣ
チップ（２）とを組み合わせて構成され、電圧入力端子
（Ｖｉ）から入力される非安定の入力電圧を一定電圧に
安定化して電圧出力端子（Ｖｏ）から出力するようにな
っている。ＰＮＰ形トランジスタチップ（１）を用いる
ことにより、通常ダーリントン接続構成として用いられ
るＮＰＮ形トランジスタチップの場合に比し低損失にな
っている。2. Description of the Related Art Generally, as shown in FIG. 4, a low loss voltage regulator includes a PNP transistor chip (1) and an output control IC for controlling the base current of the PNP transistor chip (1).
It is configured by combining with the chip (2), and the unstable input voltage input from the voltage input terminal (Vi) is stabilized to a constant voltage and output from the voltage output terminal (Vo). By using the PNP type transistor chip (1), the loss is lower than that of the NPN type transistor chip normally used as the Darlington connection configuration.
【０００３】そして、前述の低損失ボルテージレギュレ
ータは、図３に示すように、リードフレーム（３）の各
放熱フィン部としても機能するチップ搭載部（３ａ）
に、各々１個のＰＮＰ形トランジスタチップ（１）と出
力制御用ＩＣチップ（２）とを１組として搭載し、ＰＮ
Ｐ形トランジスタチップ（１）と出力制御用ＩＣチップ
（２）相互間およびこれらと入力用、出力用および接地
用の各リード端子（３ｂ）〜（３ｄ）との所要間を、金
線等の金属ワイヤ（４）をワイヤボンディングすること
により電気的に接続し、１点鎖線で示す所定部分をモー
ルド樹脂（５）で被覆封止した後に、破線で示す部分を
切断してリードフレーム（３）の連結片（３ｆ）および
補強片（３ｅ）を除去し、個々の低損失ボルテージレギ
ュレータに分離する工程を経て製作される。また、ＰＮ
Ｐ形トランジスタチップ（１）は、図５に示すように、
一面にベース電極（Ｂ）とエミッタ電極（Ｅ）とが形成
され、且つ他面にコレクタ電極（Ｃ）が形成された構成
になっている。従って、ＰＮＰ形トランジスタチップ
（１）は、リードフレーム（３）の出力用リード端子
（３ｃ）と一体であって電圧出力部となったチップ搭載
部（３ｃ）に、コレクタ電極（Ｃ）を半田（６）付して
搭載されている。一方、出力制御用ＩＣチップ（２）
は、ボンディングすべき面が接地部であってチップ搭載
部（３ａ）に対し電気的絶縁状態に搭載する必要がある
ため、エポキシ系の絶縁ペースト（７）によりダイボン
ディングされている。As shown in FIG. 3, the above-mentioned low-loss voltage regulator has a chip mounting portion (3a) which also functions as each radiation fin portion of the lead frame (3).
Each of them has a PNP transistor chip (1) and an output control IC chip (2) mounted as a set.
Between the P-type transistor chip (1) and the output control IC chip (2) and between these and the lead terminals (3b) to (3d) for input, output and ground, a gold wire or the like is provided. The metal wire (4) is electrically connected by wire bonding, and a predetermined portion indicated by a one-dot chain line is covered and sealed with a molding resin (5), and then a portion indicated by a broken line is cut to form a lead frame (3). The connecting piece (3f) and the reinforcing piece (3e) are removed and separated into individual low loss voltage regulators. Also, PN
The P-type transistor chip (1), as shown in FIG.
The base electrode (B) and the emitter electrode (E) are formed on one surface, and the collector electrode (C) is formed on the other surface. Therefore, the PNP transistor chip (1) is soldered with the collector electrode (C) to the chip mounting portion (3c) which is integrated with the output lead terminal (3c) of the lead frame (3) and serves as a voltage output portion. (6) Attached. On the other hand, output control IC chip (2)
Since the surface to be bonded is the grounding part and the chip mounting part (3a) needs to be mounted in an electrically insulated state, it is die-bonded with an epoxy-based insulating paste (7).
【０００４】[0004]
【発明が解決しようとする課題】ところで、低損失ボル
テージレギュレータを構成要素とする電子機器の多機能
化が近年において促進されるに伴い、多入出力を有する
低損失ボルテージレギュレータが要望されている。然し
乍ら、前述の低損失ボルテージレギュレータでは、リー
ドフレーム（３）のチップ搭載部（３ａ）が出力用リー
ド端子（３ｃ）と一体の電圧出力部となっているため
に、このチップ搭載部（３ａ）に複数個のＰＮＰ形トラ
ンジスタチップ（１）を搭載できないことから複数入出
力構成にすることができない。そのため、単入出力の低
損失ボルテージレギュレータを複数個用いて多入出力構
成に組み立てており、比較的広い取付スペースやレギュ
レータ相互の配線等を要して機器が大型化する問題があ
る。By the way, in recent years, as the multifunctionalization of electronic equipment including a low-loss voltage regulator as a constituent element has been promoted in recent years, a low-loss voltage regulator having multiple inputs and outputs has been demanded. However, in the above-mentioned low loss voltage regulator, since the chip mounting part (3a) of the lead frame (3) is a voltage output part integrated with the output lead terminal (3c), this chip mounting part (3a) Since a plurality of PNP type transistor chips (1) cannot be mounted on the above, a multiple input / output configuration cannot be achieved. Therefore, a plurality of single-input / output low-loss voltage regulators are used to assemble a multi-input / output configuration, and a relatively large mounting space and wiring between the regulators are required, which causes a problem of increasing the size of the device.
【０００５】そこで本発明は、同一リードフレームに複
数組のＰＮＰ形トランジスタチップと出力制御用ＩＣチ
ップとを搭載して多入出力に構成できる低損失ボルテー
ジレギュレータを提供することを技術的課題とするもの
である。Therefore, it is a technical object of the present invention to provide a low loss voltage regulator in which a plurality of sets of PNP type transistor chips and output control IC chips are mounted on the same lead frame and which can be configured for multiple inputs and outputs. It is a thing.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記した課題
を達成するための技術的手段として、多入出力低損失ボ
ルテージレギュレータを次のように構成した。即ち、各
々１個づつのＰＮＰ形トランジスタチップとこれのベー
ス電流を制御する出力制御用ＩＣチップとの組み合わせ
を複数組備え、単一の前記ＰＮＰ形トランジスタチップ
を、単一のリードフレームにおける電圧出力部となるチ
ップ搭載部に電気的接続状態に搭載し、その他の前記各
ＰＮＰ形トランジスタチップをそれぞれ個別の金属シー
トの一面に電気的接続状態に接着するとともに、該各金
属シートの他面を前記チップ搭載部に絶縁ペーストを介
在して取着し、前記各出力用制御用ＩＣチップを、各々
対応する前記各ＰＮＰ形トランジスタチップに近接して
前記チップ搭載部に絶縁ペーストにより搭載し、組をな
す前記ＰＮＰ形トランジスタチップと出力制御用ＩＣチ
ップ相互間および該各チップと各々対応するリード端子
間を金属ワイヤでそれぞれ接続し、且つ前記各金属シー
トを、各々対応する出力用リード端子に金属ワイヤで接
続したことを特徴として構成されている。The present invention has a multi-input / low-loss voltage regulator configured as follows as a technical means for achieving the above-mentioned object. That is, a plurality of combinations of one PNP type transistor chip and an output control IC chip for controlling the base current of the PNP type transistor chip are provided, and the single PNP type transistor chip is used for voltage output in a single lead frame. Are mounted in an electrically connected state on a chip mounting portion as a part, and each of the other PNP transistor chips is adhered to one surface of an individual metal sheet in an electrically connected state, and the other surface of each metal sheet is The chips are mounted on the chip mounting portion with an insulating paste interposed therebetween, and the output control IC chips are mounted on the chip mounting portion with the insulating paste in the vicinity of the corresponding PNP transistor chips. A metal is formed between the PNP transistor chip and the output control IC chip, and between each of the chips and the corresponding lead terminal. Respectively connected in ear, and is configured and the respective metal sheet, to the output lead terminals, each corresponding as characterized by connected by metal wires.
【０００７】[0007]
【作用】単一のＰＮＰ形トランジスタチップのみが、単
一のリードフレームの電圧出力部となるチップ搭載部に
電気的接続状態にダイボンディングされて該チップ搭載
部に一体の出力用リード端子に導出され、その他の各Ｐ
ＮＰ形トランジスタチップは、個々の金属シートに接着
された状態で絶縁ペーストを介在して電気的絶縁状態と
することによりチップ搭載部に取着できるようにし、且
つ各金属シートおよび金属ワイヤを介して対応する出力
用リード端子に個々に導出されているので、単一のリー
ドフレームを用いながらも多入出力構成となっている。
この所要の入出力数の低損失ボルテージレギュレータを
電子機器を適用すれば、従来の単入出力低損失ボルテー
ジレギュレータを複数個用いる場合に比較して格段に小
型化できる。また、実使用においては、多入出力に対し
負荷が択一的に加わる場合が殆どであるため、放熱フィ
ン部として機能するリードフレームのチップ搭載部の面
積およびモールド樹脂等によるパッケージサイズが従来
の単入出力低損失ボルテージレギュレータに比較して格
段に大きいことから極めて良好な放熱効果を得るれる他
に、金属シートがＰＮＰトランジスタチップの発熱時の
過渡熱抵抗および飽和熱抵抗を良くするよう作用して該
トランジスタチップの熱破壊を防止するので、使用範囲
を拡大できる。Only a single PNP transistor chip is die-bonded to a chip mounting portion, which is a voltage output portion of a single lead frame, in an electrically connected state and led to an output lead terminal integrated with the chip mounting portion. And other P
The NP-type transistor chip can be attached to the chip mounting portion by being electrically insulated by interposing an insulating paste in a state of being adhered to each metal sheet, and through each metal sheet and metal wire. Since it is led out to the corresponding output lead terminals individually, it has a multi-input / output configuration while using a single lead frame.
If the electronic device is applied to this low-loss voltage regulator with the required number of inputs / outputs, it can be remarkably downsized as compared with the case where a plurality of conventional single-input / low-loss voltage regulators are used. In addition, in actual use, in most cases, loads are selectively applied to multiple inputs / outputs, so the area of the chip mounting part of the lead frame that functions as a heat dissipation fin and the package size due to the molding resin etc. Since it is significantly larger than the single input / output low loss voltage regulator, a very good heat dissipation effect is obtained, and the metal sheet acts to improve the transient thermal resistance and the saturated thermal resistance when the PNP transistor chip generates heat. As a result, thermal destruction of the transistor chip is prevented, so that the range of use can be expanded.
【０００８】[0008]
【実施例】以下、本発明の好適な一実施例について図面
を参照しながら詳述する。図１は本発明の一実施例の製
造過程における平面図を示し、同図において図３と同一
若しくは同等のものには同一の符号を付してその説明を
省略する。同図には、ＰＮＰ形トランジスタチップ
（１）および出力制御用ＩＣチップ（２）を２組設けた
場合を例示してある。従って、リードフレーム（８）の
放熱フィン部となるチップ搭載部（８ａ）は、各々２個
づつのＰＮＰ形トランジスタチップ（１）および出力制
御用ＩＣチップ（２）を搭載できる面積に形成されてい
るとともに、このチップ搭載部（８ａ）に特定の第１出
力用リード端子（８ｃ）が一体的に連結されており、他
の第２出力用リード端子（８ｆ）および各々２個づつの
入力用リード端子（８ｂ），（８ｅ）と接地用リード端
子（８ｄ），（８ｇ）が、モールド樹脂（５）で被覆後
に連結片（８ｉ）および補強片（８ｈ）を切断除去した
時に個々に独立する形態に設けられている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a plan view in the manufacturing process of an embodiment of the present invention, in which the same or equivalent parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The figure illustrates an example in which two sets of PNP transistor chips (1) and output control IC chips (2) are provided. Therefore, the chip mounting portions (8a) serving as the heat radiation fins of the lead frame (8) are formed in an area capable of mounting two PNP transistor chips (1) and two output control IC chips (2). In addition, a specific first output lead terminal (8c) is integrally connected to this chip mounting portion (8a), and another second output lead terminal (8f) and two input terminals each are provided. The lead terminals (8b), (8e) and the grounding lead terminals (8d), (8g) are individually independent when the connecting piece (8i) and the reinforcing piece (8h) are cut and removed after being covered with the mold resin (5). It is provided in the form.
【０００９】そして、図の左方に示す１組のＰＮＰ形ト
ランジスタチップ（１）および出力制御用ＩＣチップ
（２）は、それぞれ従来と同様に半田（６）および絶縁
ペースト（７）によりチップ搭載部（８ａ）にダイボン
ディングされている。一方、図の右方に示す他のＰＮＰ
形トランジスタチップ（１）は、金属シート（９）上に
半田（６）により電気的接続状態に取り付けた後に、こ
の金属シート（９）が絶縁ペースト（７）によりチップ
搭載部（８ａ）上に電気的絶縁状態に取着されてチップ
搭載部（８ａ）に対し電気的絶縁状態に取り付けられて
いる。A pair of PNP type transistor chip (1) and output control IC chip (2) shown on the left side of the figure are mounted by soldering (6) and insulating paste (7) as in the conventional case. It is die-bonded to the portion (8a). On the other hand, another PNP shown on the right side of the figure
The transistor chip (1) is mounted on the metal sheet (9) in an electrically connected state by solder (6), and then the metal sheet (9) is mounted on the chip mounting portion (8a) by the insulating paste (7). It is attached in an electrically insulated state and attached to the chip mounting portion (8a) in an electrically insulated state.
【００１０】更に、各組のＰＮＰ形トランジスタチップ
（１）と出力制御用ＩＣチップ（２）相互間、これらと
各々対応する各入力用、出力用および接地用の各リード
端子（８ｂ）〜（８ｇ）との各間および金属シート
（９）と第２出力用リード端子（８ｆ）間が、金線等の
金属ワイヤ（４）をワイヤボンディングすることにによ
りそれぞれ電気的に接続され、１点鎖線で示す所定部分
をモールド樹脂（５）で被覆封止して図示状態とした後
に、破線で示す部分を切断してリードフレーム（８）の
連結片（８ｉ）および補強片（８ｈ）を除去して個々の
低損失ボルテージレギュレータに分離される。Further, between each set of PNP type transistor chip (1) and output control IC chip (2), and corresponding lead terminals (8b) to () for input, output and ground respectively. 8g) and each of the metal sheet (9) and the second output lead terminal (8f) are electrically connected by wire bonding a metal wire (4) such as a gold wire. A predetermined portion indicated by a chain line is covered and sealed with a mold resin (5) to be in an illustrated state, and then a portion indicated by a broken line is cut to remove the connecting piece (8i) and the reinforcing piece (8h) of the lead frame (8). Then, it is separated into individual low loss voltage regulators.
【００１１】この低損失ボルテージレギュレーシは、左
方に示す特定の単一のＰＮＰ形トランジスタチップ
（１）のみをリードフレーム（８）の電圧出力部となる
チップ搭載部（８ａ）に電気的接続状態にダイボンディ
ングし、右方に示す他方のＰＮＰ形トランジスタチップ
（１）を、絶縁ペースト（７）を介在して電気的絶縁状
態とすることによりチップ搭載部（８ａ）に対し取り付
けできるようにするとともに、各々のコレクタ電極が金
属シート（９）および金属ワイヤ（４）を介して対応す
る各第２出力用リード端子（８ｆ）に接続されている。
従って、単一のリードフレーム（８）を用いるだけであ
りながら２入出力構成となっている。In this low loss voltage regulation, only a specific single PNP transistor chip (1) shown on the left side is electrically connected to a chip mounting portion (8a) which serves as a voltage output portion of a lead frame (8). So that the other PNP transistor chip (1) shown on the right side can be attached to the chip mounting portion (8a) by electrically bonding the other PNP transistor chip (1) shown in the right side through the insulating paste (7). In addition, each collector electrode is connected to the corresponding second output lead terminal (8f) via the metal sheet (9) and the metal wire (4).
Therefore, although only a single lead frame (8) is used, it has a 2-input / output configuration.
【００１２】尚、３個以上のＰＮＰ形トランジスタチッ
プ（１）のうちの単一のＰＮＰ形トランジスタチップ
（１）のみを半田（６）によりチップ搭載部（８ａ）に
電気的接続状態にダイボンディングするとともに、それ
ぞれ出力制御用ＩＣチップ（２）と組み合わせた他の所
要個数のＰＮＰ形トランジスタチップ（１）を、金属シ
ート（９）および絶縁ペースト（７）を介してチップ搭
載部（８ａ）に電気的絶縁状態に並設することにより、
３入出力以上の多入出力構成とすることもできる。この
所要の入出力数の低損失ボルテージレギュレータを用い
て電子機器を構成すれば、従来の単入出力低損失ボルテ
ージレギュレータを複数個用いる場合に比較して格段に
小型化できる。また、実使用においては、多入出力に対
し負荷が択一的に加わる場合が殆どであり、その場合に
は、リードフレーム（８）のチップ搭載部（８ａ）の面
積およびモールド樹脂（５）によるパッケージサイズが
従来の単入出力低損失ボルテージレギュレータに比較し
て格段に大きいことから極めて良好な放熱効果を得るれ
る他に、金属シート（９）がＰＮＰトランジスタチップ
（１）の発熱時の過渡熱抵抗および飽和熱抵抗を良くす
るよう作用して該トランジスタチップ（１）の熱破壊を
防止するので、使用範囲を拡大できる。Of the three or more PNP transistor chips (1), only a single PNP transistor chip (1) is die-bonded to the chip mounting portion (8a) by soldering (6). In addition, another required number of PNP-type transistor chips (1) each combined with the output control IC chip (2) are mounted on the chip mounting portion (8a) via the metal sheet (9) and the insulating paste (7). By arranging them in an electrically insulated state,
A multi-input / output configuration with three or more inputs / outputs is also possible. If the electronic device is configured using the low loss voltage regulator having the required number of inputs / outputs, the size can be significantly reduced as compared with the case where a plurality of conventional single input / output low loss voltage regulators are used. In actual use, a load is often applied selectively to multiple inputs / outputs. In that case, the area of the chip mounting portion (8a) of the lead frame (8) and the mold resin (5) are used. The package size is significantly larger than that of the conventional single-input / low-loss voltage regulator, so that a very good heat dissipation effect can be obtained, and the metal sheet (9) has a transient state when the PNP transistor chip (1) generates heat. The transistor chip (1) is prevented from being damaged by heat by improving the thermal resistance and the saturation thermal resistance, so that the range of use can be expanded.
【００１３】図２は本発明の他の実施例を示し、同図に
おいて図１と同一若しくは同等のものには同一の符号を
付してあり、相違する点は、金属シート（９）および絶
縁ペースト（７）を介してチップ搭載部（１０ａ）に電
気的絶縁状態に取り付けるＰＮＰ形トランジスタチップ
（１）とこれと組み合わせた出力制御用ＩＣチップ
（２）の位置を図１に対し左右入れ換え、それに応じて
リードフレーム（１０）を第２入力用リード端子（１０
ｆ）と第２出力用リード端子（１０ｅ）との位置を図１
に対し左右入れ換えた形状とし、接地用リード端子（１
０ｄ）を共通として図１よりもリード端子数を１本削減
した構成のみであり、図１と同様の効果を得られる。FIG. 2 shows another embodiment of the present invention. In FIG. 2, the same or equivalent parts as those in FIG. 1 are designated by the same reference numerals, except for the difference between the metal sheet (9) and the insulation. The positions of the PNP transistor chip (1) and the output control IC chip (2) combined with the PNP transistor chip (1) electrically attached to the chip mounting portion (10a) via the paste (7) are transposed relative to FIG. Accordingly, the lead frame (10) is connected to the second input lead terminal (10
f) and the position of the second output lead terminal (10e) are shown in FIG.
The left and right sides have been replaced with the ground lead terminal (1
0d) is common, and the number of lead terminals is reduced by one from that of FIG. 1, and the same effect as in FIG. 1 can be obtained.
【００１４】[0014]
【発明の効果】以上のように本発明の多入出力低損失ボ
ルテージレギュレータによると、複数個のうちの単一の
ＰＮＰ形トランジスタチップのみを単一のリードフレー
ムの電圧出力部となるチップ搭載部に電気的接続状態に
搭載し、その他の各ＰＮＰ形トランジスタチップを、個
々の金属シートに接着した状態で絶縁ペーストを介在し
て電気的絶縁状態とすることによりチップ搭載部に取着
できるようにし、且つ金属シートおよび金属ワイヤを介
して対応する各出力用リード端子に個々に導出した構成
としたので、単一のリードフレームにより多入出力構成
とすることができ、所要の入出力数の低損失ボルテージ
レギュレータを電子機器に適用することにより従来の単
入出力低損失ボルテージレギュレータを複数個用いる場
合に比較して格段に小型化できる。また、リードフレー
ムのチップ搭載部の面積およびパッケージサイズが従来
の単入出力低損失ボルテージレギュレータに比較して格
段に大きいことから極めて良好な放熱効果を得るれる他
に、金属シートがＰＮＰトランジスタチップの発熱時の
過渡熱抵抗および飽和熱抵抗を良くするよう作用して該
トランジスタチップの熱破壊を防止するので、使用範囲
を拡大できる利点がある。As described above, according to the multiple input / output low loss voltage regulator of the present invention, only a single PNP type transistor chip among a plurality of chips serves as a voltage output part of a single lead frame. Mounted in an electrically connected state, and the other PNP transistor chips are attached to individual metal sheets in an electrically insulated state with an insulating paste interposed therebetween so that they can be attached to the chip mounting portion. In addition, since it is configured to be individually led out to the corresponding output lead terminals through the metal sheet and the metal wire, it is possible to realize a multi-input / output configuration with a single lead frame, which reduces the required number of input / output. By applying the loss voltage regulator to electronic equipment, it is significantly better than when using multiple conventional single input / output low loss voltage regulators. It can be reduced in size. In addition, the chip mounting area of the lead frame and the package size are remarkably large as compared with the conventional single input / output low loss voltage regulator, so that a very good heat dissipation effect can be obtained, and the metal sheet is a PNP transistor chip. Since it acts to improve the transient thermal resistance and the saturated thermal resistance at the time of heat generation to prevent thermal destruction of the transistor chip, there is an advantage that the range of use can be expanded.
【図１】本発明の一実施例の製造過程における平面図で
ある。FIG. 1 is a plan view in the manufacturing process of an embodiment of the present invention.
【図２】本発明の他の実施例の製造過程における平面図
である。FIG. 2 is a plan view in the manufacturing process of another embodiment of the present invention.
【図３】従来の低損失ボルテージレギュレータの製造過
程における平面図である。FIG. 3 is a plan view in the manufacturing process of the conventional low loss voltage regulator.
【図４】同上の電気系のブロック図である。FIG. 4 is a block diagram of the electrical system of the above.
【図５】ボルテージレギュレータに用いるＰＮＰ形トラ
ンジスタチップの概略斜視図である。FIG. 5 is a schematic perspective view of a PNP type transistor chip used for a voltage regulator.
１ ＰＮＰ形トランジスタチップ ２ 出力制御用ＩＣチップ ４ 金属ワイヤ ６ 半田 ７ 絶縁ペースト ８，１０ リードフレーム ８ａ，１０ａ チップ搭載部 ８ｂ〜８ｇ，１０ｂ〜１０ｆ リード端子 ９ 金属シート 1 PNP type transistor chip 2 IC chip for output control 4 Metal wire 6 Solder 7 Insulating paste 8,10 Lead frame 8a, 10a Chip mounting part 8b-8g, 10b-10f Lead terminal 9 Metal sheet
Claims (1)
ップとこれのベース電流を制御する出力制御用ＩＣチッ
プとの組み合わせを複数組備え、単一の前記ＰＮＰ形ト
ランジスタチップを、単一のリードフレームにおける電
圧出力部となるチップ搭載部に電気的接続状態に搭載
し、その他の前記各ＰＮＰ形トランジスタチップをそれ
ぞれ個別の金属シートの一面に電気的接続状態に接着す
るとともに、該各金属シートの他面を前記チップ搭載部
に絶縁ペーストを介在して取着し、前記各出力用制御用
ＩＣチップを、各々対応する前記各ＰＮＰ形トランジス
タチップに近接して前記チップ搭載部に絶縁ペーストに
より搭載し、組をなす前記ＰＮＰ形トランジスタチップ
と出力制御用ＩＣチップ相互間および該各チップと各々
対応するリード端子間を金属ワイヤでそれぞれ接続し、
且つ前記各金属シートを、各々対応する出力用リード端
子に金属ワイヤで接続したことを特徴とする多入出力低
損失ボルテージレギュレータ。1. A plurality of combinations of one PNP transistor chip and one output control IC chip for controlling a base current of the PNP transistor chip are provided, and the single PNP transistor chip is used as a single lead frame. Of the PNP type transistor chips are electrically connected to one surface of each individual metal sheet, and the other PNP type transistor chips are electrically connected to the chip mounting portion serving as a voltage output section in The surface is attached to the chip mounting portion with an insulating paste interposed, and the output control IC chips are mounted on the chip mounting portion with the insulating paste in the vicinity of the corresponding PNP transistor chips. Between the PNP transistor chip and the output control IC chip forming a set, and between the lead terminals corresponding to the chips. Are connected with metal wires,
A multi-input / low-loss voltage regulator, wherein each of the metal sheets is connected to a corresponding output lead terminal by a metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140254A JP2693688B2 (en) | 1992-06-01 | 1992-06-01 | Multi-input / low-loss voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140254A JP2693688B2 (en) | 1992-06-01 | 1992-06-01 | Multi-input / low-loss voltage regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05335469A JPH05335469A (en) | 1993-12-17 |
| JP2693688B2 true JP2693688B2 (en) | 1997-12-24 |
Family
ID=15264509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4140254A Expired - Fee Related JP2693688B2 (en) | 1992-06-01 | 1992-06-01 | Multi-input / low-loss voltage regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2693688B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8951847B2 (en) | 2012-01-18 | 2015-02-10 | Intersil Americas LLC | Package leadframe for dual side assembly |
| JP7042117B2 (en) * | 2018-03-08 | 2022-03-25 | ローム株式会社 | Linear regulator |
-
1992
- 1992-06-01 JP JP4140254A patent/JP2693688B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05335469A (en) | 1993-12-17 |
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