JPH11163045A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH11163045A
JPH11163045A JP9324424A JP32442497A JPH11163045A JP H11163045 A JPH11163045 A JP H11163045A JP 9324424 A JP9324424 A JP 9324424A JP 32442497 A JP32442497 A JP 32442497A JP H11163045 A JPH11163045 A JP H11163045A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
solder
semiconductor
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9324424A
Other languages
Japanese (ja)
Inventor
Shinpei Yoshioka
心平 吉岡
Yasuto Saito
康人 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba AVE Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba AVE Co Ltd filed Critical Toshiba Corp
Priority to JP9324424A priority Critical patent/JPH11163045A/en
Priority to AU94105/98A priority patent/AU705177B1/en
Priority to US09/199,780 priority patent/US6255672B1/en
Priority to KR1019980050906A priority patent/KR100284241B1/en
Priority to EP98122182A priority patent/EP0923131A3/en
Priority to CNB981258913A priority patent/CN1146994C/en
Publication of JPH11163045A publication Critical patent/JPH11163045A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

PROBLEM TO BE SOLVED: To reduce failure of a semiconductor switching element by heat, by efficiently transferring the heat generated in a switching element to a heat sink, etc., by soldering each electrode by turning the switching element upside down. SOLUTION: An emitter electrode 2 is provided on the surface of an IGBT 1 and bonded to a prescribed position of a copper pattern 4a on the surface of a copper-plated ceramic substrate 3 with a solder layer 5. A gate electrode 6 is provided at the end section of the surface of the IGBT 1 and bonded to a prescribed position of the substrate 3 with a solder layer 5. To the rear surface of the substrate 3, a heat sink 7 is bonded through a copper pattern 4b with a solder layer 5. On the rear surface of the IGBT 1, in addition, a collector electrode 9 is bonded to a wiring material 10 arranged at a prescribed facing position with a solder layer 5. Therefore, the heat generated in the IGBT 1 can be radiated through the solder layers 5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特にパワーエレクトロニクス分野で
制御用に使用されるスィツチング素子のサイリスタやパ
ワートランジスタ等の実装構造とその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a mounting structure of a thyristor or a power transistor of a switching element used for control in the field of power electronics and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】近年、産業用ポンプやファン等のパワー
エレクトロニクスの制御分野では、インバータ装置を用
いたエネルギーの有効利用が用いられることが多い。こ
のインバータ装置の心臓部は電流をスイッチイングする
半導体スイッチング素子である。2. Description of the Related Art In recent years, in the field of control of power electronics such as industrial pumps and fans, effective use of energy using an inverter device is often used. The heart of this inverter device is a semiconductor switching element that switches the current.

【０００３】半導体スイッチング素子としては、従来か
らサイリスタやパワートランジスタ等が適用されること
が多い。最近では、ＧＴＯ（ゲート・ターンオフ・サイ
リスタ）、ＩＧＢＴ（インシュレイテッド・ゲート・バ
イポラトランジスタ）、ＩＥＧＴ（インジェクションエ
ンハンスド・ゲート・トランジスタ）等が広く用いられ
ている。As a semiconductor switching element, a thyristor, a power transistor, or the like is conventionally often used. Recently, GTOs (gate turn-off thyristors), IGBTs (insulated gate bipolar transistors), IEGTs (injection enhanced gate transistors), and the like have been widely used.

【０００４】これらの半導体スイッチング素子は種類に
より呼び方が異なる場合もあるが、いずれも、正極電
極、負極電極と制御電極の３つの電極を備え、制御電極
で電流や電圧を制御することによりスイッチイング動作
を行っている。Although these semiconductor switching elements may be called differently depending on the type, each of them has three electrodes, ie, a positive electrode, a negative electrode, and a control electrode, and the control electrode controls the current and voltage to control the switch. Ing operation.

【０００５】これらの素子をパッケージ内に実装する場
合には、正極電極と負極電極は大電流が流れるためとス
イッチング動作の際に著しく発熱する。従って、電流容
量を十分考慮する必要があると共に放熱構造にも十分配
慮する必要がある。When these elements are mounted in a package, since a large current flows through the positive electrode and the negative electrode, heat is generated significantly during switching operation. Therefore, it is necessary to sufficiently consider the current capacity and the heat dissipation structure.

【０００６】ＩＧＢＴを例に図４を参照して説明する
と、ＩＧＢＴ１は裏面には負極電極であるコレクタ電極
９が負極電極に対向した位置の銅張りセラミック基板３
の表面の銅パターン４a の所定位置にはんだ層５を介し
てはんだ接合されている。銅張りセラミック基板３の裏
面にも銅パターン４b が形成され、その銅パターン４b
はヒートシンク７にはんだ層５を介してはんだ接合され
ている。ヒートシンク７の周囲には図示しないプラスチ
ック製の外囲器が設けられている。また、ＩＧＢＴ１や
銅張りセラミック基板３の表面は絶縁のためシリコンゲ
ル等で封止されている。Referring to FIG. 4 taking an IGBT as an example, the IGBT 1 has a copper-clad ceramic substrate 3 on the back surface where a collector electrode 9 serving as a negative electrode faces the negative electrode.
Is solder-bonded via a solder layer 5 to a predetermined position of the copper pattern 4a. A copper pattern 4b is also formed on the back surface of the copper-clad ceramic substrate 3, and the copper pattern 4b is formed.
Is soldered to the heat sink 7 via the solder layer 5. A plastic envelope (not shown) is provided around the heat sink 7. The surfaces of the IGBT 1 and the copper-clad ceramic substrate 3 are sealed with silicon gel or the like for insulation.

【０００７】ＩＧＢＴ１の表面には、正極電極であるエ
ミッタ電極２が設けられ銅張りセラミック基板３の表面
の銅パターン４a の所定位置にアルミ線１５を用いたワ
イヤボンディングにより接続されている。なお、一般に
通電容量を考慮して複数のアルミ線１５で接続されてい
る場合が多い。また、ＩＧＢＴ１の表面にはゲート電極
６が設けられ、銅張りセラミック基板３の表面の銅パタ
ーン４にアルミ線１５を用いたワイヤボンディングによ
り接続されている。ゲート電極６は大電流を流す必要が
ないため通常１本のアルミ線１５で接続されている。An emitter electrode 2 serving as a positive electrode is provided on the surface of the IGBT 1 and is connected to a predetermined position of the copper pattern 4a on the surface of the copper-clad ceramic substrate 3 by wire bonding using an aluminum wire 15. In general, the connection is often made by a plurality of aluminum wires 15 in consideration of the current carrying capacity. A gate electrode 6 is provided on the surface of the IGBT 1 and is connected to the copper pattern 4 on the surface of the copper-clad ceramic substrate 3 by wire bonding using an aluminum wire 15. The gate electrode 6 is usually connected by one aluminum wire 15 because it is not necessary to flow a large current.

【０００８】これらの構造によりＩＧＢＴ１で発生した
熱は各端子２、６、９を経由して、はんだ層５、銅張り
セラミック基板３の表面の銅パターン４a 、セラミック
層１６、銅張りセラミック基板３の裏面の銅パターン４
b 、はんだ層５を経由してヒートシンク７に伝熱され外
部に放熱される。The heat generated in the IGBT 1 by these structures passes through the terminals 2, 6 and 9, and passes through the solder layer 5, the copper pattern 4 a on the surface of the copper-clad ceramic substrate 3, the ceramic layer 16 and the copper-clad ceramic substrate 3. Copper pattern 4 on the back of
b, heat is transferred to the heat sink 7 via the solder layer 5 and radiated to the outside.

【０００９】[0009]

【発明が解決しようとする課題】上述したＩＧＢＴ等の
半導体スイッチング素子を配線基板に実装した際の問題
点は、高負荷下で使用した場合、正極電極であるエミッ
タ電極のワイヤボンディング部が熱応力によって疲労破
壊を生じることである。A problem when the above-described semiconductor switching element such as an IGBT is mounted on a wiring board is that when used under a high load, the wire bonding portion of the emitter electrode which is the positive electrode has a thermal stress. This causes fatigue fracture.

【００１０】このため、エミッタ電極についてもコレク
タ電極と同様にはんだ接合する方法が試みられている。
しかしながら、この方法ではエミッタ電極を形状的に平
板又は棒状に形成する必要がある。そのため、製造プロ
セスを一元化するためにゲート電極をエミッタ電極と同
様の構造にすると、配線同士が相互に干渉する場合が生
じたり、配線の引き回しによっては電極の製作が困難に
なる欠点がある。もちろん、ゲート電極の配線をワイヤ
ボンディング接続で行うことも可能であるが、その場合
は、２種類の接続工程が必要になり工程が複雑になって
好ましくない。For this reason, a method of soldering the emitter electrode in the same manner as the collector electrode has been attempted.
However, in this method, it is necessary to form the emitter electrode into a flat plate or a rod shape. Therefore, if the gate electrode has the same structure as the emitter electrode in order to unify the manufacturing process, wirings may interfere with each other or the wiring may be difficult to manufacture depending on the wiring layout. Of course, the wiring of the gate electrode can be performed by wire bonding connection, but in that case, two types of connection steps are required, and the steps become complicated, which is not preferable.

【００１１】[0011]

【課題を解決するための手段】本発明によれば、半導体
能動領域の一方の表面に外部露出面を有する正極電極と
制御電極とが形成され、かつ、前記半導体能動素子の他
方の表面に外部露出面を有する負極電極が形成された半
導体スイッチング素子と、この半導体スイッチング素子
の前記正極電極と前記制御電極を所定位置で各々はんだ
接合した配線基板とを有することを特徴とする半導体装
置にある。According to the present invention, a positive electrode having an externally exposed surface and a control electrode are formed on one surface of a semiconductor active region, and an external electrode is formed on the other surface of the semiconductor active element. A semiconductor device includes a semiconductor switching element on which a negative electrode having an exposed surface is formed, and a wiring board formed by soldering the positive electrode and the control electrode of the semiconductor switching element at predetermined positions.

【００１２】また本発明によれば、前記負極電極は対応
する配線材との接続がはんだ接合であることを特徴とす
る半導体装置にある。According to the invention, there is provided the semiconductor device, wherein the connection of the negative electrode to the corresponding wiring member is a solder joint.

【００１３】また本発明によれば、前記半導体スイッチ
ング素子はＩＧＢＴ又はＩＥＧＴ素子であることを特徴
とする半導体装置にある。According to the present invention, there is provided a semiconductor device, wherein the semiconductor switching element is an IGBT or IEGT element.

【００１４】また本発明によれば、前記配線基板はセラ
ミック基板上に金属導体を形成したものであることを特
徴とする半導体装置にある。Further, according to the present invention, in the semiconductor device, the wiring substrate is formed by forming a metal conductor on a ceramic substrate.

【００１５】また本発明によれば、前記配線基板は前記
半導体スイッチング素子が接合している面の反対側の面
にヒートシンクがはんだ接合されていることを特徴とす
る半導体装置にある。According to the present invention, there is provided the semiconductor device, wherein the wiring board has a heat sink soldered to a surface opposite to a surface to which the semiconductor switching element is bonded.

【００１６】また本発明によれば、前記配線基板は金属
ベース上に絶縁層を形成し、この絶縁層の上に金属導体
を形成したものであることを特徴とする半導体装置にあ
る。また本発明によれば、前記正極電極、負極電極及び
制御電極は各電極の全部又は一部の表面上に緩衝板を設
けたことを特徴とする半導体装置にある。According to the present invention, there is provided the semiconductor device, wherein the wiring board is formed by forming an insulating layer on a metal base and forming a metal conductor on the insulating layer. Further, according to the present invention, there is provided the semiconductor device, wherein the positive electrode, the negative electrode, and the control electrode are provided with a buffer plate on the entire or partial surface of each electrode.

【００１７】また本発明によれば、半導体能動領域の一
方の表面に外部露出面を有する正極電極と制御電極とが
形成され、かつ、前記半導体能動素子の他方の表面に外
部露出面を有する負極電極が形成された半導体スイッチ
ング素子を有する半導体装置の製造方法において、前記
正極電極と前記制御電極とを前記配線基板と所定の位置
関係で対向させる位置合せ工程と、この位置合せ工程の
後に前記正極電極と制御電極を前記配線基板の所定位置
にはんだ接合する接合工程と、前記負極電極を所定の配
線材の所定位置に位置合せする第２の位置合せ工程と、
この第２の位置合せ工程の後に負極電極を配線層の所定
位置にはんだ接合する第２の接合工程とを有することを
特徴とする半導体装置の製造方法のある。According to the present invention, a positive electrode having an externally exposed surface on one surface of a semiconductor active region and a control electrode are formed, and a negative electrode having an externally exposed surface on the other surface of the semiconductor active element. A method of manufacturing a semiconductor device having a semiconductor switching element having electrodes formed therein, wherein: a positioning step in which the positive electrode and the control electrode face the wiring substrate in a predetermined positional relationship; and A joining step of soldering the electrode and the control electrode to a predetermined position of the wiring board, and a second positioning step of positioning the negative electrode to a predetermined position of a predetermined wiring member;
A second bonding step of soldering the negative electrode to a predetermined position of the wiring layer after the second alignment step.

【００１８】また本発明によれば、前記接合工程は前記
正極電極と制御電極とを同時にはんだ接合により前記配
線基板に接合することを特徴とする半導体装置の製造方
法にある。Further, according to the present invention, in the method of manufacturing a semiconductor device, the bonding step includes bonding the positive electrode and the control electrode to the wiring substrate by solder bonding at the same time.

【００１９】また本発明によれば、前記位置合せ工程を
行う際に、事前に前記正極電極、負極電極及び制御電極
のそれぞれの電極の全部又は一部の仮付けはんだ層内に
は緩衝材が設けられていることを特徴とする半導体装置
の製造方法にある。Further, according to the present invention, when performing the alignment step, a buffer material is previously contained in all or a part of the temporary solder layer of each of the positive electrode, the negative electrode and the control electrode. A method for manufacturing a semiconductor device, comprising:

【００２０】また本発明によれば、前記位置合せ工程を
行う際に、事前に前記正極電極、負極電極及び制御電極
のそれぞれの電極の全部又は一部の表面上には緩衝材が
設けられていることを特徴とする半導体装置の製造方法
にある。According to the present invention, when performing the alignment step, a buffer material is provided on all or a part of the surface of each of the positive electrode, the negative electrode, and the control electrode in advance. A method for manufacturing a semiconductor device.

【００２１】[0021]

【発明の実施の形態】本発明の実施の形態について、図
１、図２および図３を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

【００２２】（実施の形態１）図１は本発明に関する半
導体装置の第１の実施の形態を示す断面図である。半導
体スイッチング素子の一つであるＩＧＢＴ１は、表面に
正極電極であるエミッタ電極２が配線基板である銅張り
セラミック基板３の表面の銅パターン４a の所定位置に
はんだ層５によってはんだ接合されている。。また、そ
の表面の端部には制御電極であるゲート電極６が設けら
れ、同様に銅張りセラミック基板３の所定位置にはんだ
層５によってはんだ接合されている。。また、銅張りセ
ラミック基板３の裏面側には裏面の銅パターン4 b を介
してヒートシンク７がはんだ層５によってはんだ接合さ
れている。このヒートシンク７の周囲には図示しないプ
ラスチック製の外囲器が設けられ、ＩＧＢＴ１や銅張り
セラミック基板３の表面は絶縁のためシリコンゲル等で
封止されている。(First Embodiment) FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. The IGBT 1 which is one of the semiconductor switching elements has an emitter electrode 2 which is a positive electrode on the surface and is soldered to a predetermined position of a copper pattern 4a on the surface of a copper-clad ceramic substrate 3 which is a wiring board by a solder layer 5. . A gate electrode 6 serving as a control electrode is provided at an end of the surface, and is similarly solder-bonded to a predetermined position of the copper-clad ceramic substrate 3 by a solder layer 5. . A heat sink 7 is solder-bonded to the back surface of the copper-clad ceramic substrate 3 by a solder layer 5 via a copper pattern 4 b on the back surface. A plastic envelope (not shown) is provided around the heat sink 7, and the surfaces of the IGBT 1 and the copper-clad ceramic substrate 3 are sealed with silicon gel or the like for insulation.

【００２３】ＩＧＢＴ１の裏面には負極電極のコレクタ
電極９が所定の対向位置（半導体装置として表面側に位
置）に配設された配線材１０にはんだ層５を介してはん
だ接合されている。On the back surface of the IGBT 1, a collector electrode 9 as a negative electrode is soldered via a solder layer 5 to a wiring member 10 disposed at a predetermined facing position (position on the front surface side as a semiconductor device).

【００２４】なお、配線基板は半導体素子で発生した熱
を放熱するために放熱特性の優れたものが好ましいく、
アルミ・インバー・鉄等の金属ベース上にエポシキ・ポ
リブタジエン・ポリイミド等の絶縁層を形成し、その上
に銅箔等で配線パターンを形成したいわゆるメタルコア
基板である。特に、アルミナ・窒化アルミナ等のセラミ
ック材料をベースとして、表面に銅・アルミ等の金属に
よる配線を形成した基板が好適で、中でも、絶縁耐圧が
要求される分野では、アルミナ・窒化アルミ等に銅箔を
直接貼り付けた銅張りセラミック基板３が好適である。It is preferable that the wiring board has excellent heat radiation characteristics in order to radiate heat generated in the semiconductor element.
This is a so-called metal core substrate in which an insulating layer made of epoxy, polybutadiene, polyimide, or the like is formed on a metal base such as aluminum, invar, or iron, and a wiring pattern is formed thereon using a copper foil or the like. In particular, a substrate formed of a ceramic material such as alumina or alumina nitride and having a wiring formed of metal such as copper or aluminum on the surface is preferable. In particular, in a field where dielectric strength is required, copper is used instead of alumina or aluminum nitride. A copper-clad ceramic substrate 3 to which a foil is directly adhered is preferable.

【００２５】また、ＩＧＢＴ１の表面及び裏面の各電極
２、６、９は、はんだ接合が可能なようにメタライズ処
理されている。メタライズ処理はアルミ電極上にチタン
・白金・金やチタン・パラジウム・金等の金属を表面に
設ける方法や、ニッケル等の金属で被覆する方法のいず
れでも可能である。The electrodes 2, 6, and 9 on the front and back surfaces of the IGBT 1 are metallized so as to enable solder bonding. The metallizing treatment can be performed by a method of providing a metal such as titanium, platinum or gold or titanium, palladium or gold on the surface of the aluminum electrode, or a method of coating with a metal such as nickel.

【００２６】また、はんだ接合部は各種のはんだ材料を
使用することが可能であるが、はんだ接合部は高い熱ス
トレスに晒されることから、耐熱ストレス性を有するは
んだ材料が好適である。複数のはんだ接合部が存在する
場合には、これらを順次はんだ付けしてもよくまた一括
してはんだ付けしてもよい。Although various solder materials can be used for the solder joint, since the solder joint is exposed to high thermal stress, a solder material having heat stress resistance is preferable. If there are a plurality of solder joints, these may be soldered sequentially or collectively.

【００２７】また、ヒートシンク７は銅の表面にニッケ
ルめっきを施したものが用いられている。The heat sink 7 has a copper surface plated with nickel.

【００２８】これらの構造により、ＩＧＢＴ１で発生す
る熱は各電極２、６、９からはんだ接合したはんだ層５
を介してヒートシンク７や配線材１０に広い接触面積で
伝熱されるため良好な熱放散が行われる。With these structures, the heat generated in the IGBT 1 is reduced by the solder layer 5 soldered from the electrodes 2, 6 and 9.
, Heat is transmitted to the heat sink 7 and the wiring member 10 with a large contact area through the heat sink, so that good heat dissipation is performed.

【００２９】また、ゲート電極６を銅張りセラミック基
板３の上の銅パターン４a にワイヤを使わずに直接はん
だ接合したため、従来の実装方法で問題となっていたゲ
ート電極６への配線の制約を解消出来たと共に、半導体
装置内部での半導体スイッチング素子の配置に関する自
由度を増すことが可能となった。Further, since the gate electrode 6 is directly solder-bonded to the copper pattern 4a on the copper-clad ceramic substrate 3 without using a wire, restrictions on wiring to the gate electrode 6, which has been a problem in the conventional mounting method, are reduced. As a result, the degree of freedom regarding the arrangement of the semiconductor switching elements inside the semiconductor device can be increased.

【００３０】また、エミッタ電極２とコレクタ電極９の
ほぼ全面がはんだ接合による配線であるため、電流容量
に余裕のある配線を行うことも可能である。絶縁耐圧面
でもエミッタ電極２とコレクタ電極９が半導体スイッチ
ング素子の両面に振り分けられているので、数百Ｖから
数千Ｖの耐圧要求にも十分応えられる。Further, since almost the entire surfaces of the emitter electrode 2 and the collector electrode 9 are wirings formed by soldering, it is possible to perform wirings having a sufficient current capacity. Since the emitter electrode 2 and the collector electrode 9 are distributed on both surfaces of the semiconductor switching element also on the dielectric withstand voltage surface, it can sufficiently meet the withstand voltage requirement of several hundred V to several thousand V.

【００３１】なお、ゲート電極６とエミッタ電極２はＩ
ＧＢＴ素子の特性上両者間の電圧差は数十Ｖであるため
近接して配置しても実際上の障害は発生しない。The gate electrode 6 and the emitter electrode 2 are I
Since the voltage difference between the two is several tens of volts due to the characteristics of the GBT element, no practical obstacle occurs even if they are arranged close to each other.

【００３２】次にこれらの構造の製造方法について説明
すると、実装装置であるダイマウンターの所定位置に銅
張りセラミック基板３をセットし、ＩＧＢＴ１を保持し
たヘッドが所定位置に降下してエミッタ電極２とゲート
電極６とを銅張りセラミック基板３の所定位置にダイマ
ウンティングを行う。このダイマウンティングは窒素雰
囲気中でフラックスレス半田を用いてスクラブマウント
を行う。はんだはシートはんだでも滴下によるはんだ供
給でもよい。次の工程でＩＧＢＴ１のコレクタ電極を所
定の配線材１０にはんだ接合する。その後、ヒートシン
ク７を銅張りセラミック基板３の裏面にはんだ接合す
る。これらのはんだ接合はそれぞれ仮付けしておきリフ
ロー炉で同時にはんだ付けを行う。Next, a method of manufacturing these structures will be described. A copper-clad ceramic substrate 3 is set at a predetermined position of a die mounter, which is a mounting device, and a head holding the IGBT 1 is lowered to a predetermined position, and the emitter electrode 2 is connected to the substrate. Die mounting is performed on the gate electrode 6 at a predetermined position on the copper-clad ceramic substrate 3. In this die mounting, scrub mounting is performed using fluxless solder in a nitrogen atmosphere. The solder may be sheet solder or solder supplied by dropping. In the next step, the collector electrode of the IGBT 1 is soldered to a predetermined wiring member 10. Thereafter, the heat sink 7 is soldered to the back surface of the copper-clad ceramic substrate 3. These solder joints are temporarily attached, and are simultaneously soldered in a reflow furnace.

【００３３】なお、これらのはんだ付はリフロー炉で同
時に行わず順次それぞれの個所を行ってもよい。It is to be noted that these soldering operations may be sequentially performed at respective locations instead of simultaneously performed in a reflow furnace.

【００３４】（実施の形態２）図２は、本発明の第２の
実施の形態を示す断面図である。半導体スイッチング素
子の一つであるＩＥＧＴ１１は、表面に正極電極である
エミッタ電極２が銅張りセラミック基板３の表面の銅パ
ターン４a の所定位置にはんだ接合されはんだ層５を形
成している。このはんだ層５の中には熱応力を緩和する
ための緩衝板１２が挿入されている。緩衝板１２はＩＥ
ＧＴ１１に応力を加えないためにＩＥＧＴ１１の基材で
あるシリコンと熱膨張率の近い材料が好ましく、モリブ
テン、タングステン等の単体金属や銅−タングステン、
４２アロイ等の合金や銅−インバー−銅等のクラッド材
を用いる。(Embodiment 2) FIG. 2 is a sectional view showing a second embodiment of the present invention. In the IEGT 11 which is one of the semiconductor switching elements, the emitter electrode 2 which is a positive electrode on the surface is soldered to a predetermined position of the copper pattern 4 a on the surface of the copper-clad ceramic substrate 3 to form a solder layer 5. A buffer plate 12 for relaxing thermal stress is inserted into the solder layer 5. The buffer plate 12 is IE
In order not to apply a stress to GT11, a material having a coefficient of thermal expansion close to that of silicon as a base material of IEGT11 is preferable, and a single metal such as molybdenum or tungsten, copper-tungsten,
An alloy such as 42 alloy or a clad material such as copper-invar-copper is used.

【００３５】また、ＩＥＧＴ１１表面の端部には制御電
極であるゲート電極６が設けられ、同様に銅張りセラミ
ック基板３の所定位置にはんだ層５ではんだ接合されて
いる。このはんだ層５も同様に緩衝板１２が挿入されて
いる。また、銅張りセラミック基板３の裏面側にも表面
の銅パターン４b を介してヒートシンク７がはんだ層５
によってはんだ接合されている。このヒートシンク７の
周囲には図示しないプラスチック製の外囲器が設けら
れ、ＩＥＧＴ１１や銅張りセラミック基板３の表面は絶
縁のためシリコンゲル等で封止されている。A gate electrode 6 serving as a control electrode is provided at an end of the surface of the IEGT 11, and is similarly soldered to a predetermined position of the copper-clad ceramic substrate 3 with a solder layer 5. The buffer layer 12 is similarly inserted into the solder layer 5. The heat sink 7 is also connected to the solder layer 5 on the back side of the copper-clad ceramic substrate 3 via the copper pattern 4b on the front side.
Soldered. A plastic envelope (not shown) is provided around the heat sink 7, and the surfaces of the IEGT 11 and the copper-clad ceramic substrate 3 are sealed with silicon gel or the like for insulation.

【００３６】ＩＥＧＴ１１の裏面には負極電極のコレク
タ電極９が（半導体装置として表面側に位置）対向位置
に配設された所定の配線材１０にはんだ層５を介しては
んだ接合されている。このはんだ層５にもエミッタ電極
２等と同様に緩衝板１２が挿入されている。On the back surface of the IEGT 11, a collector electrode 9 as a negative electrode is soldered to a predetermined wiring member 10 disposed at a facing position (located on the front side as a semiconductor device) via a solder layer 5. The buffer plate 12 is inserted into the solder layer 5 as well as the emitter electrode 2 and the like.

【００３７】なお、各緩衝板１２はそれぞれはんだ層５
の中に挿入されているが、はんだで接合される部材のい
ずれかに接合してもよい。Each buffer plate 12 has a solder layer 5
, But may be joined to any of the members joined by solder.

【００３８】また、配線基板は半導体素子で発生した熱
を放熱するために放熱特性の優れたものが好ましいく、
アルミ・インバー・鉄等の金属ベース上にエポシキ・ポ
リブタジエン・ポリイミド等の絶縁層を形成し、その上
に銅箔等で配線パターンを形成したいわゆるメタルコア
基板である。特に、アルミナ・窒化アルミナ等のセラミ
ック材料をベースとして、表面に銅・アルミ等の金属に
よる配線を形成した基板が好適で、中でも、絶縁耐圧が
要求される分野では、アルミナ・窒化アルミ等に銅箔を
直接貼り付けた銅張りセラミック基板３が好適である。Further, it is preferable that the wiring board has excellent heat radiation characteristics in order to radiate heat generated in the semiconductor element.
This is a so-called metal core substrate in which an insulating layer made of epoxy, polybutadiene, polyimide, or the like is formed on a metal base such as aluminum, invar, or iron, and a wiring pattern is formed thereon using a copper foil or the like. In particular, a substrate formed of a ceramic material such as alumina or alumina nitride and having a wiring formed of metal such as copper or aluminum on the surface is preferable. In particular, in a field where dielectric strength is required, copper is used instead of alumina or aluminum nitride. A copper-clad ceramic substrate 3 to which a foil is directly adhered is preferable.

【００３９】また、ＩＥＧＴ１１の表面及び裏面の各電
極２、６、９は、はんだ接合が可能なようにメタライズ
処理されている。メタライズ処理はアルミ電極上にチタ
ン・白金・金やチタン・パラジウム・金等の金属を表面
に設ける方法や、ニッケル等の金属で被覆する方法のい
ずれでも選択可能である。The electrodes 2, 6, and 9 on the front and back surfaces of the IEGT 11 are metallized so that solder bonding is possible. The metallizing treatment can be selected by a method of providing a metal such as titanium, platinum, gold or titanium, palladium, or gold on the surface of the aluminum electrode, or a method of coating with a metal such as nickel.

【００４０】また、はんだ接合部は各種のはんだ材料を
使用することが可能であるが、はんだ接合部は高い熱ス
トレスに晒されることから、耐熱ストレス性を有するは
んだ材料が好適である。複数のはんだ接合部が存在する
場合には、これらを順次はんだ付けしてもよくまた一括
してはんだ付けしてもよい。Although various solder materials can be used for the solder joint, since the solder joint is exposed to high thermal stress, a solder material having heat resistance is preferable. If there are a plurality of solder joints, these may be soldered sequentially or collectively.

【００４１】これらの構造により、ＩＥＧＴ１１で発生
する熱応力は各電極２、６、９からはんだ接合を介して
はんだ層５内に挿入されている緩衝板１２で緩和される
ため、ＩＥＧＴ１１やはんだの疲労を押さえることが出
来るため、各端子の接合寿命が伸びかつ信頼性も向上す
る。また電気絶縁上の耐圧についても、ＩＥＧＴ１１の
厚さ方向に緩衝板の厚さが加わるので、エミッタ電極２
とコレクタ電極９間の分離、絶縁は一層拡大する。With these structures, the thermal stress generated in the IEGT 11 is relieved by the buffer plate 12 inserted into the solder layer 5 from each of the electrodes 2, 6, 9 via the solder joint. Since fatigue can be suppressed, the joining life of each terminal is extended and the reliability is improved. Also, regarding the withstand voltage on the electrical insulation, since the thickness of the buffer plate is added in the thickness direction of the IEGT 11, the emitter electrode 2
The isolation and insulation between the electrode and the collector electrode 9 are further expanded.

【００４２】また、実施の形態１で述べたように、ヒー
トシンク７や配線材１０に広い接触面積で伝熱されるた
め良好な熱放散が行われる。Further, as described in the first embodiment, since heat is transferred to the heat sink 7 and the wiring member 10 with a large contact area, good heat dissipation is performed.

【００４３】次にこれらの構造の製造方法について説明
すると、実装装置であるダイマウンターの所定位置に銅
張りセラミック基板３をセットし、ＩＥＧＴ１１を保持
したヘッドが所定位置に降下してエミッタ電極２とゲー
ト電極６とを銅張りセラミック基板３の所定位置にダイ
マウンティングを行う。その際、緩衝板１２は予めエミ
ッタ電極２とゲート電極６にそれぞれ仮付けしてあるの
でダイマウンティングによってはんだ層５の中に挿入固
定される。このダイマウンティングは窒素雰囲気中でフ
ラックスレス半田を用いてスクラブマウントを行う。従
って、はんだ接合時に仮に気泡が発生しても除去されて
良好なはんだ接合が得られる。その際のはんだはシート
はんだでも滴下によるはんだ供給でもよい。Next, a method of manufacturing these structures will be described. A copper-clad ceramic substrate 3 is set at a predetermined position of a die mounter, which is a mounting device, and a head holding the IEGT 11 descends to a predetermined position, and the emitter electrode 2 Die mounting is performed on the gate electrode 6 at a predetermined position on the copper-clad ceramic substrate 3. At this time, since the buffer plate 12 is temporarily attached to the emitter electrode 2 and the gate electrode 6 in advance, the buffer plate 12 is inserted and fixed in the solder layer 5 by die mounting. In this die mounting, scrub mounting is performed using fluxless solder in a nitrogen atmosphere. Therefore, even if bubbles are generated at the time of soldering, they are removed and good soldering is obtained. The solder at that time may be sheet solder or solder supply by dropping.

【００４４】次にＩＥＧＴ１１のコレクタ電極を所定の
配線材１０にはんだ接合する。この際も、緩衝板１２は
予めコレクタ電極に仮付けされてあるのでダイマウンテ
ィングによってはんだ層５の中に挿入固定される。その
後、ヒートシンク７を銅張りセラミック基板３の裏面に
はんだ接合する。これらのはんだ接合はそれぞれ仮付け
しておきリフロー炉で同時にはんだ付けを行う。Next, the collector electrode of the IEGT 11 is soldered to a predetermined wiring member 10. Also at this time, since the buffer plate 12 is temporarily attached to the collector electrode in advance, it is inserted and fixed in the solder layer 5 by die mounting. Thereafter, the heat sink 7 is soldered to the back surface of the copper-clad ceramic substrate 3. These solder joints are temporarily attached, and are simultaneously soldered in a reflow furnace.

【００４５】なお、緩衝板１２の仮付け位置ははんだ層
の内部でなくて、はんだ層の両側のいずれかに密接して
配置してもよい。Note that the temporary attachment position of the buffer plate 12 may be arranged closely on either side of the solder layer, not inside the solder layer.

【００４６】なお、これらのはんだ付はリフロー炉で同
時に行わず順次それぞれの個所を行ってもよい。It should be noted that these soldering steps may be performed sequentially at respective locations instead of being performed simultaneously in a reflow furnace.

【００４７】図３は半導体スイッチング素子の斜視図
で、素子の大きさは□２０ｍｍ程度である。FIG. 3 is a perspective view of a semiconductor switching element, and the size of the element is about 20 mm.

【００４８】[0048]

【発明の効果】以上に述べたように本発明は、半導体ス
イッチング素子の表裏を逆にし、各電極をはんだ接合す
ることにより半導体スイッチング素子内で発生する熱を
効率よくヒートシンク７等へ伝熱することができるの
で、半導体スイッチング素子の熱による障害を大幅に軽
減することが可能になった。As described above, according to the present invention, the heat generated in the semiconductor switching element is efficiently transferred to the heat sink 7 or the like by inverting the semiconductor switching element and soldering each electrode. As a result, it is possible to greatly reduce the trouble of the semiconductor switching element due to heat.

【００４９】また、配線基板とゲート電極の接続を、エ
ミッタ電極と配線基板との接合工程と同時に行うことに
より工程に短縮が可能となった。Further, the connection between the wiring substrate and the gate electrode is performed simultaneously with the step of joining the emitter electrode and the wiring substrate, thereby making it possible to reduce the number of steps.

【００５０】また、半導体スイッチング素子の表面にゲ
ート電極が存在しないため、半導体スイッチング素子の
表面に配置しているコレクタ電極の配線は、配線インダ
クタンスが低い平板配線が行えるようになり、かつ、平
板配線による半導体スイッチング素子の放熱が可能とな
った。Further, since the gate electrode does not exist on the surface of the semiconductor switching element, the wiring of the collector electrode disposed on the surface of the semiconductor switching element can be formed by a flat wiring with a low wiring inductance. The heat dissipation of the semiconductor switching element by the above was made possible.

【００５１】また、各電極をはんだ接合するはんだ層内
に緩衝板１２を設けたので、半導体スイッチング素子の
発熱による熱応力は緩和され、各はんだ接合部のはんだ
疲労を抑止することが出来るようになった。Further, since the buffer plate 12 is provided in the solder layer for solder-joining the respective electrodes, the thermal stress caused by the heat generated by the semiconductor switching element is alleviated, and the solder fatigue of each solder-joined portion can be suppressed. became.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置を基板に実装した一実施例
を示す断面図。FIG. 1 is a cross-sectional view showing one embodiment in which a semiconductor device of the present invention is mounted on a substrate.

【図２】本発明の半導体装置を基板に実装した他の実施
例を示す断面図。FIG. 2 is a sectional view showing another embodiment in which the semiconductor device of the present invention is mounted on a substrate.

【図３】本発明の半導体装置を基板に実装した一実施例
を示す斜視図。FIG. 3 is a perspective view showing one embodiment in which the semiconductor device of the present invention is mounted on a substrate.

【図４】従来の半導体装置を基板に実装した例を示す断
面図。FIG. 4 is a cross-sectional view illustrating an example in which a conventional semiconductor device is mounted on a substrate.

【符号の説明】[Explanation of symbols]

１…ＩＧＢＴ ２…エミッタ電極 ３…銅張りセラミック基板 ４a 、４b …銅パターン ５…はんだ層 ６…ゲート電極 ７…ヒートシンク ９…コレクタ電極 １０…配線材 １１…ＩＥＧＴ １２…緩衝板 １５…アルミ線 DESCRIPTION OF SYMBOLS 1 ... IGBT 2 ... Emitter electrode 3 ... Copper-clad ceramic substrate 4a, 4b ... Copper pattern 5 ... Solder layer 6 ... Gate electrode 7 ... Heat sink 9 ... Collector electrode 10 ... Wiring material 11 ... IEGT 12 ... Buffer plate 15 ... Aluminum wire

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 半導体能動領域の一方の表面に外部露出
面を有する正極電極と制御電極とが形成され、かつ、前
記半導体能動素子の他方の表面に外部露出面を有する負
極電極が形成された半導体スイッチング素子と、 この半導体スイッチング素子の前記正極電極と前記制御
電極を所定位置で各々はんだ接合した配線基板とを有す
ることを特徴とする半導体装置。A positive electrode having an externally exposed surface and a control electrode are formed on one surface of a semiconductor active region, and a negative electrode having an externally exposed surface is formed on the other surface of the semiconductor active element. A semiconductor device comprising: a semiconductor switching element; and a wiring board in which the positive electrode and the control electrode of the semiconductor switching element are soldered at predetermined positions. 【請求項２】 前記負極電極は対応する配線材との接続
がはんだ接合であることを特徴とする請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein said negative electrode is connected to a corresponding wiring member by solder bonding. 【請求項３】 前記半導体スイッチング素子はＩＧＢＴ
又はＩＥＧＴ素子であることを特徴とする請求項１記載
の半導体装置。3. The semiconductor switching device is an IGBT.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an IEGT element. 【請求項４】 前記配線基板はセラミック基板上に金属
導体を形成したものであることを特徴とする請求項１記
載の半導体装置。4. The semiconductor device according to claim 1, wherein said wiring substrate is formed by forming a metal conductor on a ceramic substrate. 【請求項５】 前記配線基板は前記半導体スイッチング
素子が接合している面の反対側の面にヒートシンクがは
んだ接合されていることを特徴とする請求項１記載の半
導体装置。5. The semiconductor device according to claim 1, wherein a heat sink is soldered to a surface of the wiring board opposite to a surface to which the semiconductor switching element is bonded. 【請求項６】 前記配線基板は金属ベース上に絶縁層を
形成し、この絶縁層の上に金属導体を形成したものであ
ることを特徴とする請求項１記載の半導体装置。6. The semiconductor device according to claim 1, wherein the wiring board has an insulating layer formed on a metal base, and a metal conductor formed on the insulating layer. 【請求項７】 前記正極電極、負極電極及び制御電極は
各電極の全部又は一部の表面上に緩衝板を設けたことを
特徴とする請求項１記載の半導体装置。7. The semiconductor device according to claim 1, wherein the positive electrode, the negative electrode, and the control electrode are provided with a buffer plate on all or a part of the surface of each electrode. 【請求項８】 半導体能動領域の一方の表面に外部露出
面を有する正極電極と制御電極とが形成され、かつ、前
記半導体能動素子の他方の表面に外部露出面を有する負
極電極が形成された半導体スイッチング素子を有する半
導体装置の製造方法において、前記正極電極と前記制御
電極とを前記配線基板と所定の位置関係で対向させる位
置合せ工程と、 この位置合せ工程の後に前記正極電極と制御電極を前記
配線基板の所定位置にはんだ接合する接合工程と、 前記負極電極を所定の配線材の所定位置に位置合せする
第２の位置合せ工程と、この第２の位置合せ工程の後に
負極電極を配線層の所定位置にはんだ接合する第２の接
合工程とを有することを特徴とする半導体装置の製造方
法。8. A positive electrode having an externally exposed surface and a control electrode are formed on one surface of the semiconductor active region, and a negative electrode having an externally exposed surface is formed on the other surface of the semiconductor active element. A method of manufacturing a semiconductor device having a semiconductor switching element, wherein: a positioning step of causing the positive electrode and the control electrode to face the wiring substrate in a predetermined positional relationship; A bonding step of solder bonding to a predetermined position of the wiring board; a second positioning step of positioning the negative electrode to a predetermined position of a predetermined wiring member; and wiring of the negative electrode after the second positioning step. A second joining step of solder joining at a predetermined position of the layer. 【請求項９】 前記接合工程は前記正極電極と制御電極
とを同時にはんだ接合により前記配線基板に接合するこ
とを特徴とする請求項８記載の半導体装置の製造方法。9. The method according to claim 8, wherein in the bonding step, the positive electrode and the control electrode are simultaneously bonded to the wiring board by solder bonding. 【請求項１０】 前記位置合せ工程を行う際に、事前に
前記正極電極、負極電極及び制御電極のそれぞれの電極
の全部又は一部の仮付けはんだ層内には緩衝材が設けら
れていることを特徴とする請求項８記載の半導体装置の
製造方法。10. A buffer material is provided in a temporary solder layer of all or a part of each of the positive electrode, the negative electrode, and the control electrode before performing the alignment step. 9. The method for manufacturing a semiconductor device according to claim 8, wherein: 【請求項１１】 前記位置合せ工程を行う際に、事前に
前記正極電極、負極電極及び制御電極のそれぞれの電極
の全部又は一部の表面上には緩衝材が設けられているこ
とを特徴とする請求項８記載の半導体装置の製造方法。11. The method according to claim 1, wherein a buffer material is provided on all or a part of the surface of each of the positive electrode, the negative electrode, and the control electrode before performing the positioning step. The method for manufacturing a semiconductor device according to claim 8.
JP9324424A 1997-11-26 1997-11-26 Semiconductor device and its manufacture Pending JPH11163045A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP9324424A JPH11163045A (en) 1997-11-26 1997-11-26 Semiconductor device and its manufacture
AU94105/98A AU705177B1 (en) 1997-11-26 1998-11-24 Semiconductor device
US09/199,780 US6255672B1 (en) 1997-11-26 1998-11-25 Semiconductor device
KR1019980050906A KR100284241B1 (en) 1997-11-26 1998-11-26 Semiconductor device
EP98122182A EP0923131A3 (en) 1997-11-26 1998-11-26 Semiconductor assembly
CNB981258913A CN1146994C (en) 1997-11-26 1998-11-26 Semiconductor device

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JP9324424A JPH11163045A (en) 1997-11-26 1997-11-26 Semiconductor device and its manufacture

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US6885096B2 (en) 2000-07-11 2005-04-26 Kabushiki Kaisha Toshiba Semiconductor device having at least three power terminals superposed on each other
WO2005071733A1 (en) * 2004-01-26 2005-08-04 Hitachi, Ltd. Semiconductor device, power converter employing it, motor employing it, hybrid automobile employing it, and motor drive system employing it
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