JP2000049280A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JP2000049280A
JP2000049280A JP21704898A JP21704898A JP2000049280A JP 2000049280 A JP2000049280 A JP 2000049280A JP 21704898 A JP21704898 A JP 21704898A JP 21704898 A JP21704898 A JP 21704898A JP 2000049280 A JP2000049280 A JP 2000049280A
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Japan
Prior art keywords
electrode
semiconductor device
solder
conductor
wiring board
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Pending
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JP21704898A
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Japanese (ja)
Inventor
Yasuto Saito
Shinpei Yoshioka
心平 吉岡
康人 斉藤
Original Assignee
Toshiba Ave Kk
Toshiba Corp
東芝エー・ブイ・イー株式会社
株式会社東芝
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Application filed by Toshiba Ave Kk, Toshiba Corp, 東芝エー・ブイ・イー株式会社, 株式会社東芝 filed Critical Toshiba Ave Kk
Priority to JP21704898A priority Critical patent/JP2000049280A/en
Publication of JP2000049280A publication Critical patent/JP2000049280A/en
Application status is Pending legal-status Critical

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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/4005Shape
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    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/45124Aluminium (Al) as principal constituent
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    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/838Bonding techniques
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    • H01L2224/848Bonding techniques
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
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    • H01L2924/1305Bipolar Junction Transistor [BJT]
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    • H01L2924/1305Bipolar Junction Transistor [BJT]
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a switching element and manufacture thereof, which has bond zones having reduced wiring inductances and reduced thermal stresses, esp. in a mounting structure for thyristors, power transistors, etc., which are used in the power electronics. SOLUTION: In a wiring between a semiconductor switching element 1 and wiring board 2 on which it is mounted, at least one of connections of a positive electrode 4 or a control electrode 8 of the semiconductor switching element 1 or a load electrode 5 to the wiring board 2 is made by a conductor 7 composed of woven thin lead wires.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、スイッチング素子を有する半導体装置で、特にパワーエレクトロニクスの分野で使用されるサイリスタやパワートランジスタなどの実装構造で、配線インダクタンスが低く、かつ、熱応力を小さくした接合部を有する半導体装置とその製造方法に関する。 BACKGROUND OF THE INVENTION The present invention is a semiconductor device having a switching element, in particular in the mounting structure such as a thyristor and power transistor used in the field of power electronics, wiring inductance is low and has a small thermal stress a semiconductor device having a junction method for producing the same.

【0002】 [0002]

【従来の技術】近年、産業用ポンプやファン等のパワーエレクトロニクスの制御分野では、エネルギーの有効利用の観点からインバータ装置が注目されている。 In recent years, in the control field of power electronics industrial pumps, fans, etc., the inverter device from the viewpoint of effective use of energy has been attracting attention. インバータ装置の心臓部は電流をスイツチングする半導体素子である。 The heart of the inverter device is a semiconductor device for switching-current.

【0003】半導体スィッチング素子としては従来からサイリスタ、パワー・トランジスタなどが知られており、最近ではGTO(ゲート・ターン・オフ・サイリスタ)やIGBT(インシユレーテツド・ゲート・バイポーラ・トランジスタ)などが広く使用されている。 [0003] The semiconductor Suitchingu thyristor from the past as an element, a power transistor, etc. have been known, and in recent years GTO (gate turn-off thyristor) or IGBT (in Shiyu Rete each time-gate bipolar transistor) widely used.

【0004】半導体スイッチング素子は種類により呼び方は異なるものの、いずれも正極(エミッタ)電極、負極(コレクタ)電極と制御極(ゲート)電極の3端子で構成され、制御極への電圧、電流を制御することにより正極と負極間の導通の制御を行なつている。 [0004] Although the semiconductor switching element is how call the type varies, both positive (emitter) electrode, is composed of three terminals of an anode (collector) electrode and a control electrode (gate) electrode, the voltage to the control electrode, the current and controlling the conduction between the positive electrode and the negative electrode line summer by controlling. これらの素子をパッケージ内に実装する場合には、正極、負極には大電流が通電されるため配線の電流容量を考慮すると共に、スイッチングにより著しく発熱するため放熱構造に留意した構造が採用されている。 When the implementation in these device package, the positive electrode, a negative electrode with consideration of the current capacity of wiring for a large current is energized, the structure noted heat dissipation structure to significantly heat by switching is employed there.

【0005】図5は、従来のバッケ一ジ内部での実装例を示す断面図である。 [0005] Figure 5 is a sectional view showing a mounting example of a conventional Bakke temporary internally. 半導体スイツチング素子の一種であるIGBT101は、裏面に設けられたコレクタ電極105がDBC基板(銅張りセラミツク基板)102の表面銅パターン103に半田104により接合されている。 A semiconductor switching-is a kind of element IGBT101 has a collector electrode 105 provided on the back surface is solder-bonded 104 to the DBC substrate surface copper pattern 103 (copper-clad ceramic substrate) 102. IGBT101の表面にはエミッタ電極110が設けられており、DBG基板102の表面銅パターン10 The surface of IGBT101 and emitter electrode 110 is provided, the surface copper pattern 10 of DBG substrate 102
6にアルミニウム線を用いたワイヤボンディング107 6 wire bonding 107 using aluminum line
により複数のワイヤで接続されている。 It is connected by a plurality of wires by.

【0006】また、IGBT101の表面にはゲート電極108が設けられて、DBC基板102の表面銅パターン109にアルミニウム線を用いたワイヤボンディング110により接続されている。 Further, the surface of the IGBT101 gate electrode 108 is provided and connected by wire bonding 110 using aluminum wire on the surface copper pattern 109 of DBC substrate 102. ゲート電極は大電流を流す必要がないため、通常1本のワイヤで構成されている。 Since the gate electrode is not necessary to flow a large current, and a normal single wire.

【0007】また、DBC基板102の裏面銅パターン111はヒートシンク112と半田113により接合されており、IGBT101で発生した熱は、半田10 Further, the back surface copper patterns 111 of the DBC substrate 102 is joined by the heat sink 112 and the solder 113, the heat generated in IGBT101 the solder 10
4、表面銅パターン103、セラミック層114、裏面銅パターン111、半田113を経てヒートシンク11 4, the surface copper pattern 103, the ceramic layer 114, back surface copper pattern 111, the heat sink 11 through the solder 113
2に達し外部に放熱される。 Is radiated to the outside reaches 2.

【0008】また、ここでは図示しないが、ヒートシンクの周囲にはプラスチック製の外囲器が設けられており、IGBT101やDBC基板102の表面は絶縁のためのシリコンゲル等で封止されている。 Further, although not shown here, the periphery of the heat sink is provided with an envelope made of plastic, the surface of IGBT101 and DBC substrate 102 is sealed with a silicone gel or the like for insulation.

【0009】なお、半導体スイッチング素子としてGT [0009] In addition, GT as a semiconductor switching element
Oを使用したの場合も、エミッタ電極をアノード電極、 In the case of using the O, anode electrode an emitter electrode,
コレクタ電極をカソード電極と読み替えることで、実装構造は同様である。 By replaced the collector electrode and the cathode electrode, the mounting structure is the same.

【0010】図6は、配線に銅製の平板を用いて、接合部を半田で接合したパッケージ内部の実装例を示す断面図である。 [0010] Figure 6, using a copper flat plate to the wiring, a cross-sectional view showing a mounting example of a package internal bonding the bonding portion with solder.

【0011】半導体スィッチング素子の一種であるIG [0011] The IG is a kind of semiconductor switching devices
BT151は、裏面に設けられたコレクタ電極150がDBC基板152の表面銅パターン153に半田154 BT151, the collector electrode 150 provided on the back surface of the solder in the surface copper pattern 153 of DBC substrate 152 154
により接合されている。 They are joined by. IGBT151の表面にはエミッタ電極155が設けられており、DBC基板152の表面銅パターン156と平板状の導体157により接続されている。 The surface of IGBT151 has emitter electrode 155 is provided and connected by a surface copper pattern 156 and the flat plate-shaped conductor 157 of DBC substrate 152.

【0012】また、IGBT151の表面にはゲート電極158が設けられており、DBC基板152の表面銅パターン153(紙面に垂直方向にあるため図示せず) Further, on the surface of the IGBT151 A gate electrode 158 is provided (not shown because it is in the vertical direction to the paper surface) surface copper pattern 153 of DBC substrate 152
に、同様に平板状の導体159(紙面に垂直方向に延長)により接続されている。 To, and is similarly connected to the plate-shaped conductor 159 (extending in direction perpendicular to the plane of the paper). ゲート電極は大電流を流す必要がないため、通常は細い導体1本で構成されている。 Since the gate electrode is not necessary to flow a large current, typically it is composed of thin conductors 1 present.

【0013】また、DBC基板152の裏面銅パターン161はヒートシンク162と半田163により接合されており、IGBT151で発生した熱は、半田15 Further, the back surface copper patterns 161 of the DBC substrate 152 is joined by the heat sink 162 and the solder 163, the heat generated in IGBT151 the solder 15
4、表面銅パターン153、セラミック層164、裏面銅パターン161、半田163を経てヒートシンク16 4, the surface copper pattern 153, the ceramic layer 164, back surface copper pattern 161, the heat sink 16 through the solder 163
2に達し、外部に放熱される。 2 reached, is radiated to the outside.

【0014】また、ここでは図示しないが、ヒートシンク162の周囲にはプラスチック製の外囲器があり、I Further, although not shown here, the periphery of the heat sink 162 has an envelope made of plastic, I
GBT161やDBC基板152の表面は絶縁のためのシリコンゲル等で封止されている。 Surface of GBT161 and DBC substrate 152 is sealed with a silicone gel or the like for insulation.

【0015】なお半導体スイッチング素子としてGT0 [0015] It should be noted that as the semiconductor switching element GT0
を使用したの場合も、エミッタ電極をアノード電極、コレクタ電極をカソード電極と読み替えることで、実装構造は同様である。 For was used also, by replaced the emitter electrode anode electrode, a collector electrode and the cathode electrode, the mounting structure is the same.

【0016】 [0016]

【発明が解決しようとする課題】以上述べた様に、図5 As mentioned above [0008], as shown in FIG. 5
で示した技術では、特に高負荷下で使用した場合、エミッタ電極のワイヤボンディング部が熱応力による疲労により破壊することが挙げられる。 In art shown in, especially when used under a high load, and that the wire bonding portion of the emitter electrode is destroyed by fatigue due to thermal stress.

【0017】その対策として、エミッタ電極についてもコレクタ電極と同様に半田接合とする方法が試みられている。 [0017] As a countermeasure, a method of similarly to the solder junction and the collector electrode also emitter electrode have been attempted. しかしながら、この方法では平板または棒状の電極によりコレクタ電極を構成しているが、接続プロセスを一元化するためゲート電極を同様の構造で構成すると、配線同士が相互に干渉する場合が生じたり、配線の引き回しによっては電極の製作が困難となる欠点が生じていた。 However, although constituting a collector electrode by a flat plate or bar-shaped electrode in this way, when made of the same structure of the gate electrode to centralize the connection process, wiring to each other or cause interfere with each other, the wiring disadvantage fabrication of electrodes becomes difficult to have occurred by lead.

【0018】また、図6に示した技術では、 平板または棒状の電極によりコレクタ電極を構成するが、電極の剛性が高いと、素子発熱時の熱応力が大きくなり、これによる疲労で素子や接合部などが破壊する欠点があった。 [0018] In the technique shown in FIG. 6, and constitute the collector electrode by a flat plate or rod-shaped electrodes, the rigidity of the electrode is high, the thermal stress at the time of device heating is increased, fatigue element and bonding by this part and there is a drawback to destroy.

【0019】本発明は、素子発熱時の熱応力で素子や接合部などが破壊することのない実装がなされたさ半導体装置とその製造方法を提供するものである。 [0019] The present invention like elements and joints in the thermal stress during device exotherm provide no implementation made the Is semiconductor device and a manufacturing method thereof be destroyed.

【0020】 [0020]

【課題を解決するための手段】請求項1の発明による手段によれば、一表面に正極電極と制御電極とが形成され他表面に負極電極が形成された半導体スイッチング素子と、金属導体が設けられ且つ前記半導体スイッチング素子が実装される配線基板とを具備し、この配線基板の、 Means for Solving the Problems] According to the measure according to the invention of claim 1, the semiconductor switching element anode electrodes are formed on the other surface formed with the positive electrode and the control electrode on one surface, provided with a metal conductor is and then and a wiring board on which the semiconductor switching elements are mounted, a wiring substrate,
金属導体と前記正極電極及び制御電極及び負極電極の少なくとも一つに対する電気的接続は、細導線を編み上げた導体により行われていることを特徴とする半導体装置にある。 Electrical connection to at least one metal conductor and the positive electrode and the control electrode and the negative electrode is a semiconductor device characterized in that it is made by conductors braided fine wires.

【0021】請求項2の発明による手段によれば、前記配線基板の金属導体と、前記細導線を編み上げた導体とは半田接合により接合されていることを特徴とする請求項1記載の半導体装置にある。 [0021] According to the measure according to the invention of claim 2, the semiconductor device of the metal conductor of the wiring board, according to claim 1, wherein the conductor braided said fine conductors, characterized in that it is joined by the joining solder It is in.

【0022】請求項3の発明による手段によれば、前記細導線を編み上げた導体と接続されている前記正極電極及び前記制御電極及び前記負極電極の少なくとも一つは半田接合により接合されていることを特徴とする請求項1記載の半導体装置にある。 [0022] According to the measure according to the invention of claim 3, that at least one is bonded by bonding the solder of said positive electrode and said control electrode and the negative electrode is connected to the conductor braided said fine wire the semiconductor device according to claim 1, wherein there.

【0023】請求項4の発明による手段によれば、前記半導体スイツチング素子がIGBT素子又はIEGT素子であることを特徴とする請求項1記載の半導体装置にある。 [0023] According to the measure according to the invention of claim 4, in the semiconductor device according to claim 1, wherein the semiconductor switching-device is an IGBT element or IEGT element.

【0024】請求項5の発明による手段によれば、前記配線基板がセラミック基板上に金属導体を形成したものであることを特徴とする請求項1記載の半導体装置にある。 According to the means according to the invention of claim 5, in the semiconductor device according to claim 1, wherein said wiring board is made by forming a metal conductor on a ceramic substrate.

【0025】請求項6の発明による手段によれば、前記配線基板は金属べース上に絶縁層を形成し、さらにその上に金属導体を形成したものであることを特徴とする請求項1記載の半導体装置にある。 [0025] According to the measure according to the invention of claim 6, claim 1, wherein said wiring board by forming an insulating layer on a metal base over scan, and characterized in that further forming a metal conductor thereon in the semiconductor device according.

【0026】請求項7の発明による手段によれば、前記細導線は銅製の線材を平帯状に編み上げたものであることを特徴とする請求項1記載の半導体装置にある。 [0026] According to the measure according to the invention of claim 7, wherein the fine wires are in the semiconductor device according to claim 1, wherein a is obtained braided copper wire in the flat belt.

【0027】請求項8の発明による手段によれば、前記細導線を平帯状に編み上げた導体の長手方向の弾性率が1GPa以下であることを特徴とする請求項7記載の半導体装置にある。 [0027] According to the measure according to the invention of claim 8, in the semiconductor device according to claim 7, wherein the longitudinal elastic modulus of conductors braided said fine wire into a flat strip is equal to or less than 1 GPa.

【0028】請求項9の発明による手段によれば、前記半導体スイッチング素子が複数個前記配線基板上設けられた際に、各半導体スイッチング素子間の配線の一部として細導線を編み上げた導体を使用したことを特徴とする半導体装置にある。 [0028] According to the measure according to the invention of claim 9, wherein when the semiconductor switching element is provided with a plurality said wiring board, using the conductors braided fine wires as part of the wiring between the semiconductor switching devices in a semiconductor device, characterized in that the.

【0029】請求項10の発明による手段によれば、一表面に正極電極と制御電極とが形成され且つ他裏面に負極電極が形成された半導体スイッチング素子と、金属導体が設けられ且つ前記半導体スイッチ素子が実装される配線基板とを具備する半導体装置の製造方法において、 [0029] According to the measure according to the invention of claim 10, the semiconductor switching element anode electrodes are formed on and another back surface and the positive electrode and the control electrode is formed on one surface, and the semiconductor switch metallic conductors are provided the method of manufacturing a semiconductor device including a wiring board device is mounted,
前記正極電極と前記制御電極とを前記配線基板の金属導体に対して半田接合するか、又は、前記負極電極を前記配線基板の金属導体に対して半田接合する第1の半田接合工程と、前記正極電極及び前記制御電極及び前記負極電極の少なくとも一つを一端が前記配線基板の金属導体に電気的に接続される細導線を編み上げた導体の他端に半田接合する第2の半田接合工程とを有することを特徴とする半導体装置の製造方法にある。 Or the said control electrode and the cathode electrode soldered to the metal conductors of the wiring board, or, a first solder bonding step of the solder joint of the negative electrode to the metal conductor of the wiring board, wherein a second solder bonding step of the solder joint to the other end of the positive electrode and the control electrode and the conductor at least one end of the negative electrode is braided electrically connected to thin wires to the metal conductors of the wiring substrate in a method of manufacturing a semiconductor device characterized by having a.

【0030】 [0030]

【発明の実施の形態】図1は本発明にかかる半導体装置の第1の実施の形態を示したものである。 Figure 1 DETAILED DESCRIPTION OF THE INVENTION shows a first embodiment of a semiconductor device according to the present invention. 半導体スイッチング素子の一種であるIGBT1は、裏面に設けられたコレクタ電極5がDBC基板2の表面銅パターン3に半田6により接合されている。 It is a kind of semiconductor switching element IGBT1 has a collector electrode 5 provided on the back surface are joined by solder 6 to the surface copper pattern 3 of the DBC substrate 2. IGBT1の表面にはエミッタ電極4が設けられており、DBC基板2の表面銅パターン3と銅製の細導線を平帯状に編み上げた導体7 The surface of IGBT1 and emitter electrode 4 are provided, the conductor braided surface copper pattern 3 and the copper fine wires of DBC substrate 2 flat belt 7
により接続されている。 They are connected by. この導体の長手方向の弾性率は、1GPa以下が好ましい。 Longitudinal elastic modulus of the conductor is preferably equal to or less than 1 GPa. またIGBT1の表面にはゲート電極8が設けられており、DBC基板2の表面銅パターン(紙面に垂直方向にあるため図示せず)に同様に平板状の導体9(紙面に垂直方向に延長)により接続されている。 Also on the surface of the IGBT1 and the gate electrode 8 is provided, DBC surface copper pattern of the substrate 2 (not shown because of the direction perpendicular to the plane of the paper) in the same manner as plate-shaped conductor 9 (extending in the direction perpendicular to the plane of the drawing) They are connected by.

【0031】ゲート電極8は大電流を流す必要がないため、通常細い導体1本で構成されている。 [0031] Since the gate electrode 8 is not necessary to flow a large current, and a normal thin conductor one. なお、IGB It should be noted, IGB
T1の表面および裏面の各電極4、5、8、は、半田接合が可能なようにメタライズされている。 T1 of the front and back surfaces of the electrodes 4, 5, 8, are metallized so as to allow solder joint. メタライズの方法は特定されるものではなく、アルミニウム電極上にチタン・白金・金やチタン・パラジウム・金などの方法で表面に金属層を設ける方法やニッケル等で被覆する方法等を用いる。 The method of metallizing is not to be identified, a method for coating by a method and a nickel or the like providing a metal layer on the surface by a method such as titanium, platinum, gold or titanium-palladium-gold on the aluminum electrode or the like.

【0032】また、DBC基板2の裏面銅パターン11 Further, DBC back surface copper patterns 11 of the substrate 2
はヒートシンク12に半田13を介して接合されており、IGBT1で発生した熱は、半田6、表面銅パターン3、セラミック層14、裏面銅パターン11、半田1 Are joined through the solder 13 to the heat sink 12, heat generated in IGBT1 is, the solder 6, the surface copper pattern 3, the ceramic layer 14, the back surface copper pattern 11, the solder 1
3を経てヒートシンク12に達し、外部に放熱される。 3 through reached the heat sink 12 and radiated to the outside.

【0033】また、ここでは図示しないが、ヒートシンク12の周囲にはプラスチツク製の外囲器があり、IG Further, although not shown here, the periphery of the heat sink 12 has an envelope made of plastic, IG
BT1やDBC基板2の表面は絶縁のためのシリコンゲル等で封止されている。 Surface of BT1 and DBC substrate 2 is sealed with a silicone gel or the like for insulation. なお半導体スイッチング素子としてGT0を使用したの場合も、エミッタ電極5をアノード電極、コレクタ電極10をカソード電極と読み替えることで、実装構造は同様である。 In the case of using GT0 as semiconductor switching elements also, by replaced the emitter electrode 5 anode electrode, a collector electrode 10 and the cathode electrode, the mounting structure is the same.

【0034】本発明によれば、エミッタ電極4と配線基板2間に形成された配線を銅製の細導線を平帯状に編み上げた導体7とすることにより、素子の発熱によりエミッタ電極4とDBC基板2の間が変位して熱応力による疲労が発生する状態となっても、配線部分の剛性を小さくすることにより、熱応力発生を大幅に軽減することが出来る。 According to the present invention, by a conductor 7 that braided wires and the emitter electrode 4 is formed between the wiring substrate 2 made of copper fine wires into a flat strip, the emitter electrode 4 and the DBC substrate by heating elements even in a state in which between 2 fatigue due to the displacement to thermal stress generated by reducing the rigidity of the wiring part, the thermal stress generated can be greatly reduced.

【0035】従って、半導体素子との半田接合の破壊を免れることができ、さらに長寿命化を図ることが可能となる。 [0035] Accordingly, it is possible to avoid the destruction of the solder joint between the semiconductor element, it is possible to further increase the life of.

【0036】なお、細導線を編み上げた導体の材質や形状は、これを限定するものではないが、電気伝導性の点からは銅線であることが好ましく、またパッケージ形状を薄型とする観点からは、平帯状に形成されたいわゆる平網線とすることが好ましい。 [0036] The material and shape of the conductors braided fine wires include, but are not limited to this, it is preferable that a copper wire in terms of electrical conductivity, also the package shape from the viewpoint of a thin is preferably a so-called tint lines formed on the flat belt.

【0037】平網線はその素線径と数により各種あるが、ここでは応力緩和を目的とするため、長手方向の弾性率が1GPa以下とすることが特に好ましい。 [0037] While Hiraamisen are various by the wire diameter and number, wherein for the purpose of stress relaxation, it is particularly preferred that the longitudinal direction of the elastic modulus is less 1 GPa. また編線の端子部分はそのままであつても、薄板等でばらけ防止のため端子処理したものでも良い。 Terminal portion of the hand braided be thick as it may be one obtained by the terminal processing for loose preventing a thin plate or the like.

【0038】配線基板は、半導体素子で発生する熱を放熱するため、放熱性に優れた基板が好ましい。 The wiring board, for dissipating heat generated in the semiconductor element, superior substrate is preferred to heat dissipation. このためアルミニウム・インバー・鉄などの金属べース上にエボキシ・ポリブタジエン・ポリイミドなどの絶縁層を形成し、その上に銅箔などで配線パターンを形成したいわゆるメタルコア基板や、アルミニウム・窒化アルミニウムなどのセラミック材料を基材として、表面に銅・アルミニウムなどの金属による配線を形成した基板が好適で、 Therefore the aluminum invar, iron, etc. on the metal base over the scan to form an insulating layer such as Ebokishi polybutadiene polyimide, on so-called metal core substrate and forming a wiring pattern with a copper foil on the aluminum-aluminum nitride, etc. the ceramic material as a base material of a substrate formed with wiring by metal such as copper, aluminum on the surface is preferred,
中でも絶縁耐圧が要求される分野では、アルミニウム・ Above all in the field of dielectric strength is required, aluminum
窒化アルミニウムなどに銅箔を直接貼り付けたいわゆるDBC基板(銅張りセラミック基板)等が好適である。 So-called DBC substrate stuck on copper foil directly to aluminum nitride (copper-clad ceramic substrate) and the like.

【0039】また、半田接合の材料としては各種の半田材料をし使用することが可能であるが、本発明の半田接合部は、高い熱ストレスに晒されることから、耐ストレス性を有する半田材料が好適である。 Further, although as the material of the solder joint can be used to various solder materials, the solder joints of the present invention, from exposure to high thermal stress, a solder material having a stress resistance it is preferred. また複数の半田接合部が存在する場合には、これらを順次、単独に半田付けしても、また複数の部位を一括して半田付けしても良く、前者においては順位に応じて融点を順次低くしていかなければならないことは当然である。 If a plurality of solder joints are present, sequentially, even if the soldering alone, also may be soldered collectively multiple sites sequentially melting point in accordance with the ranking in the former that we must be low is a matter of course.

【0040】次にこれらの構造の製造方法について説明すると、図示しない実装装置であるダイマウンターの所定位置に銅張りセラミック基板2をセットし、IGBT Next will be described a method for manufacturing these structures, to set the copper-clad ceramic substrate 2 to a predetermined position of the die mounter an implementation device (not shown), IGBT
1を保持したヘッドが所定位置に降下してコレクタ電極10を銅張りセラミック基板2の所定位置にダイマウンティングを行う。 Head holding the 1 performs die mounting the collector electrode 10 descends to a predetermined position in a predetermined position of the copper-clad ceramic substrate 2. このダイマウンティングは窒素雰囲気中でフラックスレス半田を用いてスクラブマウントを行う。 The die mounting do scrub mount by using a flux-free solder in a nitrogen atmosphere. 半田はシート半田でも滴下による半田供給でもよい。 Solder may be a solder supply by dropping in a sheet solder.

【0041】次の工程でIGBT1のエミッタ電極4とゲート電極8をそれぞれ銅製の平織線である導体7、9 The conductors 7 and 9 are each copper plain weave wire emitter electrode 4 and the gate electrode 8 of the IGBT1 in the next step
と半田接合する。 And the solder joint. その後、ヒートシンク12を銅張りセラミック基板2の裏面に半田接合する。 Then, solder bonding the heat sink 12 on the rear surface of the copper-clad ceramic substrate 2. これらの半田接合はそれぞれ仮付けしておきリフロー炉で同時に半田付けを行う。 These solder joints do soldering simultaneously in a reflow furnace previously temporarily attached respectively.

【0042】なお、これらの半田付はリフロー炉で同時に行わず順次それぞれの個所を行ってもよい。 [0042] It should be noted, these soldering may be carried out sequentially each of the locations without at the same time in a reflow furnace.

【0043】図2は本発明にかかる半導体装置の第2の実施の形態を示したものである。 [0043] FIG. 2 shows a second embodiment of a semiconductor device according to the present invention. 第1のIEGT21と第2のIEGT22は、いづれも半導体スイツチング素子の一種である。 A first IEGT21 second IEGT22 is Izure is also a kind of semiconductor switching-devices. 第1のIEGT21の表面に設けられたエミッタ電極23はDBC基板24の表面銅パターン25と細導線を編み上げた第1の導体26により接続されている。 Emitter electrode 23 provided on the surface of the first IEGT21 are connected by a first conductor 26 that braided surface copper pattern 25 and the fine wire of DBC substrate 24.

【0044】第2のIEGT22の表面エミッタ電極2 The surface emitter electrode 2 of the second IEGT22
7は、銅製の細導線を平帯状に編み上げた第2の導体2 7, the second conductor braided copper fine wires to flat belt 2
8により、引き出し端子29と接続されている。 By 8 is connected to the lead terminal 29. また第1のIEGT21と第2のIEGT22の表面にはそれぞれゲート電極30、31が設けられており、DBC基板24の表面銅パターン(紙面に垂直方向にあるため図示せず)に平帯状の導体32と33(紙面に垂直方向に延長)により接続されている。 The first IEGT21 and have gate electrodes 30 and 31 respectively is provided on the surface of the second IEGT22, DBC surface copper pattern of the substrate 24 (the paper not shown because it is in the vertical direction) in the flat strip conductor are connected by 32 and 33 (extending in the direction perpendicular to the plane of the drawing). また、また第1のIEG In addition, also the first of IEG
T21と第2のIEGT22の裏面にはそれぞれコレクタ電極43、44が設けられていて、それぞれDBC基板24の表面銅パターン25、39に半田接続されている。 T21 and the back surface of the second IEGT22 have collector electrodes 43 and 44 are respectively provided, are soldered to the surface copper pattern 25, 39 of the DBC substrate 24, respectively.

【0045】ゲート電極30、31は大電流を流す必要がないため、通常細い導体1本で構成されている。 [0045] Since the gate electrodes 30 and 31 need not to flow a large current, and a normal thin conductor one. またDBC基板24の裏面銅パターン34はヒートシンク3 The back surface copper pattern 34 of the DBC substrate 24 is a heat sink 3
5と半田36により接合されており、IEGT21で発生した熱は、半田37、38、表面銅パターン25と銅パターン39、セラミック層40、裏面銅パターン3 5 and are joined by solder 36, heat generated in IEGT21, the solder 37 and 38, the surface copper pattern 25 and the copper pattern 39, the ceramic layer 40, the back surface copper pattern 3
4、半田36を経てヒートシンク35に達して外部に放熱される。 4, are radiated to the outside reaches the heat sink 35 through the solder 36.

【0046】また、ここでは図示しないが、ヒートシンク35の周囲にはプラスチック製の外囲器があり、IE [0046] Furthermore, although not shown here, the periphery of the heat sink 35 has an envelope made of plastic, IE
GT21やDBC基板24の表面は絶縁のためのシリコンゲル等で封止されている。 Surface of GT21 and DBC substrate 24 is sealed with a silicone gel or the like for insulation.

【0047】なお、半導体スイッチング素子としてGT [0047] In addition, GT as a semiconductor switching element
0を使用したの場合も、エミッタ電極を正極(アノード)電極、コレクタ電極を負極(カソード)電極と読み替えることで、実装構造は同様である。 For using 0. By replaced the emitter electrode positive (anode) electrode, a collector electrode and the negative electrode (cathode) electrode, mounting structure is the same.

【0048】次にこれらの構造の製造方法について説明すると、図示しない実装装置であるダイマウンターの所定位置に銅張りセラミック基板24をセットし、第1のIGBT21を保持したヘッドが所定位置に降下してコレクタ電極43を銅張りセラミック基板24にダイマウンティングを行う。 Next will be described a method for manufacturing these structures, to set the copper-clad ceramic substrate 24 in a predetermined position of the die mounter an implementation device (not shown), the head holding a first IGBT21 is lowered to a predetermined position performing die mounting the collector electrode 43 to the copper-clad ceramic substrate 24 Te. 続いて同様に、第2のIGBT22 Similarly Subsequently, the second IGBT22
を保持したヘッドが所定位置に降下してコレクタ電極4 It descends to a predetermined position head holding the collector electrode 4
4を銅張りセラミック基板24の所定位置にダイマウンティングを行う。 4 performs die mounting in position of the copper-clad ceramic substrate 24. このダイマウンティングは窒素・水素混合雰囲気中でフラックスレス半田を用いてスクラブマウントを行う。 The die mounting do scrub mount by using a flux-free solder in a nitrogen-hydrogen mixed atmosphere. 半田はシート半田でも滴下による半田供給でもよい。 Solder may be a solder supply by dropping in a sheet solder.

【0049】次の工程でIGBT21のエミッタ電極2 [0049] IGBT21 of the emitter electrode in the next step 2
3とゲート電極30をそれぞれ銅製の平織線である導体26、32と半田接合する。 3 and the gate electrode 30 to the conductor 26, 32 and the solder joint is copper plain weave line. 続いて同様に、IGBT2 Similarly followed, IGBT2
2のエミッタ電極27とゲート電極31をそれぞれ銅製の平織線である導体28、33と半田接合する。 Second emitter electrode 27 and the gate electrode 31 and conductor 28, 33 and the solder joint is copper plain weave line. さらに、導体28、33の他端部を基板24上の所定の導体に半田接続する。 Further, solder connection and the other end of the conductor 28, 33 to the predetermined conductor on the substrate 24. その後、ヒートシンク35を銅張りセラミック基板24の裏面に半田接合する。 Then, solder bonding the heat sink 35 on the rear surface of the copper-clad ceramic substrate 24. これらの半田接合はそれぞれ仮付けしておきリフロー炉で同時に半田付けを行う。 These solder joints do soldering simultaneously in a reflow furnace previously temporarily attached respectively.

【0050】なお、これらの半田付けはリフロー炉で同時に行わず順次それぞれの個所を行ってもよい。 [0050] It should be noted, these soldering may be carried out sequentially each of the locations without at the same time in a reflow furnace.

【0051】この第2の実施の形態によれば、半導体スイッチング素子の発熱による熱応力は配線部分の剛性を小さくすることにより、応力発生を大幅に軽減することが出来る。 [0051] According to this second embodiment, the thermal stress due to heat generation of the semiconductor switching element by reducing the rigidity of the wiring portion can be significantly reduced stress generation. したがって、半導体スイッチ素子との半田接合部の半田の疲労を抑えることが可能になり、接合寿命の高信頼かが可能となる。 Therefore, it is possible to suppress the solder fatigue of the solder joint between the semiconductor switching element, thereby enabling reliable or joint life. 従って、半導体スイッチング素子や半田接合部の半田の疲労を押さえることが可能となり、接合寿命の高信頼性化が可能となる。 Therefore, it is possible to suppress the solder fatigue of the semiconductor switching element and the solder joint, high reliability of bonding life becomes possible.

【0052】図3は本発明に関する半導体装置の第3の実施の形態を示す断面図である。 [0052] FIG. 3 is a sectional view showing a third embodiment of a semiconductor device relating to the present invention. 半導体スイッチング素子の一つであるIGBT1aは、裏面に正極電極であるエミッタ電極4aが配線基板である銅張セラミック基板2aの表面の銅パターン3aの所定位置に半田層6aによって半田接合されている。 Is one IGBT1a semiconductor switching element is soldered by the solder layer 6a at a predetermined position on the surface of the copper pattern 3a of the copper-clad ceramic substrate 2a is an emitter electrode 4a is positive electrode on the back surface is a wiring board. また、その裏面の端部には制御電極であるゲート電極8aが設けられ、同様に銅張セラミック基板2aの所定位置に半田層6aによって半田接合されている。 Moreover, the the end of the back gate electrode 8a is provided as a control electrode are solder-bonded similarly by the solder layer 6a at a predetermined position of the copper-clad ceramic substrate 2a. また、銅張セラミック基板2aの裏面側には裏面の銅パターン3aを介してヒートシンク1 The heat sink 1 on the back side of the copper-clad ceramic substrate 2a via the back surface of the copper pattern 3a
2aが半田層6aによって半田接合されている。 2a is soldered by the solder layer 6a. このヒートシンク12aの周囲には図示しないプラスチック製の外囲器が設けられ、IGBT1aや銅張セラミック基板2aの表面は絶縁のためシリコンゲル等で封止されている。 The plastic envelope (not shown) around the heat sink 12a is provided, the surface of IGBT1a and clad ceramic substrate 2a is sealed with a silicone gel or the like for insulation.

【0053】IGBT1aの表面には負極電極のコレクタ電極5aが所定の対向位置(半導体装置として表面側に位置)に配設された導体7aに半田層6aを介して半田接合されている。 [0053] The surface of IGBT1a collector electrode 5a of the negative electrode is soldered via a solder layer 6a at a predetermined position opposite the conductor 7a disposed (positioned on the surface side as a semiconductor device). この導体7aは、銅製の細導線を平帯状に編み上げて成形されたものである。 The conductors 7a are those molded braided copper fine wire to a flat strip. そして、この導体7aの長手方向の弾性率は1GPa以下が好ましい。 The longitudinal elastic modulus of the conductor 7a is preferably equal to or less than 1 GPa.

【0054】その結果、この第3の実施の形態の半導体装置も、熱応力の発生を大幅に軽減することができるので、半田接合破壊を防止して長寿命化を図ることができる。 [0054] As a result, the third embodiment of the semiconductor device also, since the occurrence of thermal stress can be greatly reduced, it is possible to increase the life of to prevent solder joint fracture.

【0055】図4は、本発明の第4の実施の形態を示す断面図である。 [0055] Figure 4 is a sectional view showing a fourth embodiment of the present invention. 半導体スイッチング素子の一つであるI I is one of the semiconductor switching elements
EGT11aは、裏面に正極電極であるエミッタ電極4 EGT11a, the emitter electrode 4 is positive electrode on the back surface
aが銅張りセラミック基板2aの表面の銅パターン3a Copper pattern 3a on the surface of a copper-clad ceramic substrate 2a
の所定位置に半田接合され半田層6aを形成している。 It is of a predetermined position solder joint to form a solder layer 6a.
この半田層6aの中には熱応力を緩和するための緩衝板16aが挿入されている。 Buffer plate 16a for relieving the thermal stress is inserted into the solder layer 6a. 緩衝板16aはIEGT11 Buffer plate 16a is IEGT11
aに応力を加えないためにIEGT11aの基材であるシリコンと熱膨張率の近い材料が好ましく、モリブテン、タングステン等の単体金属や銅−タングステン、4 Silicon and the material preferably close to that of thermal expansion coefficient as the base material of IEGT11a in order not stressed to a, molybdenum, elemental metal or copper tungsten - tungsten, 4
2アロイ等の合金や銅−インバー−銅等のクラッド材を用いる。 Alloy and copper, such as 2 alloy - Invar - using clad material such as copper.

【0056】また、IEGT11a表面の端部には制御電極であるゲート電極8aが設けられ、同様に銅張りセラミック基板2aの所定位置に半田層6aで半田接合されている。 [0056] Further, the end portion of the IEGT11a surface is provided gate electrode 8a is controlled electrodes are soldered with a solder layer 6a in the same manner as a predetermined position of the copper-clad ceramic substrate 2a. この半田層6aも同様に緩衝板16aが挿入されている。 The solder layer 6a likewise buffer plate 16a is inserted. また、銅張りセラミック基板2aの裏面側にも表面の銅パターン3Yを介してヒートシンク12a The heat sink 12a via the copper pattern 3Y surface on the back surface side of the copper-clad ceramic substrate 2a
が半田層6aによって半田接合されている。 There has been soldered by the solder layer 6a. このヒートシンク12aの周囲には図示しないプラスチック製の外囲器が設けられ、IEGT11aや銅張りセラミック基板2aの表面は絶縁のためシリコンゲル等で封止されている。 This is around the heat sink 12a plastic envelope (not shown) is provided, the surface of IEGT11a and copper-clad ceramic substrate 2a is sealed with a silicone gel or the like for insulation. IEGT11aの表面には負極電極のコレクタ電極5aが(半導体装置として表面側に位置)対向位置に配設された所定の導体7aに半田層6aを介して半田接合されている。 The surface of IEGT11a are bonded solder through the solder layer 6a on predetermined conductor 7a collector electrode 5a is (the position on the surface side as a semiconductor device) is disposed in the position facing the negative electrode. この半田層6aにもエミッタ電極4a等と同様に緩衝板16aが挿入されている。 Buffer plate 16a similar to the emitter electrode 4a and the like are also inserted into the solder layer 6a.

【0057】前記導体7aは、銅製の細導線を平帯状に編み上げて成形されたものである。 [0057] The conductors 7a are those molded braided copper fine wire to a flat strip. そして、この導体7 Then, the conductor 7
aの長手方向の弾性率は1GPa以下が好ましい。 Longitudinal elastic modulus of a is preferably equal to or less than 1 GPa. その結果、この第4の実施の形態の半導体装置も、熱応力の発生を大幅に軽減することができるので、半田接合破壊を防止して長寿命化を図ることができる。 As a result, the fourth embodiment of the semiconductor device also, since the occurrence of thermal stress can be greatly reduced, it is possible to increase the life of to prevent solder joint fracture.

【0058】特に、半田層6a内に挿入している緩衝板12aにより、熱応力を緩和することができる効果は、 [0058] In particular, the effect that can be the buffer plate 12a that is inserted into the solder layer 6a, to relax the thermal stress,
平帯状に編み上げられた導体7aを用いる効果と相俟って相乗的に作用する。 Act synergistically effect coupled with the use of conductors 7a which is braided into a flat strip.

【0059】なお、各緩衝板16aはそれぞれ半田層6 [0059] In addition, each of the buffer plate 16a is solder layer 6
aの中に挿入されているが、半田で接合される部材のいずれかに接合してもよい。 Has been inserted into the a, it may be bonded to one of the members to be joined by soldering.

【0060】 [0060]

【発明の効果】以上に述べたように本発明によれば、従来の平板または棒状の電極に代えて、細導線を編み上げた導体を用いることで、配線インダクタンスが低い平板配線の利点を保ったまま、電極の剛性を低下させたと共に熱応力を小さくした。 According to the present invention as described above, according to the present invention, instead of the conventional flat or rod-shaped electrodes, by using the conductor braided fine wires, wiring inductance keeping the advantages of lower flat wire while, and reduce the thermal stress with reduced stiffness of the electrode.

【0061】従って、熱疲労による半導体素子の接合部等の破壊を確実に防止することができる。 [0061] Accordingly, it is possible to reliably prevent the breakage of the joint portion of the semiconductor element due to thermal fatigue.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施の形態の半導体装置を示す断面図である。 1 is a sectional view showing a semiconductor device of the first embodiment of the present invention.

【図2】本発明の第2の実施の形態の半導体装置を示す断面図である。 2 is a sectional view showing a semiconductor device of the second embodiment of the present invention.

【図3】本発明の第3の実施の形態の半導体装置を示す断面図である。 3 is a sectional view showing a semiconductor device of the third embodiment of the present invention.

【図4】本発明の第4の実施の形態の半導体装置を示す断面図である。 4 is a fourth sectional view showing a semiconductor device of the embodiment of the present invention.

【図5】従来の半導体装置を基板に実装した例を示す断面図である。 [5] The conventional semiconductor device is a sectional view showing an example of mounting on a substrate.

【図6】従来の半導体装置を基板に実装した別の例を示す断面図である。 [6] The conventional semiconductor device is a sectional view showing another example of mounting on a substrate.

【符号の説明】 DESCRIPTION OF SYMBOLS

1、1a、21、22…IGBT、2、2a,24…D 1,1a, 21,22 ... IGBT, 2,2a, 24 ... D
BC基板(銅張セラミック基板)、3、3a…表面銅パターン、4、4a、23、27…エミッタ電極、5、5 BC substrate (copper-clad ceramic substrate), 3, 3a ... surface copper patterns, 4, 4a, 23, 27 ... emitter electrode, 5,5
a、10、43、44…コレクタ電極、6、6a…半田(層)、7、7a…導体、8、30、31…ゲート電極、11…裏面銅パターン a, 10,43,44 ... a collector electrode, 6, 6a ... solder (layers), 7, 7a ... conductor, 8,30,31 ... gate electrode, 11 ... rear surface copper pattern

Claims (10)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 一表面に正極電極と制御電極とが形成され他表面に負極電極が形成された半導体スイッチング素子と、金属導体が設けられ且つ前記半導体スイッチング素子が実装される配線基板とを具備し、この配線基板の金属導体の、前記正極電極及び制御電極及び負極電極の少なくとも一つに対する電気的接続は、細導線を編み上げた導体により行われていることを特徴とする半導体装置。 1. A comprising a positive electrode on one surface and a control electrode and is formed a semiconductor switching element anode electrodes are formed on the other surface, and a wiring board in which the metal conductor is provided and the semiconductor switching elements are mounted semiconductor device, and the metal conductor of the wiring board, electrically connected to at least one of the positive electrode and the control electrode and the negative electrode, characterized in that is performed by conductors braided fine wires.
  2. 【請求項2】 前記配線基板の金属導体と、前記細導線を編み上げた導体とは半田接合により接合されていることを特徴とする請求項1記載の半導体装置。 Wherein said metal conductor of the wiring board, a semiconductor device according to claim 1, wherein the conductor braided said fine conductors, characterized in that it is joined by the joining solder.
  3. 【請求項3】 前記細導線を編み上げた導体と接続されている前記正極電極及び前記制御電極及び前記負極電極の少なくとも一つは半田接合により接合されていることを特徴とする請求項1記載の半導体装置。 3. A according to claim 1, characterized in that it is joined by at least one solder joint of the positive electrode and the control electrode and the negative electrode is connected to the conductor braided said fine wire semiconductor device.
  4. 【請求項4】 前記半導体スイツチング素子がIGBT Wherein said semiconductor switching-device IGBT
    素子又はIEGT素子であることを特徴とする請求項1 Claim, characterized in that an element or IEGT element 1
    記載の半導体装置。 The semiconductor device according.
  5. 【請求項5】 前記配線基板がセラミック基板上に金属導体を形成したものであることを特徴とする請求項1記載の半導体装置。 Wherein said semiconductor device according to claim 1, wherein the wiring board is made by forming a metal conductor on a ceramic substrate.
  6. 【請求項6】 前記配線基板は金属べース上に絶縁層を形成し、さらにその上に金属導体を形成したものであることを特徴とする請求項1記載の半導体装置。 Wherein said wiring board is a semiconductor device according to claim 1, wherein the forming an insulating layer on a metal base over scan, in which further forming a metal conductor thereon.
  7. 【請求項7】 前記細導線は銅製の線材を平帯状に編み上げたものであることを特徴とする請求項1記載の半導体装置。 Wherein said fine conductors semiconductor device according to claim 1, wherein a is obtained braided copper wire in the flat belt.
  8. 【請求項8】 前記細導線を平帯状に編み上げた導体の長手方向の弾性率が1GPa以下であることを特徴とする請求項7記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the longitudinal elastic modulus of conductors braided said fine wire into a flat strip is equal to or less than 1 GPa.
  9. 【請求項9】 前記半導体スイッチング素子が複数個前記配線基板上設けられた際に、各半導体スイッチング素子間の配線の一部として細導線を編み上げた導体を使用したことを特徴とする半導体装置。 Wherein said semiconductor when the switching element is provided with a plurality said wiring board, a semiconductor device characterized by using the conductors braided fine wires as part of the wiring between the semiconductor switching devices.
  10. 【請求項10】 一表面に正極電極と制御電極とが形成され且つ他裏面に負極電極が形成された半導体スイッチング素子と、金属導体が設けられ且つ前記半導体スイッチ素子が実装される配線基板とを具備する半導体装置の製造方法において、 前記正極電極と前記制御電極とを前記配線基板の金属導体に対して半田接合するか、又は、前記負極電極を前記配線基板の金属導体に対して半田接合する第1の半田接合工程と、 前記正極電極及び前記制御電極及び前記負極電極の少なくとも一つを一端が前記配線基板の金属導体に電気的に接続される細導線を編み上げた導体の他端に半田接合する第2の半田接合工程とを有することを特徴とする半導体装置の製造方法。 10. A semiconductor switching element one surface and the positive electrode and the control electrode is formed on and another backside negative electrode is formed and a wiring board in which the metal conductor is provided and the semiconductor switch element is mounted the method of manufacturing a semiconductor device including either a said control electrode and the cathode electrode soldered to the metal conductors of the wiring board, or, soldered to the negative electrode to the metal conductor of the wiring substrate a first solder bonding step, the solder at the other end of the positive electrode and the control electrode and the conductor at least one end of the negative electrode is braided electrically connected to thin wires to the metal conductors of the wiring substrate the method of manufacturing a semiconductor device characterized by a second solder bonding step of bonding.
JP21704898A 1998-07-31 1998-07-31 Semiconductor device and manufacture thereof Pending JP2000049280A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023137A (en) * 2001-07-09 2003-01-24 Sansha Electric Mfg Co Ltd Power semiconductor module
JP2003197864A (en) * 2001-12-06 2003-07-11 Abb Res Ltd Power semiconductor module
JP2006310341A (en) * 2005-04-26 2006-11-09 Fuji Electric Device Technology Co Ltd Semiconductor device
EP1764832A1 (en) * 2005-08-24 2007-03-21 Semikron Elektronik GmbH & Co. KG Patentabteilung Bonding connection for semiconductor power devices
JP2007243157A (en) * 2006-02-09 2007-09-20 Diamond Electric Mfg Co Ltd Semiconductor module, semiconductor device provided with the same, and manufacturing method of semiconductor module
JP2008042041A (en) * 2006-08-09 2008-02-21 Fuji Electric Holdings Co Ltd Semiconductor device
JP2013042135A (en) * 2011-08-16 2013-02-28 General Electric Co <Ge> Power overlay structure with leadframe connections
JP2014187146A (en) * 2013-03-22 2014-10-02 Sumitomo Electric Ind Ltd Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023137A (en) * 2001-07-09 2003-01-24 Sansha Electric Mfg Co Ltd Power semiconductor module
JP2003197864A (en) * 2001-12-06 2003-07-11 Abb Res Ltd Power semiconductor module
JP4669650B2 (en) * 2001-12-06 2011-04-13 エー ビー ビー リサーチ リミテッド Power semiconductor module
JP2006310341A (en) * 2005-04-26 2006-11-09 Fuji Electric Device Technology Co Ltd Semiconductor device
EP1764832A1 (en) * 2005-08-24 2007-03-21 Semikron Elektronik GmbH &amp; Co. KG Patentabteilung Bonding connection for semiconductor power devices
JP2007243157A (en) * 2006-02-09 2007-09-20 Diamond Electric Mfg Co Ltd Semiconductor module, semiconductor device provided with the same, and manufacturing method of semiconductor module
JP2008042041A (en) * 2006-08-09 2008-02-21 Fuji Electric Holdings Co Ltd Semiconductor device
JP2013042135A (en) * 2011-08-16 2013-02-28 General Electric Co <Ge> Power overlay structure with leadframe connections
JP2014187146A (en) * 2013-03-22 2014-10-02 Sumitomo Electric Ind Ltd Semiconductor device

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