JP2008042041A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008042041A
JP2008042041A JP2006216326A JP2006216326A JP2008042041A JP 2008042041 A JP2008042041 A JP 2008042041A JP 2006216326 A JP2006216326 A JP 2006216326A JP 2006216326 A JP2006216326 A JP 2006216326A JP 2008042041 A JP2008042041 A JP 2008042041A
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semiconductor chip
thermal stress
buffer member
stress buffer
semiconductor device
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JP5023604B2 (en
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Yuji Iizuka
祐二 飯塚
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which thermal stress resulting from difference in thermal expansion between a semiconductor chip and a wiring lead material is reduced, while ensuring high conductivity and a heat transmission route between the semiconductor chip and the wiring lead material for connection to its upper surface side main electrode. <P>SOLUTION: A semiconductor device mounts a semiconductor chip 3 on an insulating substrate 2 bonded to a heat dissipation metal base 1 to transmit heat, and mounts the leg of a wiring lead material 4 for connection to its upper surface main electrode. The semiconductor chip 3 and the wiring lead material 4 are bonded by inserting a thermal stress buffering member 9 composed of a composite material produced by osmotically-dispersing a metal having a melting point lower than that of a substrate into a carbon substrate or a metal substrate between the semiconductor chip and the wiring lead material. The thermal stress buffering member 9 has a box shape surrounding the periphery of the semiconductor chip 3, the peripheral leg is bonded to the insulating substrate which is bonded to the metal base to transmit heat, a conduction/heat transmission route is ensured by forming a conductor post 9a in the region of bonding surface to the semiconductor chip, and the inside of the thermal stress buffering member 9 is filled with sealing resin 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電力変換装置，スイッチング電源などに適用するパワー半導体デバイスを対象とした半導体装置に関し、詳しくはそのパッケージ構造に係わる。   The present invention relates to a semiconductor device intended for a power semiconductor device applied to a power conversion device, a switching power supply, etc., and more particularly to a package structure thereof.

昨今では、頭記の電力変換装置，スイッチング電源などに適用するパワー半導体デバイスの大容量化が進み、これに伴いパワー半導体デバイスに搭載する半導体チップ（例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）など）は高い電流密度で通電使用されることから、放熱対策およびパワーサイクル耐量の長寿命化を図ることが重要課題となっている。   In recent years, the capacity of power semiconductor devices applied to the power converters and switching power supplies mentioned above has increased, and as a result, semiconductor chips (for example, IGBTs (Insulated Gate Bipolar Transistors) mounted on power semiconductor devices) Since energization and use is performed at a high current density, it is important to improve the heat dissipation and extend the life of power cycle resistance.

すなわち、ＩＧＢＴなどのパワー半導体デバイスでは、半導体チップの接合部温度Ｔjに上限保証温度（例えば１２５℃）が規定されているのに対して、放熱用ベース（銅ベース板）に絶縁基板を介して半導体チップをマウントした片面冷却方式では、半導体チップの上面側がパッケージ内に充填した封止樹脂で封止されているためにチップの上面側からの放熱は殆ど期待できない。このために半導体チップの大電流化に伴い発熱密度が増大すると、半導体チップの上面電極に接続する配線リードとしてアルミワイヤをボンディングした在来の配線構造では、チップの接合部温度を上限保証温度以下に抑えることが困難であるばかりか、アルミワイヤのジュール発熱も加わってワイヤ溶断のおそれもあってパワーサイクル耐量，信頼性の低下が懸念される。   That is, in a power semiconductor device such as an IGBT, an upper limit guaranteed temperature (for example, 125 ° C.) is defined for the junction temperature Tj of the semiconductor chip, whereas the heat dissipation base (copper base plate) is interposed via an insulating substrate. In the single-sided cooling method in which the semiconductor chip is mounted, the upper surface side of the semiconductor chip is sealed with the sealing resin filled in the package, so that heat radiation from the upper surface side of the chip can hardly be expected. For this reason, when the heat generation density increases with the increase in current of the semiconductor chip, in the conventional wiring structure in which an aluminum wire is bonded as a wiring lead connected to the upper surface electrode of the semiconductor chip, the junction temperature of the chip is below the upper limit guaranteed temperature. This is not only difficult to suppress, but also due to the joule heat generation of the aluminum wire, there is a risk of wire fusing, and there is a concern that power cycle resistance and reliability will be reduced.

特に、最近では半導体素子に耐熱温度の高い（３５０℃）化合物半導体（ＧａＡｇ，ＩｎＰなど）を用いて高速動作化した半導体デバイスの開発が進められていてその放熱対策がますます重要性を増している。
一方、半導体チップの上面に放熱経路を確保してチップ全体の放熱性を高める手段として、前記のアルミワイヤに代えて断面積の大きなフレーム状の配線リード材（リードフレーム）を半導体チップの上面主電極に半田接合し、このリードフレームを伝熱経路として半導体チップの発生熱をチップ上面側から絶縁基板を介して金属ベースに放熱せるようにした構成のものが知られている（例えば、特許文献１参照）。 In particular, the development of high-speed semiconductor devices that use high-heat-resistant (350 ° C) compound semiconductors (GaAg, InP, etc.) as semiconductor elements has been underway recently, and countermeasures for heat dissipation are becoming increasingly important. Yes.
On the other hand, instead of the aluminum wire, a frame-like wiring lead material (lead frame) having a large cross-sectional area is used instead of the aluminum wire as a means for securing a heat dissipation path on the upper surface of the semiconductor chip. There is known a configuration in which the heat generated by the semiconductor chip is radiated from the upper surface side of the chip to the metal base via the insulating substrate by soldering to the electrode and using this lead frame as a heat transfer path (for example, Patent Documents) 1).

次に、ＩＧＢＴの半導体デバイスを例に、従来におけるパッケージ構造を図４に示す。図４において、１は放熱用銅ベース、２は絶縁基板であり、この絶縁基板２は、窒化珪素，窒化ホウ素，窒化アルミなどのセラミックス基板２ａの表，裏両面に銅箔を直接接合して導体パターン２ｂ〜２ｄを形成したＤＣＢ（Direct Copper Bonding）基板である。また、３は絶縁基板２の上に形成した導体パターン２ｂにマウントしたパワー半導体チップ（ＩＧＢＴ）、４は半導体チップ３の上面電極（ＩＧＢＴのエミッタ電極）と絶縁基板２の導体パターン２ｃとの間に配線した配線リード材（両端にブロック状の接合脚部を形成したリードフレーム）、５は銅ベース１に結合したパッケージの外囲樹脂ケース、６は外部導出端子、７は外部導出端子６と絶縁基板２の上面側導体パターン２ｂとの間に配線したボンディングワイヤ、８はロウ付けした部品間の接合部であり、銅ベース１／絶縁基板２，絶縁基板２／半導体チップ３，半導体チップ３／リード材４，リード材４／絶縁基板２の間が例えばＳｎＡｇＣｕなどの半田で接合されている。なお、半導体チップ３を湿気，塵などから保護し、表面電極の酸化，腐食を防止するために、外囲樹脂ケース５の内部にはシリコーンゲルなどの封止樹脂を注入して半導体チップ３の周域を封止している。また、図示していなが前記銅ベース１の裏面には放熱フィン（ヒートシンク）を取付けて放熱性能を高めるようにしている。   Next, a conventional package structure is shown in FIG. 4 by taking an IGBT semiconductor device as an example. In FIG. 4, 1 is a copper base for heat dissipation, and 2 is an insulating substrate. This insulating substrate 2 is formed by directly bonding copper foil to the front and back surfaces of a ceramic substrate 2a such as silicon nitride, boron nitride, and aluminum nitride. It is a DCB (Direct Copper Bonding) substrate on which conductor patterns 2b to 2d are formed. Further, 3 is a power semiconductor chip (IGBT) mounted on a conductor pattern 2b formed on the insulating substrate 2, and 4 is a space between the upper surface electrode (IGBT emitter electrode) of the semiconductor chip 3 and the conductor pattern 2c of the insulating substrate 2. Wiring lead material (lead frame in which block-shaped joint legs are formed on both ends), 5 is an outer resin case of the package coupled to the copper base 1, 6 is an external lead terminal, 7 is an external lead terminal 6 and Bonding wires wired between the upper surface side conductor pattern 2b of the insulating substrate 2 and 8 are joint portions between the brazed components, and are copper base 1 / insulating substrate 2, insulating substrate 2 / semiconductor chip 3, semiconductor chip 3 The lead material 4, the lead material 4 and the insulating substrate 2 are joined together by solder such as SnAgCu. In order to protect the semiconductor chip 3 from moisture, dust and the like, and to prevent oxidation and corrosion of the surface electrode, a sealing resin such as silicone gel is injected into the surrounding resin case 5 so that the semiconductor chip 3 The peripheral area is sealed. Although not shown, a heat radiating fin (heat sink) is attached to the back surface of the copper base 1 so as to improve the heat radiating performance.

そのほか、半導体チップの上面主電極に良伝熱性の金属導体ブロックを半田接合し、これをヒートスプレッダとして半導体チップの局部的な温度上昇を緩和させるようにした構成も知られている（例えば、特許文献２参照）。
ところで、前記のように半導体チップ３の主面に配線リード材４（ないし前記のヒートスプレッダ）を重ね合わせて両者の間を半田接合（面接合）したパッケージの組立構造で、実使用時における半導体チップの動作温度が高まる（例えば２００℃以上）と部品間を半田付けした接合部の接合界面に金属間化合物が成長し、半田が溶融しない場合でも再結晶化が進んで結晶組織が劣化する。また、半導体チップ３（Ｓｉ）と配線リード材４（Ｃｕ，Ａｌなど）との熱膨張差から、ヒートサイクルに伴い半田接合部に発生する熱応力がその接合面方向に剪断応力として繰り返し作用する。このために、ロウ接合層８には前記の結晶組織の劣化，熱応力による疲労でクラックが発生するなどの欠陥が生じて接合の信頼性が低下する問題がある。 In addition, a configuration is also known in which a heat conductive metal conductor block is soldered to the upper surface main electrode of a semiconductor chip, and this is used as a heat spreader to alleviate a local temperature rise of the semiconductor chip (for example, Patent Documents). 2).
By the way, as described above, the assembly structure of the package in which the wiring lead material 4 (or the heat spreader) is superimposed on the main surface of the semiconductor chip 3 and soldered between the two (surface bonding), and the semiconductor chip in actual use. When the operating temperature increases (for example, 200 ° C. or higher), an intermetallic compound grows at the joint interface of the soldered part, and recrystallization proceeds and the crystal structure deteriorates even when the solder does not melt. Further, due to the difference in thermal expansion between the semiconductor chip 3 (Si) and the wiring lead material 4 (Cu, Al, etc.), the thermal stress generated in the solder joint portion with the heat cycle repeatedly acts as a shear stress in the joint surface direction. . For this reason, there is a problem that the reliability of the bonding is lowered due to defects such as the deterioration of the crystal structure and the occurrence of cracks due to fatigue due to thermal stress in the solder joint layer 8.

一方、半導体チップと配線リード材との熱膨張差に起因して半田接合層の接合界面に作用する熱応力の緩和策として、ヤング率が半田よりも低い樹脂材の緩衝層に、該緩衝層を貫通してポスト電極を分散形成した構造の熱応力緩和層を半導体チップの主面電極と配線リード材との間に介挿した上で、そのポスト電極の両端をそれぞれ半導体チップの主電極面，配線リード材に接合し、該ポスト電極を介して半導体チップ／配線リード材間に導電経路を確保するとともに、半導体チップとリードフレームとの熱膨張係数差に起因して半田接合層に作用する熱応力を前記樹脂緩衝層で吸収緩和させるようにした半導体装置の構造が知られている（例えば、特許文献３参照）。   On the other hand, as a measure for mitigating thermal stress acting on the bonding interface of the solder bonding layer due to the difference in thermal expansion between the semiconductor chip and the wiring lead material, the buffer layer is formed on the buffer layer of a resin material having a Young's modulus lower than that of solder. A thermal stress relaxation layer having a structure in which post electrodes are formed so as to penetrate through are inserted between the main surface electrode of the semiconductor chip and the wiring lead material, and both ends of the post electrode are respectively connected to the main electrode surface of the semiconductor chip. , Bonded to the wiring lead material, securing a conductive path between the semiconductor chip / wiring lead material via the post electrode, and acting on the solder bonding layer due to the difference in thermal expansion coefficient between the semiconductor chip and the lead frame A structure of a semiconductor device in which thermal stress is absorbed and relaxed by the resin buffer layer is known (see, for example, Patent Document 3).

そのほか、半導体チップを搭載する放熱部材（ベース）として、線膨張係数の小さなモリブデン，タングステンなどを基材とする多孔質の金属焼結体に伝熱性の高い銅を含浸させるとともに、半導体チップの搭載面域には伝熱性の高い銅または銅合金の貫通金属体を埋設し、この放熱部材に半導体チップをロウ付けしてマウントした組立構造も知られている（例えば、特許文献４参照）。
特開２００１−３３２６６４号公報 特開２００５−１１６７０２号公報（図１） 特開２００３−２３４４４７号公報 ２００５−２７７３８２号公報 In addition, as a heat dissipation member (base) for mounting a semiconductor chip, a porous metal sintered body based on molybdenum, tungsten, etc. with a small linear expansion coefficient is impregnated with copper having high heat conductivity, and mounting of a semiconductor chip There is also known an assembly structure in which a copper or copper alloy penetrating metal body having high heat conductivity is embedded in the surface area, and a semiconductor chip is brazed to the heat radiating member and mounted (for example, see Patent Document 4).
JP 2001-332664 A Japanese Patent Laying-Open No. 2005-116702 (FIG. 1) JP 2003-234447 A 2005-277382

ところで、半導体チップとその上面主電極に接合する配線リード材（リードフレーム）との熱膨張差に起因して接合部に作用する熱応力の緩和策として、特許文献３に開示されている構成では、応力緩衝層が非導電性の樹脂層とこの樹脂層を貫通するポスト電極で形成されていることから、その通電，伝熱経路がポスト電極の部分に限定される。このために、発熱量の大きなパワー半導体デバイスでは、ハイパワー動作の高い信頼性を確保させることが困難である。   By the way, in the configuration disclosed in Patent Document 3, as a measure for mitigating thermal stress acting on the joint due to the difference in thermal expansion between the semiconductor chip and the wiring lead material (lead frame) joined to the upper surface main electrode. Since the stress buffer layer is formed of the non-conductive resin layer and the post electrode penetrating the resin layer, the energization and heat transfer paths are limited to the post electrode portion. For this reason, it is difficult to ensure high reliability of high-power operation in a power semiconductor device that generates a large amount of heat.

本発明は上記の点に鑑みなされたものであり、半導体チップとその上面側主電極に接続する配線リード材との間に通電性と高い伝熱性を確保しつつ、半導体チップと配線リード材との熱膨張差に起因する熱応力を効果的に低減して高い放熱性と高温動作の信頼性向上が図れるように改良した半導体装置のパッケージ構造を提供することを目的とする。   The present invention has been made in view of the above points, and while ensuring electrical conductivity and high heat conductivity between a semiconductor chip and a wiring lead material connected to the upper surface side main electrode, the semiconductor chip and the wiring lead material An object of the present invention is to provide an improved package structure of a semiconductor device that can effectively reduce the thermal stress caused by the difference in thermal expansion of the semiconductor device so that high heat dissipation and high temperature operation reliability can be achieved.

上記目的を達成するために、本発明によれば、放熱用金属ベースに伝熱接合した絶縁基板の上に半導体チップ、および該半導体チップの上面主電極に接続する配線リード材を搭載し、かつその周域を樹脂封止してなる半導体装置において、
炭素基材または金属基材に、これら基材よりも融点が低い低融点金属を浸透分散させて複合化した複合材からなる熱応力緩衝部材を、前記半導体チップと前記配線リード材との間に介挿して接合する（請求項１）ものとし、具体的には前記熱応力緩衝部材，およびその接合構造を次記のような態様で構成する。
（１）前記熱応力緩衝部材は、前記半導体チップおよび配線リード材に接合される天板部と、前記絶縁基板上の導体パターンに接合される脚部を有する箱型形状となし、パッケージの組立状態で該熱応力緩衝部材と前記絶縁基板との間に絶縁性の樹脂を充填して半導体チップを封止する（請求項２）。
（２）前記熱応力緩衝部材には、該熱応力緩衝部材の天板部を貫通し前記半導体チップと前記配線リード材との間を接続する導体ポストを設ける（請求項３）。 In order to achieve the above object, according to the present invention, a semiconductor chip and a wiring lead material connected to an upper surface main electrode of the semiconductor chip are mounted on an insulating substrate heat-transfer bonded to a metal base for heat dissipation, and In the semiconductor device formed by resin-sealing the peripheral area,
A thermal stress buffer member made of a composite material obtained by infiltrating and dispersing a low melting point metal having a melting point lower than that of a base material into a carbon base material or a metal base material is interposed between the semiconductor chip and the wiring lead material. In this case, the thermal stress buffer member and the joining structure thereof are configured in the following manner.
(1) The thermal stress buffer member has a box shape having a top plate portion joined to the semiconductor chip and the wiring lead material, and a leg portion joined to the conductor pattern on the insulating substrate, and assembly of the package In this state, an insulating resin is filled between the thermal stress buffer member and the insulating substrate to seal the semiconductor chip.
(2) The thermal stress buffer member is provided with a conductor post that passes through the top plate portion of the thermal stress buffer member and connects the semiconductor chip and the wiring lead material.

また、前記構成になる半導体装置の製造方法として、本発明によれば、炭素基材または金属基材に、これら基材よりも融点が低い低融点金属を浸透分散させて複合化した熱応力緩衝部材を構成し、該熱応力緩衝部材を前記半導体チップと前記配線リード材との間に介挿して接合するようにし（請求項４）、さらにこの熱応力緩衝部材に対して次記のような方法で導体ポストを形成し、半導体チップ，絶縁基板，配線リード材との接合を行うようにすることかできる。
（１）前記熱応力緩衝部材の基材に貫通孔を穿孔しておき、該基材に前記の低融点金属を浸透分散させて複合化する際に、前記貫通孔にも前記低融点金属を充填して前記半導体チップと前記配線リード材との間を接続するための導体ポストを形成する（請求項５）。
（２）前記熱応力緩衝部材を半導体チップに接合する際に、前記基材に前記低融点金属を浸透分散させて複合化させるとともに、前記低融点金属にて熱応力緩衝部材と半導体チップとを同時に接合させる（請求項６）。
（３）前記熱応力緩衝部材は、前記半導体チップに接合される天板部と前記絶縁基板上の導体パターンに接合される脚部を有し、該熱応力緩衝部材の基材に浸透分散させた前記低融点金属にて熱応力緩衝部材の天板部と前記半導体チップとの間、および前記応力緩衝部材の脚部と前記絶縁基板上の導体パターンとの間をそれぞれ接合させる（請求項７）。
（４）前記熱応力緩衝部材には半導体チップとの接合面域から外れた位置に樹脂注入孔を形成しておき、該樹脂注入孔を通じて前記熱応力緩衝部材と前記絶縁基板との間に絶縁性の樹脂を注入し、該樹脂により半導体チップを封止する（請求項８）。 In addition, as a method for manufacturing a semiconductor device having the above-described structure, according to the present invention, a thermal stress buffer obtained by compounding a carbon base material or a metal base material by infiltrating and dispersing a low melting point metal having a melting point lower than those of the base material. And a thermal stress buffer member interposed between the semiconductor chip and the wiring lead material (Claim 4), and the thermal stress buffer member as described below. A conductor post can be formed by a method, and a semiconductor chip, an insulating substrate, and a wiring lead material can be joined.
(1) When a through hole is drilled in the base material of the thermal stress buffer member and the low melting point metal is infiltrated and dispersed in the base material, the low melting point metal is also put into the through hole. A conductor post for filling and connecting between the semiconductor chip and the wiring lead material is formed.
(2) When joining the thermal stress buffer member to a semiconductor chip, the low melting point metal is infiltrated and dispersed into the base material to be combined, and the thermal stress buffer member and the semiconductor chip are combined with the low melting point metal. They are joined simultaneously (Claim 6).
(3) The thermal stress buffer member has a top plate portion bonded to the semiconductor chip and a leg portion bonded to the conductor pattern on the insulating substrate, and is permeated and dispersed in the base material of the thermal stress buffer member. Further, the low melting point metal is used to join the top portion of the thermal stress buffer member and the semiconductor chip, and the leg portion of the stress buffer member and the conductor pattern on the insulating substrate, respectively. ).
(4) A resin injection hole is formed in the thermal stress buffer member at a position deviating from a bonding surface area with the semiconductor chip, and insulation is provided between the thermal stress buffer member and the insulating substrate through the resin injection hole. Resin is injected, and the semiconductor chip is sealed with the resin.

上記した組立構造の半導体装置およびその製造方法によれば、次記の効果を奏する。
（１）絶縁基板上にマウントした半導体チップの上面主電極と配線リード材との間に前記した複合材の熱応力緩衝部材を介挿し、該熱応力緩衝部材と半導体チップおよび配線リード材との間を接合することにより、半導体チップと配線リード材との間にハイパワー動作に必要な通電，伝熱経路を確保しつつ、半導体チップと配線リード材との熱膨張差に起因して部品間の接合部に作用する熱応力を効果的に緩和できる。また、この熱応力緩衝部材は半導体チップに対しヒートスプレッダとして機能し、半導体チップの局部的な発熱集中を防ぐこともできる。 According to the semiconductor device having the above-described assembly structure and the manufacturing method thereof, the following effects can be obtained.
(1) The above-mentioned composite thermal stress buffer member is interposed between the upper surface main electrode of the semiconductor chip mounted on the insulating substrate and the wiring lead material, and the thermal stress buffer member, the semiconductor chip and the wiring lead material By joining the gaps between the components due to the difference in thermal expansion between the semiconductor chip and the wiring lead material while securing the energization and heat transfer paths necessary for high power operation between the semiconductor chip and the wiring lead material It is possible to effectively relieve the thermal stress acting on the joint. Further, this thermal stress buffer member functions as a heat spreader for the semiconductor chip, and can also prevent local concentration of heat generation of the semiconductor chip.

ここで、配線リード材などに用いられる金属（Ｃｕ，Ａｌ，Ｃｕ−Ａｌ合金など）に比べてヤング率が低い炭素基材（黒鉛）の焼結体を母材として、これに基材よりも融点の低い金属（Ｃｕ，Ａｌ，Ｃｕ−Ａｌ合金など）を浸透分散させた複合材で熱応力緩衝部材を構成することにより、半導体チップ／配線リード材の熱膨張差に起因する熱応力を緩衝部材が吸収して部品間の接合部に作用する熱応力を効果的に緩和できる。   Here, a sintered body of a carbon base material (graphite) having a Young's modulus lower than that of a metal (Cu, Al, Cu-Al alloy, etc.) used for a wiring lead material is used as a base material. The thermal stress buffer member is composed of a composite material in which a metal having a low melting point (Cu, Al, Cu-Al alloy, etc.) is dispersed and dispersed, thereby buffering the thermal stress caused by the difference in thermal expansion of the semiconductor chip / wiring lead material. It is possible to effectively relieve the thermal stress that the member absorbs and acts on the joint between the parts.

また、配線リード材などに用いられる金属に比べて線膨張係数が小さな低熱膨張金属基材低熱膨張金属（Ｍｏ，Ｗ，ＳｉＣなど）を基材とする焼結体を母材として、これに基材よりも融点の低い金属（Ｃｕ，Ａｌ，Ｃｕ−Ａｌ合金など）を浸透分散させた複合材で熱応力緩衝部材を構成することにより、半導体チップ／緩衝板，緩衝板／配線リード材の間の熱膨張差が縮小して、部品間の接合部に作用する熱応力を低減できる。これにより高い導電性と放熱性を確保してハイパワーな半導体装置の信頼性向上が図れる。
（２）前記の熱応力緩衝部材の形状を箱型形状として、その天板部を半導体チップの上面主電極に接合した上で、周縁の脚部を絶縁基板に接合したことにより、半導体チップの上面側から伝熱した熱を熱応力緩衝部材から絶縁基板を経て放熱用金属ベース（ヒートシンク）に逃がすことができてチップ上面側からの放熱性が向上する。また、箱型形状の内部に封止樹脂を充填して半導体チップを封止することで、半導体チップの表面電極に生じる放電，酸化による腐食劣化を防ぐとともに、半導体チップ／熱応力緩衝部材間の接合部の自由端に生じる歪み集中を封止樹脂で吸収緩和させることができる。
（３）さらに、本発明の製造方法において、熱応力緩衝部材の基材に貫通孔を穿孔しておき、該基材に前記の低融点金属を浸透分散させて複合化する際に、前記貫通孔にも前記低融点金属を充填させることで、半導体チップと配線リード材との間を接続するための導体ポストを同時に形成することができる。加えて、この熱応力緩衝部材を半導体チップに接合する際に、前記のように熱応力緩衝部材の基材に低融点金属を浸透分散させるようにすれば、熱応力緩衝部材の複合化と半導体チップとの接合を同時に行うことができて半導体装置の組立工程数削減化が図れる。 In addition, a low thermal expansion metal base material having a low coefficient of linear expansion compared to the metal used for the wiring lead material, etc. is based on a sintered body based on a low thermal expansion metal (Mo, W, SiC, etc.) as a base material. By forming a thermal stress buffer member with a composite material in which a metal having a melting point lower than that of the material (Cu, Al, Cu—Al alloy, etc.) is permeated and dispersed, the semiconductor chip / buffer plate, buffer plate / wiring lead material Thus, the thermal stress acting on the joint between the parts can be reduced. As a result, high conductivity and heat dissipation can be ensured and the reliability of a high-power semiconductor device can be improved.
(2) The shape of the thermal stress buffer member is a box shape, the top plate portion is bonded to the upper surface main electrode of the semiconductor chip, and the peripheral leg portion is bonded to the insulating substrate. The heat transferred from the upper surface side can be released from the thermal stress buffer member through the insulating substrate to the heat radiating metal base (heat sink), and the heat dissipation from the chip upper surface side is improved. In addition, by sealing the semiconductor chip by filling the inside of the box shape with a sealing resin, corrosion deterioration due to discharge and oxidation occurring on the surface electrode of the semiconductor chip is prevented, and between the semiconductor chip and the thermal stress buffer member The strain concentration generated at the free end of the joint can be absorbed and relaxed by the sealing resin.
(3) Furthermore, in the manufacturing method of the present invention, when the through hole is drilled in the base material of the thermal stress buffer member and the low melting point metal is infiltrated and dispersed in the base material, the penetration is made. By filling the hole with the low melting point metal, a conductor post for connecting the semiconductor chip and the wiring lead material can be formed at the same time. In addition, when joining the thermal stress buffer member to the semiconductor chip, if the low melting point metal is permeated and dispersed in the base material of the thermal stress buffer member as described above, the composite of the thermal stress buffer member and the semiconductor Bonding with the chip can be performed at the same time, and the number of assembly steps of the semiconductor device can be reduced.

以下、本発明の実施の形態を図１〜図３に示す実施例に基づいて説明する。なお、図１は半導体装置の組立構造を表す断面図、図２は図１における要部構造の分解斜視図、図３は半導体チップ（ＩＧＢＴ素子）のゲート電極の配線に関する応用実施例を示すものであり、図４と対応する部材には同じ符号を付してその機能説明は省略する。
図１において、放熱用金属ベース１をヒートシンクとして、その上に伝熱接合した絶縁基板２の上面側に分割形成した導体パターンには、半導体チップ（ＩＧＢＴ素子）３、半導体チップ３の上面主電極に接続する配線リード材５、および半導体チップ３と配線リード材５との間に介挿した熱応力緩衝部材９が個別にマウントされている。ここで、半導体チップ３／熱応力緩衝部材９の間，および熱応力緩衝部材９／配線リード材４の間を後記のような方法で接合し、半導体チップ３に対する上面主電極（エミッタ電極）の通電経路，およびチップ上面側からの放熱経路を形成している。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on the examples shown in FIGS. 1 is a cross-sectional view showing an assembly structure of a semiconductor device, FIG. 2 is an exploded perspective view of the main structure in FIG. 1, and FIG. 3 shows an application example relating to wiring of a gate electrode of a semiconductor chip (IGBT element). The members corresponding to those in FIG. 4 are denoted by the same reference numerals, and the functional description thereof is omitted.
In FIG. 1, a semiconductor chip (IGBT element) 3 and an upper surface main electrode of the semiconductor chip 3 are formed on a conductor pattern divided on the upper surface side of an insulating substrate 2 heat-transfer bonded on the metal base 1 for heat dissipation. The wiring lead material 5 connected to the semiconductor chip 3 and the thermal stress buffer member 9 interposed between the semiconductor chip 3 and the wiring lead material 5 are individually mounted. Here, the semiconductor chip 3 / thermal stress buffer member 9 and the thermal stress buffer member 9 / wiring lead material 4 are joined by the method as described later, and the upper surface main electrode (emitter electrode) of the semiconductor chip 3 is connected. An energization path and a heat dissipation path from the upper surface side of the chip are formed.

また、熱応力緩衝部材９は詳細を後記するように半導体チップ３を包囲する箱型形状になり、その内方には封止樹脂１２を充填して半導体チップ３を封止し、さらに熱応力緩衝部材９を取り囲んで外囲ケース５の内方に注入した封止樹脂１３でその外周域を封止している。
次に、上記した組立構造の各部詳細について説明する。まず、金属ベース１は裏面側に放熱フィン１ａを形成したＣｕ，Ａｌなどの金属体で、その上面に絶縁基板２が伝熱結合されている。なお、図示例の金属ベース１は、半導体チップ３，熱応力緩衝部材９をマウントする中央板部と、配線リード材４をマウントする外周枠部とに二分割して半導体チップ３の発熱が外周枠部側に直接伝熱するのを防ぐようにした上で、その裏面側に形成した放熱フィン１ａが外囲ケース５の底壁５ａを貫通して外部に突き出すように配置されており、さらに中央板部には冷媒流路１ｂを形成して半導体チップ３から伝熱して来る熱の放熱性を高めるようにしている。 Further, the thermal stress buffer member 9 has a box shape surrounding the semiconductor chip 3 as will be described in detail later. The inside of the thermal stress buffer member 9 is filled with a sealing resin 12 to seal the semiconductor chip 3, and further the thermal stress. The outer peripheral area is sealed with a sealing resin 13 that surrounds the buffer member 9 and is injected into the outer case 5.
Next, details of each part of the assembly structure described above will be described. First, the metal base 1 is a metal body such as Cu, Al or the like in which the heat dissipating fins 1a are formed on the back side, and the insulating substrate 2 is heat-transfer coupled to the upper surface thereof. In the illustrated example, the metal base 1 is divided into a central plate portion for mounting the semiconductor chip 3 and the thermal stress buffer member 9 and an outer peripheral frame portion for mounting the wiring lead material 4 so that the heat generated by the semiconductor chip 3 is The heat dissipating fins 1a formed on the back surface side of the frame case side are arranged so as to protrude through the bottom wall 5a of the outer case 5 and prevent the heat from being directly transferred to the frame side. A refrigerant passage 1b is formed in the central plate portion so as to improve the heat dissipation of heat transferred from the semiconductor chip 3.

一方、金属ベース１の上に載置した絶縁基板２は、その絶縁層が窒化珪素，窒化ホウ素，窒化アルミニウムなどのセラミックで、その上面側に分割形成した導体パターン２ｂ，２ｃは、半導体チップ３と熱膨張率が均衡する金属系複合材を銀ロウ付けなどして形成するか、線膨張率の比較的高いＣｕ，Ａｌ，Ａｇなどをパターンニングした上に線膨張係数の小さなＷ，Ｍｏを厚膜状にスパッタコートして形成している。なお、絶縁基板２の裏面に形成した導体パターンは銀ロウ，アルミ系ロウなどの高温ロウ材で金属ベース１と接合して伝熱的に一体化しており、そのロウ接合部を符号１０で表す。   On the other hand, the insulating substrate 2 placed on the metal base 1 has an insulating layer made of ceramic such as silicon nitride, boron nitride, or aluminum nitride, and the conductor patterns 2b and 2c formed separately on the upper surface side thereof are formed on the semiconductor chip 3. A metal-based composite material with a thermal expansion coefficient balanced with silver brazing is formed, or Cu, Al, Ag, etc. having a relatively high linear expansion coefficient are patterned, and then W and Mo having a small linear expansion coefficient are formed. A thick film is formed by sputter coating. The conductor pattern formed on the back surface of the insulating substrate 2 is joined to the metal base 1 with a high-temperature brazing material such as silver brazing or aluminum brazing, and is thermally integrated, and the brazing joint is denoted by reference numeral 10. .

また、配線リード材４は、図２で示すように平角導体（Ｃｕ）を逆Ｕ字形に屈曲形成したもので、その両端の脚部が前記した金属ベース１の外周枠部に絶縁基板２を介してロウ付けされており、この位置で配線リード材４の脚部と外部導出端子６との間がボンディングワイヤ７で接続されている。なお、図示例の配線リード材４には上方に起立して封止樹脂１３の外方に露呈する放熱フィン４ａを形成してパッケージ上面側からの放熱性を高めるようにしている。   Further, the wiring lead material 4 is formed by bending a rectangular conductor (Cu) into an inverted U shape as shown in FIG. 2, and the leg portions at both ends of the insulating substrate 2 are attached to the outer peripheral frame portion of the metal base 1 described above. The leg portion of the wiring lead material 4 and the external lead-out terminal 6 are connected by a bonding wire 7 at this position. In the illustrated example, the wiring lead material 4 is provided with heat radiating fins 4a that are erected upward and exposed to the outside of the sealing resin 13 so as to improve heat dissipation from the upper surface side of the package.

次に、熱応力緩衝部材９の詳細構造について述べる。すなわち、熱応力緩衝部材９は、配線リード材４などに用いられる金属（Ｃｕ，Ａｌ，Ｃｕ−Ａｌ合金など）に比べてヤング率が低い炭素基材（黒鉛），または線膨張係数が小さな低熱膨張金属基材（Ｍｏ，Ｗ，ＳｉＣなど）の多孔質な焼結体に、前記の基材よりも融点の低い金属（Ｃｕ，Ａｌ，Ｓｎ，Ａｇ，これら金属の合金など）を浸透分散させた複合材で構成されている。ここで、基材に浸透分散させる金属としては、高い導電性と高い伝熱性を有するものが望ましい。すなわち、浸透分散させる金属が基材となる材料に比べて導電性が高ければ、通電時の電気抵抗を基材単体で用いる場合に比べて低くすることができ、また伝熱性が高ければ、通電時に半導体チップ３が発する熱を放熱させるのに有利である。   Next, the detailed structure of the thermal stress buffer member 9 will be described. That is, the thermal stress buffer member 9 is a carbon base material (graphite) having a lower Young's modulus than a metal (Cu, Al, Cu—Al alloy, etc.) used for the wiring lead material 4 or the like, or a low heat having a small linear expansion coefficient. Metals (Cu, Al, Sn, Ag, alloys of these metals, etc.) having a melting point lower than that of the base material are permeated and dispersed in the porous sintered body of the expanded metal base material (Mo, W, SiC, etc.). Consists of composite materials. Here, as the metal to be permeated and dispersed in the base material, a metal having high conductivity and high heat conductivity is desirable. That is, if the metal to be permeated and dispersed is higher in conductivity than the material used as the base material, the electrical resistance during energization can be reduced as compared with the case where the base material is used alone, and if the heat conductivity is high, the electrical current is supplied. It is advantageous to dissipate heat sometimes generated by the semiconductor chip 3.

また、図２で示すように、熱応力緩衝部材９は半導体チップ３の上面および周囲を包囲するように天板部と周囲側壁で構成された箱型形状になり、その周縁脚部が絶縁基板２に形成した導体パターン２ｃに銀ロウ，アルミ系ロウ材などの高温ロウ材で接合されている。なお、そのロウ接合部を図１の符号１０で示す。
さらに、箱型形状になる前記熱応力緩衝部材９について、半導体チップ３の上面主電極（エミッタ電極）３ａと接合する天板部には、金属材の導体ポスト（ポスト状電極）９ａが天板部を貫通して分散形成されている。ここで導体ポスト９ａに用いる金属は、導電性，伝熱性の一方もしくは双方が前記基材に浸透分散された金属の導電性，伝熱性と同等以上のものが望ましい。 Further, as shown in FIG. 2, the thermal stress buffer member 9 has a box shape formed by a top plate portion and a peripheral side wall so as to surround the upper surface and the periphery of the semiconductor chip 3, and the peripheral leg portion is an insulating substrate. 2 is joined to the conductive pattern 2c formed in 2 by a high-temperature brazing material such as silver brazing or aluminum brazing. The solder joint is indicated by reference numeral 10 in FIG.
Further, with respect to the thermal stress buffer member 9 having a box shape, a metal material conductor post (post-shaped electrode) 9 a is provided on the top plate portion joined to the upper surface main electrode (emitter electrode) 3 a of the semiconductor chip 3. It is formed dispersed through the part. Here, it is desirable that the metal used for the conductor post 9a is one having one or both of conductivity and heat conductivity equal to or higher than the conductivity and heat conductivity of the metal infiltrated and dispersed in the base material.

この導体ポスト９ａを形成するには、例えば前記炭素基材もしくは前記焼結体の所定箇所（半導体チップ３のエミッタ電極との接合面域）にあらかじめ貫通孔を穿孔しておく。そして、前記炭素基材もしくは前記焼結体に金属を浸透分散させることにより、前記貫通孔に金属が充填れて導体ポスト９ａが同時に形成される。
また、熱応力緩衝部材９の天板部上面には、前記導体ポスト９ａの端面を含めて全域に導体層９ｂをパターン形成しており、さらに半導体チップ３との接合面域から外れた側方位置には封止樹脂１２を注入するための樹脂注入孔９ｃを開口している。なお、側壁面には半導体チップ３のゲート電極３ｂと外部導出端子６との間を接続するボンディングワイヤ７ａの通し穴９ｄを開口しておく。 In order to form the conductor post 9a, for example, a through hole is previously drilled in a predetermined portion of the carbon base material or the sintered body (a joint surface area with the emitter electrode of the semiconductor chip 3). Then, by penetrating and dispersing the metal into the carbon base material or the sintered body, the through hole is filled with the metal, and the conductor post 9a is simultaneously formed.
Further, on the top surface of the top portion of the thermal stress buffer member 9, a conductor layer 9b is patterned over the entire area including the end face of the conductor post 9a. A resin injection hole 9c for injecting the sealing resin 12 is opened at the position. A through hole 9d of a bonding wire 7a that connects between the gate electrode 3b of the semiconductor chip 3 and the external lead-out terminal 6 is opened on the side wall surface.

そして、組立工程では熱応力緩衝部材９の天板部と半導体チップ３の上面主電極３ａとの間を銀ロウ，アルミ系ロウなどの高温ロウ材で接合する。なお、ロウ付けする代わりに最近注目されている金属ナノ粒子ペーストを用いて接合してもよい。また、熱応力緩衝部材９の天板部上面にはその全面域に導体層９ｂをパターン形成した上で、その導体層９ｂの表面にＡｕ，Ａｇ，Ａｌなどを材料とする小径（数１０μｍ程度）なバンプ１１を分散形成しておく。そして、熱応力緩衝部材９の上に配線リード材４を重ねた状態で前記バンプ１１とリード材４とを超音波接合するか、もしくは側方から接合部にレーザー光を照射し、局部加熱して接合する。   In the assembly process, the top plate portion of the thermal stress buffer member 9 and the upper surface main electrode 3a of the semiconductor chip 3 are joined with a high-temperature brazing material such as silver brazing or aluminum brazing. In addition, you may join using the metal nanoparticle paste which attracts attention recently instead of brazing. Further, a conductor layer 9b is patterned on the entire top surface of the top surface of the top portion of the thermal stress buffer member 9, and the surface of the conductor layer 9b has a small diameter (approximately several tens μm) made of Au, Ag, Al or the like. ) Bumps 11 are formed in a distributed manner. Then, the bump 11 and the lead material 4 are ultrasonically bonded in a state where the wiring lead material 4 is superimposed on the thermal stress buffer member 9, or the joint is irradiated with laser light from the side to be locally heated. And join.

なお、熱応力緩衝部材９に導体ポスト９ａを形成する方法としては、炭素基材，金属基材を焼結する以前の前駆体（プリフォーム材）の状態で導体ポスト９ａの形成領域に多数の貫通穴を分散形成しておき、焼結後に行う前記低融点金属（フィラー）の浸透分散工程で同時に前記貫通穴に金属を含浸させ導体ポスト９ａを形成することかできる。もしくは、基材の焼結体に前記の低融点金属を浸透分散させた後に導体ポスト９ａの貫通穴を穿孔しておき、この熱応力緩衝部材９を半導体チップ３に接合する際に高温ロウ材を前記貫通穴に浸透させて導体ポスト９ａを形成すると同時に、この導体ポスト９ａを半導体チップ３の上面主電極３ａに接合することもできる。   In addition, as a method of forming the conductor post 9a on the thermal stress buffer member 9, a large number of conductor posts 9a are formed in the state of the precursor (preform material) before sintering the carbon base material and the metal base material. Through holes can be formed in a dispersed manner, and the metal posts can be simultaneously impregnated with the metal in the low melting point metal (filler) permeation dispersion step after sintering to form the conductor posts 9a. Alternatively, after the low melting point metal is infiltrated and dispersed in the sintered body of the base material, a through hole of the conductor post 9a is drilled, and when the thermal stress buffer member 9 is joined to the semiconductor chip 3, a high temperature brazing material is used. The conductor post 9a can be formed by penetrating the through hole into the through hole, and at the same time, the conductor post 9a can be joined to the upper surface main electrode 3a of the semiconductor chip 3.

また、半導体チップ３との接合後には、熱応力緩衝部材９の天板部に穿孔した樹脂注入穴９ｃを通じて半導体チップ３の周域に封止樹脂１２を注入する。この封止樹脂１２は、耐熱性を確保するためにＰＥＩ（ポリエーテルイミド），ＰＡＩ（ポリアミイミド），ＰＩ（ポリイミド）などの高耐熱性エンジニアリングプラスチックが好ましい。この封止樹脂１２の充填により、樹脂層が半導体チップ３を保護してチップ表面からの放電，および上面主電極の酸化腐食を防止するとともに、半導体チップ３／熱応力緩衝部材９間を接合したロウ接合部の周縁自由端に生じる歪の集中を分散緩和させることができる。なお、熱応力緩衝部材９を取り囲んで外囲ケース５の内方に充填した封止樹脂１３は、前記した封止樹脂１２に比べて耐熱温度の低い樹脂でよい。   Further, after joining with the semiconductor chip 3, the sealing resin 12 is injected into the peripheral area of the semiconductor chip 3 through the resin injection hole 9 c drilled in the top plate portion of the thermal stress buffer member 9. The sealing resin 12 is preferably a high heat resistant engineering plastic such as PEI (polyetherimide), PAI (polyamiimide), PI (polyimide) in order to ensure heat resistance. By filling the sealing resin 12, the resin layer protects the semiconductor chip 3 to prevent discharge from the chip surface and oxidative corrosion of the upper surface main electrode, and the semiconductor chip 3 / thermal stress buffer member 9 is joined. It is possible to disperse and relax the concentration of strain generated at the free edge of the solder joint. The sealing resin 13 that surrounds the thermal stress buffer member 9 and fills the inside of the outer case 5 may be a resin having a lower heat-resistant temperature than the sealing resin 12 described above.

上記の組立構造により、半導体チップ３と配線リード材（Ｃｕ）との間に介挿した熱応力緩衝部材９が次記のように機能し、半導体チップ３とリード材４との大きな熱膨張差による部品間接合部の熱応力を軽減する。
すなわち、熱応力緩衝板９を、配線リード材（Ｃｕ）４に比べてヤング率が低い炭素基材（黒鉛）の焼結体を母材とした複合材で構成すれば、半導体チップ３／配線リード材４の熱膨張差に起因する熱応力を低ヤング率の熱応力緩衝部材９が吸収してロウ接合部に作用する熱応力を緩和する。また、熱応力緩衝部材９を、配線リード材（Ｃｕ）４に比べて線膨張係数が小さい低熱膨張金属（Ｍｏ，Ｗ，ＳｉＣなど）の焼結体を母材とした複合材で構成すれば、半導体チップ３／熱応力緩衝部材９，および熱応力緩衝部材９／配線リード材４の間の熱膨張差が縮小し、この熱膨張差に起因して部品間のロウ付け接合部に作用する熱応力を低減してヒートサイクル耐性が向上する。しかも、熱応力緩衝部材９の基材（多孔質焼結体）には前記した良導電性，良伝熱性の低融点金属が浸透分散され、さらに半導体チップ３との間の接合面域には導体ポスト９ａが形成されている。これにより、半導体チップ３とリード材４との間に高い導電路と高い放熱経路が確保されとともに、熱応力緩衝部材９が半導体チップ３に対するヒートスプレッダとして機能してチップの局部的な温度上昇を緩和できる。 With the above assembly structure, the thermal stress buffer member 9 interposed between the semiconductor chip 3 and the wiring lead material (Cu) functions as follows, and a large thermal expansion difference between the semiconductor chip 3 and the lead material 4 Reduces the thermal stress at the joints between parts.
That is, if the thermal stress buffer plate 9 is made of a composite material using a sintered body of a carbon base material (graphite) whose Young's modulus is lower than that of the wiring lead material (Cu) 4, the semiconductor chip 3 / wiring The thermal stress due to the thermal expansion difference of the lead material 4 is absorbed by the thermal stress buffer member 9 having a low Young's modulus, and the thermal stress acting on the solder joint is relaxed. Further, if the thermal stress buffer member 9 is composed of a composite material whose base material is a sintered body of a low thermal expansion metal (Mo, W, SiC, etc.) having a smaller linear expansion coefficient than the wiring lead material (Cu) 4. The thermal expansion difference between the semiconductor chip 3 / thermal stress buffer member 9 and the thermal stress buffer member 9 / wiring lead material 4 is reduced, and acts on the brazed joint between components due to the thermal expansion difference. Reduces thermal stress and improves heat cycle resistance. In addition, the base material (porous sintered body) of the thermal stress buffer member 9 is infiltrated and dispersed with the above-described low-melting-point metal having good conductivity and good heat conductivity. Conductor posts 9a are formed. Thereby, a high conductive path and a high heat dissipation path are ensured between the semiconductor chip 3 and the lead material 4, and the thermal stress buffer member 9 functions as a heat spreader for the semiconductor chip 3 to alleviate a local temperature rise of the chip. it can.

また、熱応力緩衝部材９および配線リード材４はその脚部が絶縁基板２に接合されており、該絶縁基板２を介して金属ベース１と伝熱的に結合されている。これにより、半導体チップ３の上面側から熱応力緩衝部材９，配線リード材４に伝熱した熱は停滞なく金属ベース１に伝熱してここから外部に熱放散される。加えて配線リード材４の上面に放熱フィン４ａを形成しておくことで、上面側からの放熱性がより一層向上する。   Further, the leg portions of the thermal stress buffer member 9 and the wiring lead material 4 are bonded to the insulating substrate 2, and are thermally coupled to the metal base 1 through the insulating substrate 2. Thereby, the heat transferred from the upper surface side of the semiconductor chip 3 to the thermal stress buffer member 9 and the wiring lead material 4 is transferred to the metal base 1 without stagnation and is dissipated to the outside from here. In addition, by forming the radiation fins 4 a on the upper surface of the wiring lead material 4, the heat dissipation from the upper surface side is further improved.

なお、半導体装置を設置する周囲環境の制約から配線リード材５の放熱フィン４ａを風冷できないような場合には、放熱フィン４ａの相互間に水冷パイプなどの冷媒流路を圧入して液冷することも可能である。この場合には通電路となる配線リード材４と冷媒流路との間を電気的に絶縁するために、放熱フィン４ａの表面にはセラミック，樹脂などの絶縁材をコーティングしておくようにするのがよい。   If the heat radiation fins 4a of the wiring lead material 5 cannot be air-cooled due to restrictions in the surrounding environment where the semiconductor device is installed, a coolant channel such as a water-cooled pipe is pressed between the heat radiation fins 4a for liquid cooling. It is also possible to do. In this case, in order to electrically insulate between the wiring lead material 4 serving as an energization path and the refrigerant flow path, the surface of the radiation fin 4a is coated with an insulating material such as ceramic or resin. It is good.

また、以上述べた本発明による実施例の半導体装置は、図１に示した組立構造に限定されるものではなく、細部の構造において様々な変更が可能である。
例えば、図１の構造においては、半導体チップ３のゲート端子３ｂから引出したボンディングワイヤ７ａを熱応力緩衝部材９の側壁に開口した穴９ｄを通じて外部導出端子６に接続するようにしているが、熱応力緩衝部材９に穴９ｄを穿孔せずに、図３で示すようにゲート端子３ｂに接続したボンディングワイヤを７ａと７ｂとに分割した上で、ボンディングワイヤ７ａを熱応力緩衝部材９の内側で絶縁基板の導体パターン２ｃに接合し、他方の分割ボンディングワイヤ７ｂを熱応力緩衝部材９の外側で絶縁基板２の導体パターン２ｃと外部導出端子６との間に接続してもよい。 Further, the semiconductor device of the embodiment according to the present invention described above is not limited to the assembly structure shown in FIG. 1, and various modifications can be made in the detailed structure.
For example, in the structure of FIG. 1, the bonding wire 7 a drawn from the gate terminal 3 b of the semiconductor chip 3 is connected to the external lead-out terminal 6 through the hole 9 d opened in the side wall of the thermal stress buffer member 9. The hole 9d is not drilled in the stress buffer member 9, and the bonding wire connected to the gate terminal 3b is divided into 7a and 7b as shown in FIG. It may be joined to the conductor pattern 2 c of the insulating substrate, and the other divided bonding wire 7 b may be connected between the conductor pattern 2 c of the insulating substrate 2 and the external lead-out terminal 6 outside the thermal stress buffer member 9.

また、放熱用金属ベース１についても、放熱性に厳しい条件が課せられなければ、図示例のように半導体チップ２と熱応力緩衝部材９の脚部を搭載する中央板部と、配線リード材４の脚部を搭載する外周枠部とに分割せずに一枚板で構成してもよい。   As for the heat radiating metal base 1, if severe conditions are not imposed on the heat radiating property, the central plate portion on which the legs of the semiconductor chip 2 and the thermal stress buffer member 9 are mounted as shown in the example, and the wiring lead material 4. You may comprise with a single plate, without dividing | segmenting into the outer periphery frame part which mounts the leg part.

本発明の実施例による半導体デバイスの組立構造を示す断面図Sectional drawing which shows the assembly structure of the semiconductor device by the Example of this invention 図１における要部構造の分解斜視図1 is an exploded perspective view of the main part structure in FIG. 半導体チップのゲート電極に対する配線構造に関する図１と異なる実施例の配線構造を表す図The figure showing the wiring structure of the Example different from FIG. 1 regarding the wiring structure with respect to the gate electrode of a semiconductor chip 従来例の半導体デバイスの組立構造図Assembly structure diagram of conventional semiconductor device

符号の説明Explanation of symbols

１ 放熱用金属ベース
１ａ 放熱フィン
１ｂ 冷媒流路
２ 絶縁基板
２ｂ，２ｃ 上面側の導体パターン
３ 半導体チップ
３ａ 上面側主電極
４ 配線リード材
４ａ 放熱フィン
５ 外囲ケース
６ 外部導出端子
９ 熱応力緩衝部材
９ａ 導体ポスト
９ｂ 導体パターン
９ｃ 樹脂注入穴
１０ ロウ付け接合部
１１ バンプ
１２ 封止樹脂（内部側）
１３ 封止樹脂（外部側） DESCRIPTION OF SYMBOLS 1 Metal base for thermal radiation 1a Radiation fin 1b Refrigerant flow path 2 Insulating substrate 2b, 2c Conductor pattern on upper surface side 3 Semiconductor chip 3a Upper surface side main electrode 4 Wiring lead material 4a Radiation fin 5 Outer case 6 External lead terminal 9 Thermal stress buffer Member 9a Conductor post 9b Conductor pattern 9c Resin injection hole 10 Brazing joint 11 Bump 12 Sealing resin (inside)
13 Sealing resin (external side)

Claims (8)

放熱用金属ベースに伝熱接合した絶縁基板の上に半導体チップ、および該半導体チップの上面主電極に接続する配線リード材を搭載し、かつその周域を樹脂封止してなる半導体装置において、
炭素基材または金属基材に、これら基材よりも融点が低い低融点金属を浸透分散させて複合化した複合材からなる熱応力緩衝部材を、前記半導体チップと前記配線リード材との間に介挿して接合したことを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip and a wiring lead material connected to an upper surface main electrode of the semiconductor chip are mounted on an insulating substrate heat-transfer bonded to a heat radiating metal base, and the peripheral area thereof is resin-sealed.
A thermal stress buffer member made of a composite material obtained by infiltrating and dispersing a low melting point metal having a melting point lower than that of a base material into a carbon base material or a metal base material is interposed between the semiconductor chip and the wiring lead material. A semiconductor device characterized by being inserted and joined. 請求項１に記載の半導体装置において、
前記熱応力緩衝部材は、前記半導体チップおよび配線リード材に接合される天板部と、前記絶縁基板上の導体パターンに接合される脚部を有する箱型形状になり、該熱応力緩衝部材と前記絶縁基板との間に絶縁性の樹脂を充填して半導体チップを封止したことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The thermal stress buffer member has a box shape having a top plate portion bonded to the semiconductor chip and the wiring lead material, and a leg portion bonded to a conductor pattern on the insulating substrate, and the thermal stress buffer member; A semiconductor device, wherein an insulating resin is filled between the insulating substrate and a semiconductor chip is sealed. 請求項１に記載の半導体装置において、
前記熱応力緩衝部材は、該熱応力緩衝部材を貫通し前記半導体チップと前記配線リード材との間を接続する導体ポストを有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
The thermal stress buffer member includes a conductor post that penetrates the thermal stress buffer member and connects the semiconductor chip and the wiring lead material. 放熱用金属ベースに伝熱接合した絶縁基板の上に半導体チップ、および該半導体チップの上面主電極に接続する配線リード材を搭載し、かつその周域を樹脂封止してなる半導体装置の製造方法において、
炭素基材または金属基材に、これら基材よりも融点が低い低融点金属を浸透分散させて複合化した熱応力緩衝部材を構成し、該熱応力緩衝部材を前記半導体チップと前記配線リード材との間に介挿して接合することを特徴とする半導体装置の製造方法。 Manufacturing of a semiconductor device in which a semiconductor chip and a wiring lead material connected to an upper surface main electrode of the semiconductor chip are mounted on an insulating substrate thermally conductively bonded to a heat radiating metal base, and the peripheral area thereof is resin-sealed In the method
A thermal stress buffer member is formed by infiltrating and dispersing a low melting point metal having a melting point lower than that of the base material into a carbon base material or a metal base material, and the thermal stress buffer member is constituted by the semiconductor chip and the wiring lead material. A method for manufacturing a semiconductor device, comprising: 請求項４に記載の半導体装置の製造方法において、
前記熱応力緩衝部材の基材に貫通孔を穿孔しておき、該基材に前記の低融点金属を浸透分散させて複合化する際に、前記貫通孔にも前記低融点金属を充填して前記半導体チップと前記配線リード材との間を接続するための導体ポストを形成することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4,
When a through hole is drilled in the base material of the thermal stress buffer member and the low melting point metal is infiltrated and dispersed in the base material, the through hole is filled with the low melting point metal. A method of manufacturing a semiconductor device, comprising: forming a conductor post for connecting between the semiconductor chip and the wiring lead material. 請求項４または５に記載の半導体装置の製造方法において、
前記熱応力緩衝部材を半導体チップに接合する際に、前記基材に前記低融点金属を浸透分散させて複合化させ、同時にこの低融点金属にて熱応力緩衝部材と半導体チップとを接合することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4 or 5,
When bonding the thermal stress buffer member to the semiconductor chip, the low melting point metal is infiltrated and dispersed into the base material to be combined, and at the same time, the thermal stress buffer member and the semiconductor chip are bonded with the low melting point metal. A method of manufacturing a semiconductor device. 請求項６に記載の半導体装置の製造方法において、
前記熱応力緩衝部材は、前記半導体チップに接合される天板部と前記絶縁基板上の導体パターンに接合される脚部を有し、該熱応力緩衝部材の基材に浸透分散させた前記低融点金属にて熱応力緩衝部材の天板部と前記半導体チップとの間、および前記応力緩衝部材の脚部と前記絶縁基板上の導体パターンとの間をそれぞれ接合することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 6,
The thermal stress buffer member includes a top plate portion bonded to the semiconductor chip and a leg portion bonded to a conductor pattern on the insulating substrate, and the low-temperature stress buffer member is permeated and dispersed in a base material of the thermal stress buffer member. A semiconductor device characterized in that a melting point metal is used to join a top plate portion of a thermal stress buffer member and the semiconductor chip, and a leg portion of the stress buffer member and a conductor pattern on the insulating substrate, respectively. Manufacturing method. 請求項７に記載の半導体装置の製造方法において、
前記熱応力緩衝部材には半導体チップとの接合面域から外れた位置に樹脂注入孔を形成しておき、該樹脂注入孔を通じて前記熱応力緩衝部材と前記絶縁基板との間に絶縁性の樹脂を注入し、該樹脂により半導体チップを封止することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
In the thermal stress buffer member, a resin injection hole is formed at a position deviated from the bonding surface area with the semiconductor chip, and an insulating resin is interposed between the thermal stress buffer member and the insulating substrate through the resin injection hole. And a semiconductor chip is sealed with the resin.
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