JP2003188318A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2003188318A
JP2003188318A JP2001385791A JP2001385791A JP2003188318A JP 2003188318 A JP2003188318 A JP 2003188318A JP 2001385791 A JP2001385791 A JP 2001385791A JP 2001385791 A JP2001385791 A JP 2001385791A JP 2003188318 A JP2003188318 A JP 2003188318A
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JP
Japan
Prior art keywords
resin
conductor
semiconductor chip
electrode block
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001385791A
Other languages
Japanese (ja)
Other versions
JP3719506B2 (en
Inventor
Takanori Tejima
孝紀 手嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2001385791A priority Critical patent/JP3719506B2/en
Priority to US10/321,365 priority patent/US6693350B2/en
Publication of JP2003188318A publication Critical patent/JP2003188318A/en
Application granted granted Critical
Publication of JP3719506B2 publication Critical patent/JP3719506B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a joint member from adhering to the surfaces of conductor members, etc., those contact with resin, in a semiconductor device and its manufacturing method. <P>SOLUTION: In the semiconductor device, a first coating resin 14 is preapplied to side faces of electrode blocks 3 as a means for preventing the adhesion of the joint member. Therefore, solder 6 does not adhere to the side faces of the blocks 3 even when the solder 6 creeps up the side faces due to the own weights of members 1-5 when the members 1-5 are joined to each other with the solder 6, because the resin 14 has a nonadhesive property to the solder 6. Since the solder 6 is not interposed between the side faces of the electrode blocks 3 and a second coating resin 15, the adhesion between the side faces of the blocks 3 and the resin 15 can be maintained even when a heat cycle is applied. Consequently, the peeling of a resin 9 from the electrode blocks 3 can be prevented. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップの両
面が導体部材と電気的に接続された構成を有する半導体
装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which both sides of a semiconductor chip are electrically connected to conductor members and a method for manufacturing the same.

【０００２】[0002]

【従来技術】半導体チップの表裏両面から放熱するとと
もに表裏両面に電流を流す構成の半導体装置として、図
４に示す概略断面図のような構成が考えられる。2. Description of the Related Art As a semiconductor device having a structure in which heat is radiated from both front and back surfaces of a semiconductor chip and a current is supplied to both front and back surfaces, a structure as shown in a schematic sectional view of FIG.

【０００３】この図４に示されるように、この半導体装
置は、２つの半導体チップ１０１、１０２を並列接続し
つつ、第１の導体部材（電極ブロック）１０３及び第３
の導体部材１０５と第２の導体部材１０４との間に、こ
れら２つの半導体チップ１０１、１０２を狭持して、第
２の導体部材１０４と第３の導体部材１０５との間を樹
脂１０９でモールドしたものである。As shown in FIG. 4, in this semiconductor device, two semiconductor chips 101 and 102 are connected in parallel while a first conductor member (electrode block) 103 and a third conductor member 103 are provided.
The two semiconductor chips 101 and 102 are sandwiched between the conductor member 105 and the second conductor member 104, and the resin 109 is provided between the second conductor member 104 and the third conductor member 105. It is molded.

【０００４】そして、これら２つの半導体チップとして
は、例えば、絶縁ゲート型バイポーラトランジスタ（Ｉ
ＧＢＴ：Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａ
ｒＴｒａｎｓｉｓｔｏｒ）が形成された半導体チップ
（以下、ＩＧＢＴチップと略す）１０１とフライホイー
ルダイオード（ＦＷＤ：Ｆｒｅｅ ＷｈｅｅｌｉｎｇＤ
ｉｏｄｅ）が形成された半導体チップ（以下、ＦＷＤチ
ップと略す）１０２とを用いることができる。As these two semiconductor chips, for example, an insulated gate bipolar transistor (I
GBT: Insulated Gate Bipolar
A semiconductor chip (hereinafter, abbreviated as an IGBT chip) 101 having an rTransistor formed therein and a flywheel diode (FWD: Free Wheeling D).
A semiconductor chip (hereinafter, abbreviated as FWD chip) 102 having an iode) can be used.

【０００５】また、上記第１の導体部材１０３は、半導
体チップ１０１、１０２の素子形成面（表面）１０１
ａ、１０２ａにそれぞれ配置されている。The first conductor member 103 is an element forming surface (front surface) 101 of the semiconductor chips 101 and 102.
a and 102a, respectively.

【０００６】尚、この第１の導体部材１０３のうち、Ｉ
ＧＢＴチップ１０１の表面１０１ａに配置された第１の
導体部材１０３は、後述するボンディングワイヤ１０８
が設けられる領域を確保するために設けられており、一
方、ＦＷＤチップ１０２の表面１０２ａに配置された第
１の導体部材１０３は、後述する第３の導体部材１０５
が傾かないように高さを調整するために設けられてい
る。Of the first conductor member 103, I
The first conductor member 103 arranged on the front surface 101a of the GBT chip 101 includes a bonding wire 108 described later.
The first conductor member 103 provided on the front surface 102a of the FWD chip 102 is provided to secure a region in which the third conductor member 105 described later is provided.
It is provided to adjust the height so that it does not tilt.

【０００７】また、上記第２の導体部材１０４は、ＩＧ
ＢＴチップ１０１の裏面１０１ｂ（コレクタ）及びＦＷ
Ｄチップ１０２の裏面１０２ｂ（カソード）に接続され
ており、上記第３の導体部材１０５は、ＩＧＢＴチップ
１０１の表面１０１ａ（エミッタ）及びＦＷＤチップ１
０２の表面１０２ａ（アノード）に接続されている。The second conductor member 104 is an IG
Back side 101b (collector) and FW of BT chip 101
The third conductor member 105 is connected to the back surface 102b (cathode) of the D chip 102, and the third conductor member 105 includes the front surface 101a (emitter) of the IGBT chip 101 and the FWD chip 1.
02 surface 102a (anode).

【０００８】これらの第１〜第３の導体部材１０３〜１
０５は、半導体チップ１０１、１０２からの放熱を行う
と同時に、半導体チップ１０１、１０２との電気的な経
路となっている。These first to third conductor members 103 to 1
Reference numeral 05 serves as an electrical path to the semiconductor chips 101 and 102, while radiating heat from the semiconductor chips 101 and 102.

【０００９】従って、放熱性を確保し電気抵抗を小さく
するために、半導体チップ１０１、１０２と第１〜第３
の導体部材１０３〜１０５とは、電気伝導性及び熱伝導
性を有するはんだ（接合部材）１０６により接合されて
いる。Therefore, in order to secure heat dissipation and reduce electric resistance, the semiconductor chips 101 and 102 and the first to third semiconductor chips are connected.
The conductor members 103 to 105 are joined by a solder (joint member) 106 having electrical conductivity and thermal conductivity.

【００１０】また、図示しないが、ＩＧＢＴチップ１０
１の表面１０１ａの所望の位置に形成されたゲート電極
は、ボンディングワイヤ１０８により制御用端子１０７
に電気的に接続されている。Although not shown, the IGBT chip 10 is also provided.
The gate electrode formed at a desired position on the front surface 101a of the No. 1 is connected to the control terminal 107 by the bonding wire 108.
Electrically connected to.

【００１１】そして、第２及び第３の導体部材１０４、
１０５のうちの半導体チップ１０１、１０２又は第１の
導体部材１０３と接合されている面とは反対側の面１０
４ｂ、１０５ａが露出するようにして、半導体チップ１
０１、１０２、第１〜第３の導体部材１０３〜１０５、
制御用端子１０７及びボンディングワイヤ１０８が樹脂
１０９により封止されている。The second and third conductor members 104,
The surface 10 of the side 105 opposite to the surface bonded to the semiconductor chips 101, 102 or the first conductor member 103.
4b and 105a are exposed so that the semiconductor chip 1
01, 102, first to third conductor members 103 to 105,
The control terminal 107 and the bonding wire 108 are sealed with resin 109.

【００１２】さらに、第２及び第３の導体部材１０４、
１０５のうちの樹脂１０９から露出した部位、即ち、第
２の導体部材１０４の裏面１０４ｂ及び第３の導体部材
１０５の表面１０５ａを冷却部材（図示せず）などに当
接させて、半導体チップ１０１、１０２からの放熱を促
進している。Further, the second and third conductor members 104,
A portion of the semiconductor chip 105 exposed from the resin 109, that is, the back surface 104b of the second conductor member 104 and the front surface 105a of the third conductor member 105 is brought into contact with a cooling member (not shown) or the like, and the semiconductor chip 101 , 102 to promote heat dissipation.

【００１３】しかしながら、このような半導体装置にお
いては、半導体チップ１０１、１０２及び第１〜第３の
導体部材１０３〜１０５と樹脂１０９との熱膨張係数の
差が大きいため、熱サイクルを加えたときに両者の接触
部に大きな熱応力が作用し、この熱応力が樹脂１０９の
密着力よりも大きくなると、半導体チップ１０１、１０
２及び第１〜第３の導体部材１０３〜１０５から樹脂１
０９が剥離してしまうことがある。However, in such a semiconductor device, there is a large difference in the coefficient of thermal expansion between the semiconductor chips 101, 102 and the first to third conductor members 103 to 105 and the resin 109, and therefore, when a thermal cycle is applied. When a large thermal stress acts on the contact portion between the two, and this thermal stress becomes larger than the adhesive force of the resin 109, the semiconductor chips 101, 10
2 and the resin 1 from the first to third conductor members 103 to 105
09 may be peeled off.

【００１４】そして、半導体チップ１０１、１０２及び
第１〜第３の導体部材１０３〜１０５から樹脂１０９が
剥離すると、各部材１０１〜１０５の間を接合している
はんだ１０６に大きなストレスがかかるようになり、急
激にはんだ１０６が劣化してしまう。この傾向は、温度
差が大きいほど顕著である。When the resin 109 is peeled off from the semiconductor chips 101 and 102 and the first to third conductor members 103 to 105, a great stress is applied to the solder 106 joining the members 101 to 105. Then, the solder 106 deteriorates rapidly. This tendency becomes more remarkable as the temperature difference increases.

【００１５】そこで、樹脂１０９の剥離を防止する対策
として、各部材１０１〜１０５と樹脂１０９の密着力を
強くする対策が考えられる。Therefore, as a measure for preventing the resin 109 from peeling off, a measure for increasing the adhesion between the members 101 to 105 and the resin 109 can be considered.

【００１６】この対策として、各部材１０１〜１０５に
おける樹脂１０９と接触する面に、樹脂１０９との密着
性を高めるコーティング樹脂１１０（図４中のやや太い
実線参照）を塗布することが考えられている。As a countermeasure against this, it is conceivable to apply a coating resin 110 (see a slightly thick solid line in FIG. 4) to the surface of each of the members 101 to 105 that comes into contact with the resin 109, which enhances the adhesion to the resin 109. There is.

【００１７】[0017]

【発明が解決しようとする課題】しかしながら、上記従
来技術のような半導体装置においては、各部材１０１〜
１０５の間をはんだ１０６によって接合する際に、これ
ら各部材１０１〜１０５の自重により、半導体チップ１
０１、１０２や第１の導体部材１０３などの側面にはん
だ１０６が這い上がってしまい、そして、半導体チップ
１０１、１０２や第１の導体部材１０３などの側面には
んだ１０６が付着してしまうことがある。However, in the semiconductor device as in the above-mentioned prior art, each member 101-
When the portions 105 are joined by the solder 106, the weight of the respective members 101 to 105 is reduced by the weight of the semiconductor chips 1 to 105.
In some cases, the solder 106 may crawl onto the side surface of the semiconductor chip 101, 102, the first conductor member 103, or the like, and the solder 106 may adhere to the side surface of the semiconductor chip 101, 102, the first conductor member 103, or the like. .

【００１８】それにより、コーティング樹脂１１０と半
導体チップ１０１、１０２や第１の導体部材１０３など
の側面との間には、はんだ１０６が介在してしまうこと
になる。As a result, the solder 106 will be interposed between the coating resin 110 and the side surfaces of the semiconductor chips 101 and 102, the first conductor member 103, and the like.

【００１９】このような状態で半導体装置に熱サイクル
を加えると、一般的にはんだ１０６は強度の弱い材質で
あるため、はんだ１０６が半導体チップ１０１、１０２
及び第１の導体部材１０３若しくはコーティング樹脂１
１０から剥離してしまう。When the semiconductor device is subjected to a thermal cycle in such a state, the solder 106 is generally a material having low strength, so that the solder 106 is not bonded to the semiconductor chips 101 and 102.
And the first conductor member 103 or the coating resin 1
It peels from 10.

【００２０】はんだ１０６が半導体チップ１０１、１０
２及び第１の導体部材１０３若しくはコーティング樹脂
１１０から剥離してしまうと、半導体チップ１０１、１
０２及び第１の導体部材１０３から樹脂１０９が剥離し
てしまうことになる。The solder 106 is the semiconductor chip 101, 10
2 and the first conductor member 103 or the coating resin 110, the semiconductor chips 101, 1
02 and the first conductor member 103, the resin 109 is peeled off.

【００２１】そして、半導体チップ１０１、１０２及び
第１の導体部材１０３から樹脂１０９が剥離すると、前
述のように、各部材１０１〜１０５の間を接合している
はんだ１０６に大きなストレスがかかるようになり、急
激にはんだ１０６が劣化してしまう。When the resin 109 is peeled off from the semiconductor chips 101 and 102 and the first conductor member 103, a large stress is applied to the solder 106 joining the members 101 to 105 as described above. Then, the solder 106 deteriorates rapidly.

【００２２】そこで、本発明の目的は、上記問題点に鑑
み、半導体装置及びその製造方法において、導体部材等
における樹脂と接触する面に接合部材が付着してしまう
ことを防止することにある。Therefore, in view of the above problems, it is an object of the present invention to prevent the joining member from adhering to the surface of the conductor member or the like that comes into contact with the resin in the semiconductor device and the manufacturing method thereof.

【００２３】[0023]

【課題を解決するための手段】請求項１に記載の半導体
装置は、一方の導体部材と、この導体部材の上に接合部
材を介して接続された半導体チップと、この半導体チッ
プの上に接合部材を介して接続された他方の導体部材と
を備え、２つの導体部材の間を樹脂で封止してなる半導
体装置において、半導体チップまたは導体部材の少なく
ともどちらか一方における樹脂と接触する面には、予め
接合部材付着防止手段が設けられていることを特徴とし
ている。According to another aspect of the present invention, there is provided a semiconductor device, wherein one conductor member, a semiconductor chip connected to the conductor member via a bonding member, and the semiconductor chip bonded to the semiconductor chip are bonded to each other. In a semiconductor device including the other conductor member connected via a member and sealing between the two conductor members with a resin, the surface of at least one of the semiconductor chip and the conductor member that contacts the resin Is characterized in that a joining member adhesion preventing means is provided in advance.

【００２４】請求項１に記載の発明によれば、接合部材
によって半導体チップと２つの導体部材とを接合する際
に、半導体チップや導体部材における樹脂と接触する面
に接合部材が付着してしまうことを防止できるため、そ
れにより、半導体チップや導体部材と樹脂との間には接
合部材が介在しないので、半導体チップや導体部材と樹
脂との密着力を保つことができる。According to the first aspect of the invention, when the semiconductor chip and the two conductor members are joined by the joining member, the joining member adheres to the surface of the semiconductor chip or the conductor member that comes into contact with the resin. Since this can be prevented, the bonding member is not interposed between the semiconductor chip or the conductor member and the resin, so that the adhesive force between the semiconductor chip or the conductor member and the resin can be maintained.

【００２５】請求項２に記載の半導体装置は、２つの導
体部材の少なくともどちらか一方は、半導体チップと接
合される面に設けられた電極ブロックを備えており、電
極ブロックにおける樹脂と接触する面には、予め接合部
材付着防止手段が設けられていることを特徴としてい
る。According to another aspect of the semiconductor device of the present invention, at least one of the two conductor members is provided with an electrode block provided on the surface to be joined to the semiconductor chip, and the surface of the electrode block that contacts the resin. Is characterized in that a joining member adhesion preventing means is provided in advance.

【００２６】請求項２に記載の発明によれば、接合部材
によって電極ブロックと半導体チップ及び導体部材とを
接合する際に、電極ブロックにおける樹脂と接触する面
に接合部材が付着してしまうことを防止できるため、そ
れにより、電極ブロックと樹脂との間には接合部材が介
在しないので、電極ブロックと樹脂との密着力を保つこ
とができる。According to the second aspect of the present invention, when the electrode block is joined to the semiconductor chip and the conductor member by the joining member, the joining member adheres to the surface of the electrode block which comes into contact with the resin. Since this can be prevented, a bonding member is not interposed between the electrode block and the resin, so that the adhesive force between the electrode block and the resin can be maintained.

【００２７】請求項３に記載の半導体装置は、接合部材
付着防止手段は、半導体チップまたは導体部材の少なく
ともどちらか一方における樹脂と接触する面に予め塗布
されたコーティング樹脂であるため、請求項１または２
と同様の効果を得ることができる。According to a third aspect of the present invention, in the semiconductor device according to the third aspect, the joining member adhesion preventing means is a coating resin previously applied to a surface of at least one of the semiconductor chip and the conductor member which comes into contact with the resin. Or 2
The same effect as can be obtained.

【００２８】請求項４に記載の半導体装置は、接合部材
付着防止手段は、半導体チップまたは導体部材の少なく
ともどちらか一方における樹脂と接触する面に予め設け
られた凹凸であるため、請求項１または２と同様の効果
を得ることができる。In the semiconductor device according to a fourth aspect of the present invention, the joining member adhesion preventing means is an unevenness provided in advance on the surface of at least one of the semiconductor chip and the conductor member that comes into contact with the resin. The same effect as that of 2 can be obtained.

【００２９】請求項５乃至７に記載の半導体装置は、半
導体チップは、それぞれ並列に接続された複数の半導体
チップから構成されており、これら複数の半導体チップ
として、少なくともＩＧＢＴチップと還流用ダイオード
またはＭＯＳＦＥＴチップを用いたことを特徴としてい
る。In the semiconductor device according to any one of claims 5 to 7, the semiconductor chip is composed of a plurality of semiconductor chips connected in parallel, and as the plurality of semiconductor chips, at least an IGBT chip and a freewheeling diode or It is characterized by using a MOSFET chip.

【００３０】請求項５乃至７に記載のような構成の半導
体装置において、上記請求項１乃至４に記載のような構
成を適用すると、上記請求項１乃至４と同様の効果を得
ることができる。When the structure as described in any one of claims 1 to 4 is applied to the semiconductor device having the structure as described in any one of claims 5 to 7, the same effects as those in any one of claims 1 to 4 can be obtained. .

【００３１】請求項８に記載の半導体装置の製造方法
は、半導体チップと接合される面に設けられた電極ブロ
ックを少なくともどちらか一方が備えた２つの導体部材
を用意し、電極ブロックを備えた導体部材または半導体
チップの少なくともどちらか一方における側面に接合部
材付着防止手段を設ける第１の工程と、半導体チップを
接合部材を介して２つの導体部材の間に介在されるよう
に配置するとともに、接合部材により２つの導体部材と
半導体チップとを接合する第２の工程と、２つの導体部
材の間を樹脂により封止する第３の工程とを備えたこと
を特徴としている。According to the eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein two conductor members, at least one of which is provided with an electrode block provided on a surface to be joined to a semiconductor chip, are prepared, and the electrode block is provided. A first step of providing a joining member adhesion preventing means on a side surface of at least one of the conductor member and the semiconductor chip; and arranging the semiconductor chip so as to be interposed between the two conductor members via the joining member, The method is characterized by including a second step of joining the two conductor members and the semiconductor chip with a joining member, and a third step of sealing between the two conductor members with a resin.

【００３２】請求項８に記載の発明のよれば、第２の工
程を実行した際に、半導体チップや導体部材における側
面に接合部材が付着してしまうことを防止できるため、
それにより、半導体チップや導体部材の側面と樹脂との
間には接合部材が介在しないので、半導体チップや導体
部材と樹脂との密着力を保つことができる。According to the eighth aspect of the present invention, it is possible to prevent the bonding member from adhering to the side surface of the semiconductor chip or the conductor member when the second step is executed.
As a result, since no joining member is interposed between the side surface of the semiconductor chip or the conductor member and the resin, the adhesive force between the semiconductor chip or the conductor member and the resin can be maintained.

【００３３】請求項９に記載の半導体装置の製造方法
は、半導体チップの一方の面に接合される電極ブロック
と少なくともどちらか一方が電極ブロックと接合される
２つの導体部材を用意し、電極ブロックまたは半導体チ
ップの少なくともどちらか一方における側面に接合部材
付着防止手段を設ける第１の工程と、半導体チップ及び
電極ブロックを接合部材を介して２つの導体部材の間に
介在されるように配置するとともに、接合部材により２
つの導体部材と半導体チップ及び電極ブロックとを接合
する第２の工程と、２つの導体部材の間を樹脂により封
止する第３の工程とを備えたことを特徴としている。According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an electrode block bonded to one surface of a semiconductor chip and two conductor members at least one of which is bonded to the electrode block are prepared. Alternatively, the semiconductor chip and the electrode block may be arranged so as to be interposed between the two conductor members with the joining member interposed between the first step of providing the joining member adhesion preventing means on the side surface of at least one of the semiconductor chips. , 2 depending on the joining member
The method is characterized by including a second step of joining one conductor member to the semiconductor chip and the electrode block, and a third step of sealing between the two conductor members with a resin.

【００３４】請求項９に記載の発明によれば、第２の工
程を実行した際に、半導体チップや電極ブロックにおけ
る側面に接合部材が付着してしまうことを防止できるた
め、それにより、半導体チップや電極ブロックの側面と
樹脂との間には接合部材が介在しないので、半導体チッ
プや電極ブロックと樹脂との密着力を保つことができ
る。According to the invention described in claim 9, it is possible to prevent the bonding member from adhering to the side surface of the semiconductor chip or the electrode block when the second step is executed. Since there is no bonding member between the side surface of the electrode block and the resin and the resin, the adhesive force between the semiconductor chip and the electrode block and the resin can be maintained.

【００３５】請求項１０に記載の半導体装置の製造方法
は、第２の工程後であって第３の工程前に、２つの導体
部材または半導体チップまたは電極ブロックの少なくと
も何れか１つにおける樹脂と接触する面にコーティング
樹脂を塗布する工程を実行することを特徴としている。According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device, the resin in at least one of the two conductor members or the semiconductor chip or the electrode block is included after the second step and before the third step. The method is characterized in that the step of applying the coating resin to the contact surface is executed.

【００３６】請求項１０に記載の発明によれば、２つの
導体部材の間を樹脂により封止する第３の工程前に、２
つの導体部材や半導体チップや電極ブロックにおける樹
脂と接触する面にコーティング樹脂を塗布する工程を実
行しているため、半導体チップ及び導体部材及び電極ブ
ロックと樹脂との密着力を向上させることができる。According to the tenth aspect of the invention, before the third step of sealing the space between the two conductor members with the resin, 2
Since the step of applying the coating resin to the surface of one conductor member, the semiconductor chip or the electrode block which is in contact with the resin is performed, the adhesive force between the resin and the semiconductor chip, the conductor member or the electrode block can be improved.

【００３７】[0037]

【発明の実施の形態】以下、本発明を具体化した一実施
形態を、図面に従って説明する。 （第１実施形態）図１には、本発明の第１実施形態に係
る半導体装置の概略断面図を示す。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a schematic sectional view of a semiconductor device according to the first embodiment of the present invention.

【００３８】この図１に示されるように、本実施形態の
半導体装置は、２つの半導体チップ１、２を並列接続し
つつ、電極ブロック（従来技術でいう、第１の導体部
材）３及び第３の導体部材５と第２の導体部材４との間
に各半導体チップ１、２を狭持して、第２の導体部材４
と第３の導体部材５との間を樹脂９でモールドしたもの
である。As shown in FIG. 1, in the semiconductor device of this embodiment, two semiconductor chips 1 and 2 are connected in parallel while an electrode block (first conductor member in the prior art) 3 and a first conductor member 3 are connected. The semiconductor chips 1 and 2 are sandwiched between the conductor member 5 of No. 3 and the second conductor member 4, and the second conductor member 4
A resin 9 is formed between the second conductive member 5 and the third conductive member 5.

【００３９】そして、本実施形態では、半導体チップと
して、絶縁ゲート型バイポーラトランジスタ（ＩＧＢ
Ｔ：Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ
Ｔｒａｎｓｉｓｔｏｒ）が形成された半導体チップ（以
下、ＩＧＢＴチップと略す）１とフライホイールダイオ
ード（ＦＷＤ：Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄ
ｅ）が形成された半導体チップ（以下、ＦＷＤチップと
略す）２とを用いている。尚、これらの各半導体チップ
１、２は、主としてシリコンからなり、厚みは０．５ｍ
ｍ程度である。In this embodiment, the semiconductor chip is an insulated gate bipolar transistor (IGB).
T: Insulated Gate Bipolar
A semiconductor chip (hereinafter abbreviated as an IGBT chip) 1 on which a transistor (Transistor) is formed and a flywheel diode (FWD: Free Wheeling Diode).
The semiconductor chip (hereinafter abbreviated as FWD chip) 2 on which e) is formed is used. Each of these semiconductor chips 1 and 2 is mainly made of silicon and has a thickness of 0.5 m.
It is about m.

【００４０】以下、各半導体チップ１、２の外表面のう
ち、素子形成面側の面を表面１ａ、２ａといい、この表
面１ａ、２ａとは反対側の面を裏面１ｂ、２ｂという。Of the outer surfaces of the semiconductor chips 1 and 2, hereinafter, the surfaces on the element formation surface side are referred to as the front surfaces 1a and 2a, and the surfaces opposite to the front surfaces 1a and 2a are referred to as the back surfaces 1b and 2b.

【００４１】尚、図示しないが、ＩＧＢＴチップ１の表
面１ａにはエミッタ電極、ゲート電極が形成されてお
り、裏面１ｂにはコレクタ電極が形成されている。Although not shown, an emitter electrode and a gate electrode are formed on the front surface 1a of the IGBT chip 1, and a collector electrode is formed on the back surface 1b.

【００４２】各半導体チップ１、２の表面１ａ、２ａに
は、電気伝導性を有する接合部材としてのはんだ６を介
して、その側面に接合部材付着防止手段として第１のコ
ーティング樹脂１４が塗布された電極ブロック３の裏面
３ｂが接合されている。尚、この第１のコーティング樹
脂１４としては、ポリアミド樹脂やポリイミド樹脂、ア
ミド樹脂などを用いることができる。The surfaces 1a, 2a of the respective semiconductor chips 1, 2 are coated with a first coating resin 14 as a bonding member adhesion preventing means on the side surfaces thereof via a solder 6 as a bonding member having electrical conductivity. The back surface 3b of the electrode block 3 is joined. As the first coating resin 14, polyamide resin, polyimide resin, amide resin or the like can be used.

【００４３】この電極ブロック３のうち、ＩＧＢＴチッ
プ１の表面１ａに配置された電極ブロック３は、後述す
るボンディングワイヤ８が設けられる領域を確保するた
めに設けられており、一方、ＦＷＤチップ２の表面２ａ
に配置された電極ブロック３は、後述する第３の導体部
材５が傾かないように高さを調整するために設けられて
いる。Of this electrode block 3, the electrode block 3 arranged on the surface 1a of the IGBT chip 1 is provided to secure a region where a bonding wire 8 described later is provided, while the electrode block 3 of the FWD chip 2 is provided. Surface 2a
The electrode block 3 arranged at is provided for adjusting the height so that the third conductor member 5 described later does not tilt.

【００４４】また、この電極ブロック３のうち、ＩＧＢ
Ｔチップ１と電極ブロック３との接合面積は、ＩＧＢＴ
チップ１のエミッタ電極とほぼ同じ大きさになってい
る。ここで、ほぼ同じ大きさとは、エミッタ電極と可能
な限り大きな面積で接合し、且つＩＧＢＴチップ１のエ
ミッタ電極の外側に形成され電極ブロック３とは電気的
に接続したくない部位とは接合されないようにすること
を示す。ここで、電極ブロック３とは電気的に接続した
くない部位とは、ＩＧＢＴチップ１の表面１ａにおい
て、電極ブロック３と接触すると、電極ブロック３を介
してエミッタ電極と同電位になってしまい不具合を生じ
る部位のことを示す。Of the electrode block 3, IGB
The bonding area between the T chip 1 and the electrode block 3 is
It has almost the same size as the emitter electrode of the chip 1. Here, “having almost the same size” does not mean that it is joined to the emitter electrode in the largest possible area and is not joined to a portion which is formed outside the emitter electrode of the IGBT chip 1 and which is not desired to be electrically connected to the electrode block 3. Show that you do. Here, the part that is not desired to be electrically connected to the electrode block 3 is the same potential as the emitter electrode through the electrode block 3 when it contacts the electrode block 3 on the surface 1a of the IGBT chip 1. Indicates the site where

【００４５】従って、ＩＧＢＴチップ１と電極ブロック
３との接合面積を、ＩＧＢＴチップ１のエミッタ電極と
ほぼ同じ大きさにすることにより、好適にＩＧＢＴチッ
プ１と電極ブロック３とを接合することができる。Therefore, by setting the bonding area between the IGBT chip 1 and the electrode block 3 to be approximately the same size as the emitter electrode of the IGBT chip 1, the IGBT chip 1 and the electrode block 3 can be bonded appropriately. .

【００４６】また、各半導体チップ１、２の裏面１ｂ、
２ｂには、電気伝導性を有する接合部材としてのはんだ
６を介して、第２の導体部材４の表面４ａが接合（電気
的に接続）されており、電極ブロック３の裏面３ｂとは
反対側の面である表面３ａには、電気伝導性を有する接
合部材としてのはんだ６を介して、第３の導体部材５の
裏面５ｂが接合（電気的に接続）されている。Further, the back surfaces 1b of the semiconductor chips 1 and 2,
The front surface 4a of the second conductor member 4 is bonded (electrically connected) to 2b via a solder 6 as a bonding member having electrical conductivity, and the surface opposite to the back surface 3b of the electrode block 3 is provided. The back surface 5b of the third conductor member 5 is bonded (electrically connected) to the front surface 3a which is the surface of the third conductive member 5 via the solder 6 as a bonding member having electrical conductivity.

【００４７】電極ブロック３としては、電気導電性を有
する金属部材を用いることができ、本実施形態では、電
極ブロック３としてＣｕを用いており、第２及び第３の
導体部材４、５としてＣｕ合金を用いている。A metal member having electrical conductivity can be used as the electrode block 3, and Cu is used as the electrode block 3 in the present embodiment, and Cu is used as the second and third conductor members 4 and 5. It uses an alloy.

【００４８】また、図示しないが、ＩＧＢＴチップ１の
表面１ａの所望の位置に形成されたゲート電極は、ボン
ディングワイヤ８により制御用端子７と電気的に接続さ
れている。Although not shown, the gate electrode formed at a desired position on the surface 1a of the IGBT chip 1 is electrically connected to the control terminal 7 by the bonding wire 8.

【００４９】そして、各半導体チップ１、２、電極ブロ
ック３、第２の導体部材４の表面４ａ、第３の導体部材
５の裏面５ｂ、ボンディングワイヤ８、及び制御用端子
７の一部が、一括して樹脂９により封止されている。Then, each of the semiconductor chips 1, 2, the electrode block 3, the front surface 4a of the second conductor member 4, the back surface 5b of the third conductor member 5, the bonding wire 8, and a part of the control terminal 7 are It is collectively sealed with resin 9.

【００５０】これにより、第２の導体部材４の裏面４ｂ
と第３の導体部材５の表面５ａ、及び制御用端子７の一
部が露出した状態で各部材１〜８が封止された構成とな
っている。この樹脂９としては、例えば、エポキシ系モ
ールド樹脂を用いることができる。尚、この場合、各部
材１〜８を樹脂９でモールドするに当たっては、上下型
からなる成形型（図示しない）を使用している。As a result, the back surface 4b of the second conductor member 4 is formed.
And each member 1 to 8 is sealed with the surface 5a of the third conductor member 5 and a part of the control terminal 7 exposed. As the resin 9, for example, an epoxy type molding resin can be used. In this case, when molding the members 1 to 8 with the resin 9, a molding die (not shown) composed of upper and lower dies is used.

【００５１】また、樹脂９と第２及び第３の導体部材
４、５との密着力、樹脂９と各半導体チップ１、２との
密着力、並びに、樹脂９と電極ブロック３との密着力を
強くするために、上記樹脂９をモールドする前に、各部
材１〜５における樹脂９と接触する面には、第２のコー
ティング樹脂１５（図１中のやや太い実線参照）が塗布
されている。尚、この第２のコーティング樹脂１５とし
ては、前述の第１のコーティング樹脂１４と同様に、ポ
リアミド樹脂やポリイミド樹脂、アミド樹脂などを用い
ることができる。Further, the adhesive force between the resin 9 and the second and third conductor members 4, 5, the adhesive force between the resin 9 and each semiconductor chip 1, 2, and the adhesive force between the resin 9 and the electrode block 3. In order to strengthen the resin, the second coating resin 15 (see a slightly thick solid line in FIG. 1) is applied to the surfaces of the members 1 to 5 that come into contact with the resin 9 before the resin 9 is molded. There is. As the second coating resin 15, similarly to the first coating resin 14 described above, a polyamide resin, a polyimide resin, an amide resin, or the like can be used.

【００５２】このようにして、本実施形態の半導体装置
が構成されており、この半導体装置では、各半導体チッ
プ１、２からの発熱を、熱伝導性にも優れたはんだ６を
介して電極ブロック３と第２及び第３の導体部材４、５
に伝え、第２の導体部材４の裏面４ｂ及び第３の導体部
材５の表面５ａから放熱を行うことができるようになっ
ている。In this way, the semiconductor device of this embodiment is constructed. In this semiconductor device, the heat generated from each of the semiconductor chips 1 and 2 is passed through the electrode block through the solder 6 having excellent thermal conductivity. 3 and second and third conductor members 4, 5
The heat can be radiated from the back surface 4b of the second conductor member 4 and the front surface 5a of the third conductor member 5.

【００５３】さらに、第２及び第３の導体部材４、５の
うちの樹脂９から露出した部位、即ち、第２の導体部材
４の裏面４ｂ及び第３の導体部材５の表面５ａを冷却部
材（図示せず）などに当接させて、各半導体チップ１、
２からの放熱を促進している。Further, the portions of the second and third conductor members 4, 5 exposed from the resin 9, that is, the back surface 4b of the second conductor member 4 and the front surface 5a of the third conductor member 5 are cooled. Each semiconductor chip 1 is brought into contact with (not shown) or the like.
It promotes heat dissipation from 2.

【００５４】このように、本実施形態では、接合部材付
着防止手段として、予め電極ブロック３の側面には第１
のコーティング樹脂１４が塗布されているので、各部材
１〜５の間をはんだ６によって接合する際に、これら各
部材１〜５の自重などによって、電極ブロック３の側面
にはんだ６が這い上がったとしても、第１のコーティン
グ樹脂１４ははんだ６と密着しない材質であるため、電
極ブロック３の側面にはんだ６が付着することはない。As described above, in this embodiment, the first side surface of the electrode block 3 is preliminarily provided on the side surface of the electrode block 3 as the joining member adhesion preventing means.
Since the coating resin 14 is applied, the solder 6 creeps up on the side surface of the electrode block 3 due to the weight of each of the members 1 to 5 when joining the members 1 to 5 with the solder 6. Even so, since the first coating resin 14 is a material that does not adhere to the solder 6, the solder 6 does not adhere to the side surface of the electrode block 3.

【００５５】それにより、電極ブロック３の側面と第２
のコーティング樹脂１５との間にははんだ６が介在しな
いので、このような状態で半導体装置に熱サイクルを加
えたとしても、電極ブロック３の側面と第２のコーティ
ング樹脂１５との密着力を保つことができるため、電極
ブロック３から樹脂９が剥離してしまうことを防止でき
る。As a result, the side surface of the electrode block 3 and the second
Since the solder 6 is not interposed between the second coating resin 15 and the coating resin 15, the adhesive force between the side surface of the electrode block 3 and the second coating resin 15 is maintained even if a thermal cycle is applied to the semiconductor device in such a state. Therefore, the resin 9 can be prevented from peeling off from the electrode block 3.

【００５６】よって、各部材１〜５の間を接合している
はんだ６には大きなストレスがかかることを解消できる
ので、はんだ６の劣化を防止することができる。Therefore, since it is possible to prevent a large stress from being applied to the solder 6 joining the members 1 to 5, deterioration of the solder 6 can be prevented.

【００５７】次に、上記構成の半導体装置の製造方法に
ついて、本製造方法を概略断面図にて示す工程図である
図２を参照して説明する。Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIG. 2 which is a process diagram showing the manufacturing method in a schematic sectional view.

【００５８】まず、第２及び第３の導体部材４、５を板
状のＣｕ合金部材などからパンチングなどにより形成す
る。また、電極ブロック３と同等の面積であるととも
に、予めその側面に接合部材付着防止として第１のコー
ティング樹脂１４が塗布された柱状のＣｕ部材を用意し
て、このＣｕ部材から電極ブロック３と同等の厚みのＣ
ｕ部材を形成することにより、側面に第１のコーティン
グ樹脂１４が塗布された電極ブロック３が完成する。First, the second and third conductor members 4 and 5 are formed from a plate-shaped Cu alloy member or the like by punching or the like. In addition, a columnar Cu member having an area equal to that of the electrode block 3 and having the first coating resin 14 applied to its side surface in advance to prevent the attachment of the bonding member is prepared, and this Cu member is equivalent to the electrode block 3. Thickness of C
By forming the u member, the electrode block 3 having the side surface coated with the first coating resin 14 is completed.

【００５９】続いて、図２（ａ）に示されるように、第
２の導体部材４の表面４ａ上にはんだ６を介して各半導
体チップ１、２を接合する。次に、各半導体チップ１、
２の表面１ａ、２ａ上にはんだ６を介して電極ブロック
３を接合する。これにより、図２（ａ）に示す状態とな
り、このものをワーク１０とする。Subsequently, as shown in FIG. 2A, the semiconductor chips 1 and 2 are bonded onto the surface 4a of the second conductor member 4 via the solder 6. Next, each semiconductor chip 1,
The electrode block 3 is bonded to the surfaces 1a and 2a of the second electrode 2 with solder 6 interposed therebetween. As a result, the state shown in FIG. 2A is obtained, and this is the work 10.

【００６０】その後、図示していないが、ＩＧＢＴチッ
プ１と制御用端子７とをボンディングワイヤ８により電
気的に接続する。Thereafter, although not shown, the IGBT chip 1 and the control terminal 7 are electrically connected by the bonding wire 8.

【００６１】次に、図２（ｂ）に示されるように、第３
の導体部材５の裏面５ｂを上にして治具１１上に搭載
し、第３の導体部材５の裏面５ｂの所望の位置にはんだ
６を配設し、上記図２（ａ）に示すワーク１０を裏返し
にして第３の導体部材５上に搭載する。Next, as shown in FIG. 2B, the third
2 is mounted on the jig 11 with the back surface 5b of the conductor member 5 facing upward, and the solder 6 is arranged at a desired position on the back surface 5b of the third conductor member 5, and the work 10 shown in FIG. Is turned over and mounted on the third conductor member 5.

【００６２】さらに、第２の導体部材４の裏面４ｂ上に
板状の重り１２を載せる。また、治具１１には、第２及
び第３の導体部材４、５間の距離を規定するために一定
の高さを持ったスペーサ１３が備えられる。この状態が
図２（ｂ）に示す状態である。そして、この状態で加熱
炉などに入れてはんだ６をリフローさせる。Further, a plate-shaped weight 12 is placed on the back surface 4b of the second conductor member 4. Further, the jig 11 is provided with a spacer 13 having a constant height for defining the distance between the second and third conductor members 4, 5. This state is the state shown in FIG. Then, in this state, the solder 6 is reflowed by placing it in a heating furnace or the like.

【００６３】その結果、重り１２によりワーク１０が加
圧され、図２（ｃ）に示されるように、はんだ６が押し
つぶされ、第３の導体部材５の裏面５ｂと第２の導体部
材４の表面４ａとの距離がスペーサ１３の高さになる。
これにより、第２の導体部材４と第３の導体部材５の平
行度が調整される。As a result, the work piece 10 is pressed by the weight 12, the solder 6 is crushed, and the back surface 5b of the third conductor member 5 and the second conductor member 4 are crushed, as shown in FIG. 2 (c). The distance from the surface 4a is the height of the spacer 13.
Thereby, the parallelism between the second conductor member 4 and the third conductor member 5 is adjusted.

【００６４】続いて、図示しないが、各半導体チップ
１、２、第２及び第３の導体部材４、５、電極ブロック
３における樹脂９と接触する面に、第２のコーティング
樹脂１５を塗布する。この場合、例えばディッピング
（浸漬）により塗布しても良いし、コーティング樹脂塗
布用のディスペンサのノズルから滴下（または噴霧）す
ることにより塗布しても良い。尚、制御用端子７やボン
ディングワイヤ８の表面にも、コーティング樹脂を塗布
しておくことが好ましい。Next, although not shown, the second coating resin 15 is applied to the surfaces of the respective semiconductor chips 1, 2, the second and third conductor members 4, 5, and the electrode block 3 which are in contact with the resin 9. . In this case, for example, the coating may be performed by dipping (immersion), or may be applied by dropping (or spraying) from a nozzle of a dispenser for coating resin. In addition, it is preferable to apply a coating resin also to the surfaces of the control terminals 7 and the bonding wires 8.

【００６５】その後、上記図１に示されるように、樹脂
９によって各部材１〜８を封止することによって半導体
装置が完成する。Thereafter, as shown in FIG. 1, each member 1-8 is sealed with resin 9 to complete the semiconductor device.

【００６６】（第２実施形態）図３に本発明の第２実施
形態に係る半導体装置装置の概略断面図を示す。(Second Embodiment) FIG. 3 shows a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.

【００６７】本実施形態の半導体装置の構成は、上記第
１実施形態とほぼ同様であるため、第１実施形態と同等
な構成については同様の符号を付し、異なる部分につい
てのみ説明する。Since the structure of the semiconductor device of this embodiment is almost the same as that of the first embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and only different portions will be described.

【００６８】図３に示されるように、本実施形態では、
接合部材付着防止手段として、予め電極ブロック３の側
面には凹凸が設けられている。As shown in FIG. 3, in the present embodiment,
As a joining member adhesion preventing means, unevenness is provided on the side surface of the electrode block 3 in advance.

【００６９】それによって、各部材１〜５の間をはんだ
６によって接合する際に、これら各部材１〜５の自重に
より、電極ブロック３の側面にはんだ６が這い上がった
としても、少なくとも電極ブロック３の側面に設けられ
た凸部にははんだ６が這い上がってこないので、電極ブ
ロック３の側面に設けられた凸部にはんだ６が付着する
ことはない。As a result, when joining the members 1 to 5 with the solder 6, even if the solder 6 creeps up on the side surface of the electrode block 3 due to the weight of the members 1 to 5, at least the electrode block 3 Since the solder 6 does not creep up to the convex portion provided on the side surface of the electrode 3, the solder 6 does not adhere to the convex portion provided on the side surface of the electrode block 3.

【００７０】それにより、電極ブロック３の側面に設け
られた凸部と第２のコーティング樹脂１５との間にはは
んだ６が介在しないので、このような状態で半導体装置
に熱サイクルを加えたとしても、電極ブロック３の側面
に設けられた凸部と第２のコーティング樹脂１５との間
の密着力を保つことができるため、電極ブロック３から
樹脂９が剥離してしまうことを防止できる。As a result, the solder 6 does not intervene between the convex portion provided on the side surface of the electrode block 3 and the second coating resin 15. Therefore, if the semiconductor device is subjected to a thermal cycle in such a state. Also, since the adhesion between the convex portion provided on the side surface of the electrode block 3 and the second coating resin 15 can be maintained, it is possible to prevent the resin 9 from peeling off from the electrode block 3.

【００７１】よって、各部材１〜５の間を接合している
はんだ６に大きなストレスがかかることを解消できるの
で、はんだ６の劣化を防止することができる。Therefore, it is possible to prevent a large stress from being applied to the solder 6 joining the members 1 to 5, so that the deterioration of the solder 6 can be prevented.

【００７２】（他の実施形態）また、上記第１実施形態
と第２実施形態とを組み合わせてもよい。(Other Embodiments) Further, the first embodiment and the second embodiment may be combined.

【００７３】つまり、第１実施形態のように、電極ブロ
ック３の側面に予め第１のコーティング樹脂１４を塗布
しつつ、第２実施形態のように、電極ブロック３の側面
に凹凸を設けた構成としてもよい。それによって、上記
両実施形態の効果を発揮することができる。That is, as in the first embodiment, the first coating resin 14 is applied to the side surface of the electrode block 3 in advance, and the side surface of the electrode block 3 is provided with irregularities as in the second embodiment. May be Thereby, the effects of both of the above-described embodiments can be exhibited.

【００７４】尚、本発明は、上記各実施形態に限られる
ものではなく、様々な態様に適用可能である。The present invention is not limited to the above embodiments, but can be applied to various aspects.

【００７５】例えば、上記各実施形態では、各部材１〜
５の間をはんだ６によって接合した後に、各部材１〜５
における樹脂９と接触する面に第２のコーティング樹脂
１５を塗布しているが、これに限られるものではなく、
各部材１〜５における樹脂９と接触する面に第２のコー
ティング樹脂１５を塗布した後に、各部材１〜５の間を
はんだ６によって接合してもよい。それにより、各部材
１〜５の間をはんだ６によって接合する際に、各部材１
〜５における樹脂９と接触する面にはんだ６が付着して
しまうことを防止できるため、各部材１〜５と樹脂９と
の密着力を保つことができる。For example, in each of the above embodiments, each member 1 to
After joining between 5 by solder 6, each member 1-5
The second coating resin 15 is applied to the surface that contacts the resin 9 in, but the present invention is not limited to this.
The second coating resin 15 may be applied to the surfaces of the members 1 to 5 that come into contact with the resin 9, and then the members 1 to 5 may be joined by the solder 6. Thereby, when joining the members 1 to 5 with the solder 6, each member 1
Since it is possible to prevent the solder 6 from adhering to the surfaces of the members 5 to 5 that come into contact with the resin 9, the adhesion between the members 1 to 5 and the resin 9 can be maintained.

【００７６】また、上記各実施形態では、電極ブロック
３の側面のみに接合部材付着防止手段を設けたが、これ
に限られるものではなく、半導体チップ１、２や第２の
導体部材４、第３の導体部材５における第２のコーティ
ング樹脂１５が塗布される面にも接合部材付着防止手段
を設けてもよい。Further, in each of the above-mentioned embodiments, the bonding member adhesion preventing means is provided only on the side surface of the electrode block 3, but the invention is not limited to this, and the semiconductor chips 1, 2 and the second conductor member 4, Bonding member adhesion preventing means may be provided also on the surface of the third conductor member 5 to which the second coating resin 15 is applied.

【００７７】また、上記第１実施形態では、第２のコー
ティング樹脂１５を電極ブロック３における樹脂９と接
触する面にも塗布しているが、この面には予め第１のコ
ーティング樹脂１４が塗布されているので、この面には
第２のコーティング樹脂１５を塗布しなくてもよい。In the first embodiment, the second coating resin 15 is also applied to the surface of the electrode block 3 that contacts the resin 9. However, the first coating resin 14 is applied to this surface in advance. Therefore, it is not necessary to apply the second coating resin 15 to this surface.

【００７８】また、上記各実施形態では、接合部材とし
ては、はんだ６を用いる例について示したが、これに限
られるものではなく、その他にＡｇペーストなどを用い
ることができる。また、各接合部材として必ずしも同一
のものを用いなくてもよい。Further, in each of the above-mentioned embodiments, the example in which the solder 6 is used as the joining member has been shown, but the joining member is not limited to this, and Ag paste or the like may be used. Further, the same bonding member does not necessarily have to be used.

【００７９】また、上記各実施形態では、半導体チップ
として、ＩＧＢＴチップ１とＦＷＤチップ２とを用いた
構成について説明したが、これに限定されるものではな
く、半導体チップとして、その内部にＦＷＤチップと同
様の作用を有するＭＯＳＦＥＴチップを用いた構成にも
適用できる。Further, in each of the above-described embodiments, the configuration using the IGBT chip 1 and the FWD chip 2 as the semiconductor chip has been described, but the present invention is not limited to this, and the FWD chip inside the semiconductor chip is not limited to this. It can also be applied to a configuration using a MOSFET chip having the same operation as.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施形態の半導体装置の概略断面
図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】図１に示す半導体装置の製造方法を示す工程図
である。FIG. 2 is a process drawing showing the manufacturing method of the semiconductor device shown in FIG.

【図３】本発明の第２実施形態の半導体装置の概略断面
図である。FIG. 3 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.

【図４】従来技術の半導体装置の概略断面図である。FIG. 4 is a schematic cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１…ＩＧＢＴチップ（半導体チップ）、 ２…ＦＷＤチップ（半導体チップ）、 ３…電極ブロック（第１の導体部材）、 ４…第２の導体部材、 ５…第３の導体部材、 １ａ、２ａ、３ａ、４ａ、５ａ…各部材の表面、 １ｂ、２ｂ、３ｂ、４ｂ、５ｂ…各部材の裏面、 ６…はんだ（接合部材）、 ７…制御用端子、 ８…ボンディングワイヤ、 ９…樹脂、 １０…ワーク、 １２…重り、 １３…スペーサ、 １４…第１のコーティング樹脂、 １５…第２のコーティング樹脂。 1 ... IGBT chip (semiconductor chip), 2 ... FWD chip (semiconductor chip), 3 ... Electrode block (first conductor member), 4 ... a second conductor member, 5 ... Third conductor member, 1a, 2a, 3a, 4a, 5a ... Surface of each member, 1b, 2b, 3b, 4b, 5b ... the back surface of each member, 6 ... Solder (joint member), 7 ... Control terminal, 8 ... Bonding wire, 9 ... Resin, 10 ... work, 12 ... weight, 13 ... Spacer, 14 ... First coating resin, 15 ... Second coating resin.

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 一方の導体部材と、この導体部材の上に
接合部材を介して接続された半導体チップと、この半導
体チップの上に接合部材を介して接続された他方の導体
部材とを備え、前記２つの導体部材の間を樹脂で封止し
てなる半導体装置において、 前記半導体チップまたは前記導体部材の少なくともどち
らか一方における前記樹脂と接触する面には、予め接合
部材付着防止手段が設けられていることを特徴とする半
導体装置。1. A conductor member, a semiconductor chip connected to the conductor member via a joining member, and another conductor member connected to the semiconductor chip via a joining member. In a semiconductor device in which a space between the two conductor members is sealed with a resin, a bonding member adhesion preventing means is provided in advance on a surface of at least one of the semiconductor chip and the conductor member that comes into contact with the resin. A semiconductor device characterized by being provided. 【請求項２】 前記２つの導体部材の少なくともどちら
か一方は、前記半導体チップと接合される面に設けられ
た電極ブロックを備えており、前記電極ブロックにおけ
る前記樹脂と接触する面には、予め接合部材付着防止手
段が設けられていることを特徴とする請求項１に記載の
半導体装置。2. At least one of the two conductor members includes an electrode block provided on a surface to be joined to the semiconductor chip, and a surface of the electrode block that comes into contact with the resin is previously formed. The semiconductor device according to claim 1, further comprising a bonding member adhesion preventing unit. 【請求項３】 前記接合部材付着防止手段は、前記半導
体チップまたは前記導体部材の少なくともどちらか一方
における前記樹脂と接触する面に予め塗布されたコーテ
ィング樹脂であることを特徴とする請求項１または２に
記載の半導体装置。3. The bonding member adhesion preventing means is a coating resin applied in advance to a surface of at least one of the semiconductor chip and the conductor member that comes into contact with the resin. 2. The semiconductor device according to item 2. 【請求項４】 前記接合部材付着防止手段は、前記半導
体チップまたは前記導体部材の少なくともどちらか一方
における前記樹脂と接触する面に予め設けられた凹凸で
あることを特徴とする請求項１乃至３の何れか１つに記
載の半導体装置。4. The bonding member adhesion preventing means is an unevenness provided in advance on a surface of at least one of the semiconductor chip and the conductor member which comes into contact with the resin. The semiconductor device according to any one of 1. 【請求項５】 前記半導体チップは、それぞれ並列に接
続された複数の半導体チップから構成されていることを
特徴とする請求項１乃至４の何れか１つに記載の半導体
装置。5. The semiconductor device according to claim 1, wherein the semiconductor chip is composed of a plurality of semiconductor chips connected in parallel. 【請求項６】 前記複数の半導体チップとして、少なく
ともＩＧＢＴチップと還流用ダイオードを用いたことを
特徴とする請求項１乃至５の何れか１つに記載の半導体
装置。6. The semiconductor device according to claim 1, wherein at least an IGBT chip and a free wheeling diode are used as the plurality of semiconductor chips. 【請求項７】 前記複数の半導体チップとして、少なく
ともＭＯＳＦＥＴチップを用いたことを特徴とする請求
項１乃至６の何れか１つに記載の半導体装置。7. The semiconductor device according to claim 1, wherein at least MOSFET chips are used as the plurality of semiconductor chips. 【請求項８】 半導体チップと接合される面に設けられ
た電極ブロックを少なくともどちらか一方が備えた２つ
の導体部材を用意し、前記電極ブロックを備えた導体部
材または前記半導体チップの少なくともどちらか一方に
おける側面に接合部材付着防止手段を設ける第１の工程
と、 前記半導体チップを接合部材を介して前記２つの導体部
材の間に介在されるように配置するとともに、前記接合
部材により前記２つの導体部材と前記半導体チップとを
接合する第２の工程と、 前記２つの導体部材の間を樹脂により封止する第３の工
程とを備えたことを特徴とする半導体装置の製造方法。8. A two conductor member, at least one of which is provided with an electrode block provided on a surface to be joined to a semiconductor chip, is prepared, and at least one of the conductor member having the electrode block and the semiconductor chip is prepared. A first step of providing a joining member adhesion preventing means on one side surface; and arranging the semiconductor chip so as to be interposed between the two conductor members via a joining member, and by the joining member, A method of manufacturing a semiconductor device, comprising: a second step of joining a conductor member and the semiconductor chip together; and a third step of sealing between the two conductor members with a resin. 【請求項９】 半導体チップの一方の面に接合される電
極ブロックと少なくともどちらか一方が前記電極ブロッ
クと接合される２つの導体部材を用意し、前記電極ブロ
ックまたは前記半導体チップの少なくともどちらか一方
における側面に接合部材付着防止手段を設ける第１の工
程と、 前記半導体チップ及び前記電極ブロックを接合部材を介
して前記２つの導体部材の間に介在されるように配置す
るとともに、前記接合部材により前記２つの導体部材と
前記半導体チップ及び前記電極ブロックとを接合する第
２の工程と、 前記２つの導体部材の間を樹脂により封止する第３の工
程とを備えたことを特徴とする半導体装置の製造方法。9. An electrode block bonded to one surface of a semiconductor chip and two conductor members, at least one of which is bonded to the electrode block, are prepared, and at least one of the electrode block and the semiconductor chip. A first step of providing a joining member adhesion preventing means on a side surface of the semiconductor chip and the electrode block so as to be interposed between the two conductor members via a joining member, and by the joining member. A semiconductor comprising: a second step of joining the two conductor members to the semiconductor chip and the electrode block; and a third step of sealing between the two conductor members with a resin. Device manufacturing method. 【請求項１０】 前記第２の工程後であって前記第３の
工程前に、前記２つの導体部材または前記半導体チップ
または前記電極ブロックの少なくとも何れか１つにおけ
る前記樹脂と接触する面にコーティング樹脂を塗布する
工程を実行することを特徴とする請求項８または９に記
載の半導体装置の製造方法。10. The surface of the at least one of the two conductor members, the semiconductor chip, or the electrode block that comes into contact with the resin is coated after the second step and before the third step. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of applying a resin is performed.
JP2001385791A 1999-11-24 2001-12-19 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3719506B2 (en)

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