JP2001308263A - Semiconductor switching module and semiconductor device using it - Google Patents

Semiconductor switching module and semiconductor device using it

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JP2001308263A
JP2001308263A JP2000118093A JP2000118093A JP2001308263A JP 2001308263 A JP2001308263 A JP 2001308263A JP 2000118093 A JP2000118093 A JP 2000118093A JP 2000118093 A JP2000118093 A JP 2000118093A JP 2001308263 A JP2001308263 A JP 2001308263A
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side plate
semiconductor
side
le
high
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JP4192396B2 (en )
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Yasuyuki Okochi
靖之 大河内
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Denso Corp
株式会社デンソー
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a double side cooling type semiconductor device which can be remarkably cooled from both sides of a semiconductor chip. SOLUTION: In the semiconductor switching module with a built-in inverter circuit where a semiconductor chip 4a on a high side and a semiconductor chip 4b on a low side are serially connected, a configuration wherein a high side plate 1, a low side plate 2 and a middle plate 3 sandwich semiconductor chips 4a, 4b is adopted, the middle plate 3 is used as a common member, and the high side plate 1 and the low side plate 2 are arranged on the same side. As a result, the semiconductor switching module for the inverter circuit can be made compact without losing double side cooling property.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、電力用三相インバ−タ回路のコンパクト化に好適な半導体スイッチングモジュ−ル及びそれを用いた電力用三相インバ−タ回路用の半導体装置の改良に関する。 The present invention relates to the three-phase inverter power - an improvement of a semiconductor device for motor circuit - a three-phase inverter power using the same Le and - suitable semiconductor switching module in compact capacitor circuit .

【0002】 [0002]

【従来の技術】特開平6ー291223号公報は、半導体チップの両面から放熱を行う半導体装置を提案している。 BACKGROUND ART JP-A 6-1 291 223 discloses proposes a semiconductor device for performing the heat radiation from the both sides of the semiconductor chip. この半導体装置を図7に示す。 It shows the semiconductor device in FIG. (a)はその平面図、(b)はそのGーG線矢視断面図、(c)はそのH (A) is its plan view, (b) the G over G sectional view taken along the line, (c) its H
ーH線矢視断面図である。 It is over H sectional view taken along the line.

【0003】この半導体装置は、一対のヒ−トシンク兼用の伝熱部材J2、J3が、それぞれ半導体チップJ1 [0003] The semiconductor device includes a pair of heat - sink combined heat transfer members J2, J3 are each a semiconductor chip J1
の両面に熱的かつ電気的に接続され、伝熱部材J2、J Thermally and electrically connected to both sides, the heat transfer member J2, J
3はそれぞれ半導体チップへの給電部材としての機能と、ヒ−トシンク及び伝熱部材としての機能とを兼用している。 3 and functions as a power supply member to the semiconductor chip, respectively, heat - also serves a function as sink and the heat transfer member. 以下、この種の半導体装置を両面冷却型半導体装置ともいう。 Hereinafter also referred to a semiconductor device of this type with two-sided cooling semiconductor device.

【0004】この半導体装置では、少なくとも半導体チップJ1の側面は樹脂J5により封止されてカ−ド状のモジュ−ル(カ−ドモジュ−ルともいう)となっており、伝熱部材J2、J3の反チップ側の主面は冷却のために露出するとともに半導体チップの主電極に給電する主電極端子をなし、半導体チップの制御電極に給電する制御端子J4はカ−ドモジュ−ルの側面から封止樹脂を貫通して外部に突出している。 [0004] In this semiconductor device, at least the side surface of the semiconductor chip J1 is sealed with a resin J5 force - de like module - le has a (Ca - - Domoju also referred le), the heat transfer member J2, J3 anti tip side of the main surface forms a main electrode terminals for supplying power to the main electrode of the semiconductor chip with exposed for cooling, the control terminal J4 mosquitoes for feeding to the control electrode of the semiconductor chip - Domoju - sealing from the side of the Le It protrudes outside through the sealing resin.

【0005】J6は絶縁板、J7は半導体チップのボンディングパッドに接合される半田バンプである。 [0005] J6 insulating plate, J7 is a solder bump bonded to the bonding pads of the semiconductor chip.

【0006】 [0006]

【発明が解決しようとする課題】しかしながら、上記した従来の両面冷却型半導体装置では、伝熱部材J2、J [SUMMARY OF THE INVENTION However, in the conventional double-sided cooling semiconductor device described above, the heat transfer member J2, J
3を半導体チップJ1の両主面に接合することにより、 By joining 3 on both main surfaces of the semiconductor chips J1,
これら伝熱部材J2、J3を通じて半導体チップの両面から良好に放熱できるものの、伝熱部材J2、J3は半導体チップの両主面に個別に形成された主電極面に接合されるので、モジュ−ルに単純なトランジスタ又はダイオ−ドを一個乃至並列に複数個内蔵することが困難であり、複雑な電力スイッチング回路をモジュ−ル化することが困難であるという問題点があった。 Although through these heat transfer member J2, J3 can be favorably dissipated from both sides of the semiconductor chip, so the heat transfer member J2, J3 are joined to the main electrode surfaces formed separately on both main surfaces of the semiconductor chip, module - Le simple transistors or diodes to - be plural incorporated in one or in parallel to de difficult, complex power switching circuit module - a problem that it is difficult to Le of.

【0007】特に、この種の半導体スイッチングモジュ−ルの重要な用途として交流モ−タ制御用の三相インバ−タ回路があるが、上記従来技術では、6つのカ−ドモジュ−ルをそれぞれブスバ−などで接続する必要があり、部品点数、組み付け工程の増大と、組み付け部位の緩みが問題となる。 [0007] Particularly, the semiconductor switching module of this type - a three-phase inverter for motor control - - AC motor as an important application of Le there is a capacitor circuit, in the conventional art, 6 Tsunoka - Domoju - Le each bus bar - must be connected or the like, the number of parts, an increase of assembly steps, loosening of the assembly site is problematic.

【0008】本発明は、上記問題点に鑑みなされたものであり、電力用三相インバ−タ回路をコンパクトに構成できる半導体スイッチングモジュ−ル及びそれを用いた半導体装置を提供することをその目的としている。 [0008] The present invention has been made in view of the above problems, the power three-phase inverter - the semiconductor switching module can be configured capacitor circuit compact - le and its object is to provide a semiconductor device using the same It is set to.

【0009】 [0009]

【課題を解決するための手段】請求項1記載の半導体スイッチングモジュ−ルは、ハイサイド側の半導体スイッチング素子が形成されたハイサイド側の半導体チップと、ロ−サイド側の半導体スイッチング素子が形成されたロ−サイド側の半導体チップとを有し、前記両半導体スイッチング素子を直列接続してなるインバ−タ回路を内蔵する半導体スイッチングモジュ−ルにおいて、それぞれ金属板からなるハイサイド板、ミドルサイド板、ローサイド板を有し、前記両半導体チップの出力側の主電極面は、互いに離れて前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、前記ハイサイド側の半導体チップの高位電源側の主電極面は、前記ハイサイド板の内側主面に直接あるいは導電部材を介して接合され、前記ロ− Means for Solving the Problems A semiconductor switching module according to claim 1, wherein - le has a high-side semiconductor chip high-side semiconductor switching elements are formed, b - side of the semiconductor switching element is formed been Russia - and a side of the semiconductor chip, the two semiconductor inverter switching element formed by series connection - the semiconductor switching module incorporating capacitor circuit - in Le, a high-side plate of each metal plate, middle side plate has a low-side plate, wherein both main electrode surface of the output side of the semiconductor chip are bonded directly or via a conductive member inside the main surface of the middle side plate spaced apart from each other, the high-side semiconductor chip of the main electrode surface of the high potential power supply side is bonded directly or via a conductive member inside the main surface of the high-side plate, the b - イド側の半導体チップの低位電源側の主電極面は、前記ローサイド板の内側主面に直接あるいは導電部材を介して接合され、前記両半導体チップは、前記ミドルサイド板、ハイサイド板及びローサイド板の外主面を露出させてモ−ルドされる封止樹脂部により一体に被覆されていることを特徴としている。 The main electrode surface of the low potential power supply side of the id of the semiconductor chip, the bonded directly or via a conductive member inside the main surface of the low-side plate, wherein both the semiconductor chip, the middle side plate, the high-side plate and low-side plate It is characterized by being integrally covered with the sealing resin portion that is field - the outer main surface is exposed in the model.

【0010】本構成によれば、半導体チップの両面冷却機能を維持しつつ、単相インバ−タ回路を単一モジュ− According to the present configuration, while maintaining the double-sided cooling semiconductor chip, a single-phase inverter - a single module the data circuit -
ル化することができ、コンパクト化及び組み付け工数の低減を図り、車両振動などに対する締結部の緩みなどに対する懸念を軽減することができる。 It can be Le of, achieving a reduction in the compactness and assembling steps can be reduced concerns about such loosening of the fastening portion with respect to a vehicle or the like vibrations.

【0011】また、ミドルサイド板(単相インバ−タ回路の出力電極配線又はその一部)が両半導体チップの共通基板を兼ねるので、両半導体チップの高密度配置を実現することができ、更に配線部品点数の低減及び接続工数の低減と配線損失の低減とを図ることができる。 Further, middle side plate - so (single-phase inverter output electrode wiring or a part of the capacitor circuit) also serves as a common substrate for both the semiconductor chip, it is possible to realize a high-density arrangement of the two semiconductor chips, further it can be achieved and reduction of the reduced wiring loss reduction and connection steps of the wiring parts.

【0012】請求項2記載の構成によれば請求項1記載の半導体スイッチングモジュ−ルにおいて更に、前記ハイサイド板及びローサイド板の外主面は、略同一平面をなすことを特徴としている。 [0012] wherein the semiconductor switching module in accordance Invite claim 1 wherein the configuration of claim 2, wherein - yet Le, an outer main surface of the high-side plate and low-side plate is characterized in that a substantially coplanar.

【0013】本構成によれば、ハイサイド板及びローサイド板を薄い電気絶縁材を介して同じ冷却部材の同一平面に密着させることができ、簡素な構造で良好な両面冷却を図ることができる。 [0013] According to this configuration, the high-side plate and low-side plate through a thin electrically insulating material can be brought into close contact with the same plane of the same cooling member, it is possible to achieve a good double-sided cooling a simple structure.

【0014】請求項3記載の構成によれば請求項2記載の半導体スイッチングモジュ−ルにおいて更に、前記ローサイド板又はハイサイド板の一方と前記両半導体チップの一方との間、及び、前記ミドルサイド板と前記両半導体チップの他方との間に良熱伝導性かつ良電導性のスペ−サが介設され、前記両スペ−サは、前記両半導体チップの厚さの差を吸収する厚さの差を有することを特徴としている。 [0014] Semiconductor switching module according to claim 2, wherein according to the configuration of claim 3, wherein - yet Le, between one of the one and the two semiconductor chips of the low side plate or high-side plate, and the middle side plate and the good thermal conductivity and good electrical conductivity of the space between the other of the two semiconductor chips - Sa is interposed, said both space - Sa, the thickness to absorb the difference in thickness of the two semiconductor chips It is characterized by having a difference.

【0015】本構成によれば、両半導体チップの厚さの差をスペ−サにより吸収できるので、ハイサイド板、ミドルサイド板、ローサイド板を簡単な平板とし、かつ、 According to the present configuration, the difference in thickness of the two semiconductor chip space - can be absorbed by the support, and the high-side plate, middle side plate, the low-side plate and simple flat plate, and,
ハイサイド板とローサイド板とを同一厚さの部材とすることができる。 A high-side plate and low-side plate can be a member of the same thickness.

【0016】請求項4記載の構成によれば請求項3記載の半導体スイッチングモジュ−ルにおいて更に、前記両半導体チップの制御電極は、前記半導体チップのスペ− The semiconductor switching module according to claim 3, wherein according to the configuration of claim 4, wherein - yet Le, the control electrodes of the two semiconductor chips, the semiconductor chips of the space -
サ側の主面に形成されているので、このスペ−サの分だけ、ハイサイド板又はローサイド板とミドルサイド板との間にギャップを余計に確保することができるので、たとえば半導体チップの制御電極と制御電極端子とを接続する接続部材たとえばボンデディングワイヤの配置スペ−スなどを無理なく確保することができる。 Because it is formed on the main surface of the support side, the space - by the amount of service, it is possible to extra secure a gap between the high-side plate or low plate and middle side plate, for example, a semiconductor chip control connecting members for example Bonde loading wire arrangement space for connecting the electrode and the control electrode terminals - scan the like can be ensured without difficulty.

【0017】請求項5記載の構成によれば請求項1乃至4のいずれか記載の半導体スイッチングモジュ−ルにおいて更に、前記ハイサイド板、ローサイド板及びミドルサイド板の外主面は、前記半導体チップに背向する部位にて電気絶縁膜を介してそれぞれ冷却部材に密着し、前記ハイサイド板、ローサイド板及びミドルサイド板は、 The semiconductor switching module according to any one of claims 1 to 4, according to the configuration of claim 5, wherein - yet Le, the high-side plate, an outer main surface of the low-side plate and the middle side plate, said semiconductor chip respectively in close contact with the cooling member through the electrically insulating film at the site to be facing away, the high-side plate, the low-side plate and the middle side plate, the
前記封止樹脂部から略面方向へ延設されて端子をなす突出端子部を有することを特徴としている。 It is characterized by having a protruding terminal portion forming a so as to extend substantially toward the plane direction terminal from the sealing resin portion.

【0018】本構成によれば、これらハイサイド板、ローサイド板及びミドルサイド板は、半導体チップと冷却部材とを最短距離で熱的に結合するとともに、それぞれ端子を兼ねることができるので、良好な冷却と、簡素で信頼性に優れた端子構造を実現することができる。 According to the present configuration, these high-side plate, the low-side plate and the middle side plate, a semiconductor chip and a cooling member with thermally coupled with the shortest distance, so each can also serve as a terminal, good cooling and, it is possible to realize an excellent terminal structure simple and reliable.

【0019】請求項6記載の構成によれば請求項3又は4記載の半導体スイッチングモジュ−ルにおいて更に、 The semiconductor switching module according to claim 3 or 4, wherein according to the configuration of claim 6, wherein - yet Le,
前記スペ−サは、前記封止樹脂部から略面方向へ延設されて端子をなす突出端子部を有することを特徴としている。 The space - Sa is characterized by having a protruding terminal portions forming the said extending substantially toward plane direction terminals from the sealing resin portion.

【0020】本構成によれば、スペ−サが封止樹脂部から面方向へ飛び出して端子を兼ねるので、簡素で信頼性に優れた端子構造を実現することができる。 According to the present configuration, space - so support also serves as the terminal protrudes from the sealing resin portion in the plane direction, it is possible to realize an excellent terminal structure simple and reliable.

【0021】請求項7記載の構成によれば請求項1乃至6のいずれか記載の半導体スイッチングモジュ−ルにおいて更に、 前記スペ−サよりも幅広に形成された前記ハイサイド板、ローサイド板及びミドルサイド板の内側主面に接合されて面方向外側へ突出する主電極端子を有することを特徴としている。 Further in Le, the space - - [0021] semiconductor switching module according to claim 7 claims 1 to 6 According to the configuration described above high-side plate which is wider than Sa, low plate and the middle It is characterized by having a main electrode terminal that protrudes joined to the inner main surface of the side plate to face outwardly.

【0022】このようにすれば、たとえば銅など、電気抵抗がMOやWなどより格段に小さく安価な端子を用いることができ、また、スペ−サやミドルサイド板として線膨張係数が半導体チップに近い金属材料を用いる場合でも、その形状加工が容易となり、材料費や形状加工費を低減することができる。 [0022] By this way, for example, copper, electrical resistance can be used much smaller cheaper terminals from an MO or W, also space - linear expansion coefficient as the support and middle side plate within the semiconductor chip even when used near a metal material, it is possible that shaping is facilitated, reducing the material cost and shape processing costs.

【0023】請求項8記載の構成によれば請求項4及び7記載の半導体スイッチングモジュ−ルにおいて更に、 The semiconductor switching module according to claim 4 and 7, wherein according to the configuration of claim 8 - In yet Le,
前記両半導体チップの制御電極に電気的に接続されて面方向外部に突出する制御電極端子は、前記主電極端子と反対方向に突設されることを特徴としている。 The control electrode terminal to the control electrode is electrically connected to the protruding in the surface direction outside of both the semiconductor chip is characterized in that the projecting in a direction opposite to the main electrode terminal.

【0024】本構成によれば、制御電極端子と主電極端子とを反対側に突出させているので、両端子間の電気絶縁の確保が容易となり、配線(ブスバ−)引き回しが容易となる。 According to this configuration, since a control electrode terminal and the main electrode terminals are protruded to the opposite side, ensuring electrical insulation between the terminals is facilitated, the wiring (bus bars -) lead is facilitated.

【0025】請求項9記載の構成によれば請求項4及び7記載の半導体スイッチングモジュ−ルにおいて更に、 The semiconductor switching module according to claim 4 and 7, wherein according to the configuration of claim 9, wherein - yet Le,
前記半導体チップは、前記ハイサイド板及びローサイド板の一方と前記ミドルサイド板との間に互いに離れて並列に介設されるスイッチングトランジスタチップ及びフライホイルダイオ−ドチップからなることを特徴としている。 The semiconductor chip, the switching transistor chip and the flywheel diode is interposed in parallel spaced from each other between the high-side plate and low-side plate while said middle side plates - is characterized by comprising the Dochippu.

【0026】本構成によれば、各半導体チップはそれぞれIGBT(絶縁ゲ−トバイポ−ラトランジスタ)や、 According to this configuration, the semiconductor chips each IGBT (insulated gate - La transistor - Tobaipo) and,
MOST(絶縁ゲートトランジスタ)や、BPT(バイポ−ラトランジスタ)とフライホイルダイオ−ドとを並列接続した2チップ構造をもつので、更に、冷却性及び小型の単相大電流インバ−タ回路を実現することができる。 MOST (insulated gate transistors) and, BPT since with 2 chip structure and de are connected in parallel, further, single-phase high current inverter cooling properties and small - - (Baipo - La transistor) and flywheel diodes realizing a capacitor circuit can do.

【0027】なお、IGBTチップ又はBPTチップとフライホイルダイオ−ドチップとは通常厚さが異なるので、このチップ間厚さの差は異なる厚さの一対のスペ− It should be noted, IGBT chips or BPT chip and flywheel diode - usually the thickness is different from Dochippu, difference in inter-chip thickness is different thicknesses pair of space -
サを、ハイサイド板とミドルサイド板との間、及びローサイド板とミドルサイド板との間にそれぞれ介設することが好ましい。 The service, each is preferably provided between the between the high-side plate and the middle side plate, and the low-side plate and the middle side plate.

【0028】請求項10記載の構成は、前記ハイサイド板、ローサイド板及びミドルサイド板の外主面は、前記半導体チップに背向する部位にて電気絶縁膜を介してそれぞれ冷却部材に密着し、前記冷却部材は、前記半導体スイッチングモジュ−ルを挟んで厚さ方向に挟圧されることを特徴とする請求項1乃至9のいずれか記載の半導体スイッチングモジュ−ルを用いる半導体装置である。 The structure of claim 10, wherein the outer main surface of the high-side plate, the low-side plate and the middle side plate, in close contact with each cooling member via an electrically insulating film at the site to be facing away from the semiconductor chip the cooling member, the semiconductor switching module - the semiconductor switching module according to any one of claims 1 to 9, characterized in that the clamped in the thickness direction across the Le - a semiconductor device using the Le.

【0029】本構成によれば、ハイサイド板及びローサイド板とミドルサイド板とは、両側の冷却部材を挟圧することにより密着される。 [0029] According to this configuration, the high-side plate and low-side plate and the middle side plate, into close contact by nipping the both sides of the cooling member. すなわち、両冷却部材は、締め付け部材を兼ねるので、各部品間の厚さ方向の密着性は良好となり、耐振性なども向上する。 That is, both the cooling member is tightened also serves as a member, adhesion of the thickness direction among the component becomes good, also improved such as vibration resistance.

【0030】請求項11記載の構成によれば、ハイサイド側の半導体スイッチング素子が形成されたハイサイド側の半導体チップと、ロ−サイド側の半導体スイッチング素子が形成されたロ−サイド側の半導体チップとを有し、前記両半導体スイッチング素子を直列接続してなる単相インバ−タ回路を三個並列接続してなる三相の半導体スイッチングモジュ−ルにおいて、それぞれ金属板からなるハイサイド板及びローサイド板と、U相、V相、 According to the configuration of claim 11, wherein the high-side semiconductor switching element high-side semiconductor chips is formed, b - b-side of the semiconductor switching elements are formed - the side of the semiconductor and a tip, wherein the two semiconductor switching elements connected in series and comprising a single-phase inverter - the semiconductor switching module of the three-phase the capacitor circuit formed by three parallel-connected - in Le, the high-side plate each made of metal plate and low plate and, U-phase, V-phase,
W相のミドルサイド板とを有し、U相の前記両半導体チップの出力側の主電極面は、互いに離れてU相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、V相の前記両半導体チップの出力側の主電極面は、互いに離れてV相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、W相の前記両半導体チップの出力側の主電極面は、互いに離れてW相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、各相の前記ハイサイド側の半導体チップの高位電源側の主電極面は、前記ハイサイド板の内側主面に直接あるいは導電部材を介して接合され、各相の前記ロ−サイド側の半導体チップの低位電源側の主電極面は、前記ローサイド板の内側主面に直接あるいは導電部材を And a W-phase of the middle side plate, the main electrode surface of the output side of the both semiconductor chips U-phase, directly or via an electrically conductive member to the inner main surface of the middle side plate of the U-phase apart from each other joined is, the main electrode surface of the output side of the both semiconductor chips of the V phase are joined directly or via a conductive member inside the main surface of the middle side plate of V-phase spaced apart from each other, wherein both the semiconductor chip of W-phase the main electrode surface of the output side is bonded directly or via a conductive member in the inner main surface of the middle side plate of the W-phase apart from each other, the high potential power supply side of each phase of the high-side semiconductor chip main electrode surface, the bonded directly or via a conductive member inside the main surface of the high-side plate, the Hollow phase - main electrode surface of the low potential power supply side of the side of the semiconductor chip, inner main the low side plate directly or conductive member on the surface して接合され、前記両半導体チップは、前記各相のミドルサイド板、ハイサイド板及びローサイド板の外主面を露出させてモ−ルドされる封止樹脂部により一体に被覆されていることを特徴としている。 Are to joined, the two semiconductor chips, the phase of the middle side plate, to expose the outer main surface of the high-side plate and low-side plate mode - that is integrally covered with the sealing resin portion that is field It is characterized in.

【0031】本構成によれば、スペ−サ以外に合計5本のブスバ−状のハイサイド板、ローサイド板、ミドルサイド板を用いて三相インバ−タ回路を内蔵し、かつ、各半導体チップがマトリックス状に一定間隔で配置されたモジュ−ルを実現することができ、装置構成の格段の簡素化を図ることができ、かつ両面冷却により小型大出力化を実現することができる。 According to the present configuration, space - Total besides Sa five bus bars - like the high-side plate, low plate, three-phase inverter using a middle side plate - a built-in capacitor circuit, and each semiconductor chip There module arranged at regular intervals in a matrix - can be realized le, it is possible to greatly simplify the device configuration, it is possible to realize a compact high output by double-sided cooling.

【発明の実施の形態】本発明の半導体装置の好適な実施態様を図面を参照して以下説明する。 The preferred embodiment of the semiconductor device of the embodiment of the present invention will be described with reference to the drawings hereinafter.

【0032】 [0032]

【実施例1】図1は半導体スイッチングモジュ−ルの厚さ方向断面図を示し、図2はこの半導体スイッチングモジュ−ルを用いた半導体装置の厚さ方向断面図を示す。 Embodiment 1 FIG. 1 is a semiconductor switching module - showed a thickness direction cross-sectional view of Le, 2 the semiconductor switching module - shows a sectional view in the thickness direction of the semiconductor device using the Le.
(半導体スイッチングモジュ−ルの構成)図1において、1はハイサイド板、2はローサイド板、2aはスペ−サ、3はミドルサイド板、3aはスペ−サ、4aはハイサイド側の半導体チップ、4bはロ−サイド側の半導体チップ、5ははんだ層、6aは制御電極端子、7a、 In - (Configuration of Le semiconductor switching module) 1, 1 is a high-side plate, 2 low-side plate, 2a is space - Sa, 3 middle side plate, 3a is space - Sa, 4a is the high-side semiconductor chip , 4b is b - side of the semiconductor chip, 5 a solder layer, 6a is a control electrode terminal, 7a,
7bはボンディングワイヤ、8は封止樹脂部、10はローサイド板2の外主面、11はハイサイド板1の外主面、12はミドルサイド板3の外主面である。 7b is a bonding wire, 8 sealing resin portion 10 is an outer main surface of the low-side plate 2, 11 outside the main surface of the high-side plate 1, 12 is the outer main surface of the middle side plate 3.

【0033】ハイサイド板1、ローサイド板2、スペ− The high-side plate 1, the low-side plate 2, Spain -
サ2a、ミドルサイド板3、スペ−サ3aは、タングステン、モリブデン等で形成された金属平板からなるが、 Sa 2a, middle side plate 3, space - Sa 3a is tungsten, although made of a metal flat plate formed of molybdenum,
銅又はアルミ合金などで形成された金属平板で構成してもよい。 In the flat metal plate which is formed like copper or aluminum alloy may be constituted.

【0034】半導体チップ4aは、ハイサイド板1の内主面とスペ−サ3aの一対の主面の一方との間に介設されて、これら両者にはんだ層5により接合されている。 The semiconductor chip 4a is a high-side plate 1 of the inner major surface and space - is interposed between one pair of main surfaces of the support 3a, it is joined by the solder layer 5 on both.
スペ−サ3aの一対の主面の他方は、ミドルサイド板3 Space - the other of the pair of main surfaces of the support 3a is middle side plate 3
の内主面にはんだ接合されている。 It is soldered to the inner major surface of.

【0035】半導体チップ4bは、ミドルサイド板3の内主面とスペ−サ2aの一対の主面の一方との間に介設されて、これら両者にはんだ層5により接合されている。 The semiconductor chip 4b is an inner major surface and space the middle side plate 3 - is interposed between one pair of main surfaces of the support 2a, are joined by the solder layer 5 on both. スペ−サ2aの一対の主面の他方は、ローサイド板2の内主面にはんだ接合されている。 Space - the other of the pair of main surfaces of the support 2a is soldered to the inner main surface of the low-side plate 2.

【0036】スペ−サ2a、3aは、互いに厚さが異なる半導体チップ4a、4bの厚さの差を吸収する厚さの差を有し、これによりハイサイド板1の外主面と、ローサイド板2の外主面は同一高さとされている。 The space - Sa 2a, 3a, the semiconductor chip 4a having a thickness different from each other, have a difference in thickness to absorb the difference in thickness of 4b, thereby an outer main surface of the high-side plate 1, the low side outer main surface of the plate 2 are the same height.

【0037】各板1〜3は、図1における紙面奥方向又は手前方向に延設されて外部ブスバ−(図示せず)に締結される突出端子部10、20、30(図3、図4参照)を有している。 [0037] Each plate 1-3 outside extends rearward on or near side in FIG. 1 busbars - protruding terminal portions 10, 20, 30 to be fastened (not shown) (FIG. 3, FIG. 4 It has a reference). 図3は、スペ−サ2a、3aと半導体チップ4a、4bとの接合前を示す分解図であり、図4は、スペ−サ2a、3aと半導体チップ4a、4bとの接合後を示す分解図である。 3, space - Sa 2a, 3a and the semiconductor chip 4a, an exploded view of the front joining and 4b, FIG. 4, space - Sa 2a, 3a and the semiconductor chip 4a, exploded showing a post-bonding of the 4b it is a diagram.

【0038】なお、この実施例では、制御電極端子6a [0038] In this embodiment, the control electrode terminals 6a
は最初、各板1、3と一体に形成されており、ワイヤボンディング後又は樹脂モ−ルド後、各板1、3から切り離される。 The first, are formed integrally with each plate 1,3, after wire bonding or resin motor - after field, it disconnected from each plate 1,3. このような手法は通常のリ−ドフレ−ム樹脂モ−ルド技術において一般駅であるので詳細な説明は省略する。 Such an approach is typical Li - Dofure - resinless mode - a detailed description since it is generally the station those in field techniques. 制御電極端子6aは、1つの半導体チップについて5本図示しているが、この内訳はゲ−ト端子、ドレイン端子、カレントミラーセンス端子、及び半導体チップの温度を検出する温度検出端子2本である。 The control electrode terminals 6a, although illustrated five for one semiconductor chip, the breakdown gate - a preparative terminal, a drain terminal, a temperature detection terminal two for detecting the temperature of the current mirror sense terminal, and the semiconductor chip . センサ類が必要でなければ、最低限ゲ−ト端子とドレイン端子の2本あれば良い。 If necessary sensors, minimum gate - it is sufficient two preparative and drain terminals.

【0039】なお、各板1〜3は、スペ−サ2a、2b [0039] In addition, each plate 1-3, space - support 2a, 2b
よりも幅広に形成されており、スペ−サ2a、2bの周縁より更に面方向外側にはみ出しているので、各板1〜 Are wider than, Spain - Sa 2a, since further protrudes outwardly in the plane direction the periphery of 2b, each plate 1
3の内側の主面に端子の基部をそれぞれ接合し、面方向外側に突出させてもよい。 3 of the inner main surface of the base of the terminal joined respectively, may protrude outwardly in the plane direction.

【0040】ボンディングワイヤ7a、7bは、半導体チップ4a、4bの制御電極をなすボンディングパッドと制御電極端子6aとを接続し、制御電極端子6aは面方向外側へ突出している。 The bonding wires 7a, 7b, the semiconductor chips 4a, the bonding pads and the control electrode terminals 6a forming the control electrode of 4b is connected, the control electrode terminals 6a are projected to the plane outward.

【0041】封止樹脂部8は、たとえばエポキシモ−ルド樹脂であり、半導体チップ4a、4bをモ−ルドしている。 The sealing resin portion 8, for example Epokishimo - a field resins, semiconductor chips 4a, and 4b mode - are field. 封止樹脂部8は、各板1〜3及び半導体チップ4 The sealing resin portion 8, each plate 1-3 and the semiconductor chip 4
a、4bの側面を覆うが、各板1〜3の外主面10〜1 a, while covering a side surface of 4b, the outer major surface 10 to 1 for each plate 1-3
2は露出し、封止樹脂部8の厚さ方向)の端部は外主面10〜12よりも内側に制限されている。 2 is exposed, the end portion in the thickness direction) of the sealing resin portion 8 is limited to the inside than the outer major surface 10 to 12. これにより、 As a result,
外主面10〜12は冷却部材の平坦な表面に容易に密着することができる。 Outer major surface 10 to 12 can be easily brought into close contact with the flat surface of the cooling member.

【0042】はんだ層5は、ロー材や導電性接着剤などに置換することができ、また、スペ−サ2a、3aと各板1〜3との接合もこれら導電接合材料を用いることができる。 The solder layer 5 may be replaced like the brazing material or a conductive adhesive, also space - can be used support 2a, 3a and these conductive bonding material also bonding between the plates 1-3 . スペ−サ2a、3aと各板1、3とを一体化してもよい。 Space - Sa 2a, it may be integrated 3a and the respective plates 1 and 3.

【0043】半導体チップ4a、4bの制御電極と制御電極端子6aとはボンディングワイヤ7a、7bによるワイヤボンディングの他、バンプ接合などを用いることもできることはもちろんである。 The semiconductor chip 4a, 4b of the control electrode and the control electrode terminals 6a and bonding wire 7a is, 7b other wire bonding using, can of course be also be used as a bump bonding. また、図4では、ローサイド板、ハイサイド板を一主辺に、その他、ミドルサイド板、制御電極を対向辺に配置しているが、例えばローサイド板とミドルサイド板とを一辺に並べたり、ローサイド板とミドルサイド板ととの位置を変更したりするなどの変更は当然可能である。 Further, in FIG. 4, the low-side plate, the high-side plate on one main side, other middle side plate, but is arranged a control electrode on the opposite side, or side by side and low-side plate and the middle side plate to one side for example, changes, such as to change the positions of the low-side plate and the middle side plate is of course possible.

【0044】(変形態様)変形態様を図5に示す。 [0044] The (variant) variant shown in FIG.

【0045】上記実施例1では、半導体チップ4a、4 [0045] In Embodiment 1, the semiconductor chip 4a, 4
bはMOSトランジスタとしたが、図5では、半導体チップ4a、4bとしてIGBTを採用する。 b is set to MOS transistors, in FIG. 5, employing the IGBT semiconductor chips 4a, as 4b. IGBTを誘導性負荷のスイッチング制御に用いる場合はフライホイルダイオ−ドを逆並列接続する必要が有るので各板1、3の間、及び、各板2、3の間にそれぞれフライホイルダイオ−ドが形成された半導体チップ4c、4dが並列に介設されている。 Flywheel diode when used in switching control of the inductive load the IGBT - between the plates 1 and 3 since de the need to reverse parallel connection exists, and each flywheel diode between each plate 2,3 - de the semiconductor chip 4c that but formed, 4d are interposed in parallel.

【0046】また、図5では、ミドルサイド板3の突出端子部30は、ハイサイド板1の突出端子部10、ローサイド板20の突出端子部20と同一方向に引き出されている。 [0046] In FIG. 5, the protruding terminal portion 30 of the middle side plate 3, the protruding terminal portion 10 of the high-side plate 1, are led in the same direction as the protruding terminal portion 20 of the low-side plate 20.

【0047】更に、この変形例では、制御電極端子6a [0047] Further, in this modified example, the control electrode terminals 6a
は、各板1〜3の突出端子部10、20、30と反対側に突出している。 Protrudes on the opposite side of the protruding terminal portions 10, 20, 30 of each plate 1-3. これにより、配線引き回しや端子や配線間の電気絶縁が容易となる。 This facilitates electrical insulation between wire routing and terminals and wiring. 制御電極端子6aなどへのスイッチングノイズ侵入を低減することができる。 It is possible to reduce the switching noise intrusion into a control electrode terminal 6a.

【0048】(半導体装置の構成)この半導体スイッチングモジュ−ルを用いた半導体装置を図2に示す。 [0048] (Configuration of Semiconductor Device) The semiconductor switching module - shows a semiconductor device using the Le in FIG.

【0049】21、22は放熱フィンである冷却部材、 [0049] 21 and 22 is a radiating fin cooling member,
23は絶縁材、24はシリコングリス層である。 23 the insulating material, 24 is a silicon grease layer.

【0050】絶縁材23は各板1、2の外主面10、1 The outer major surface of the insulating material 23 each plate 1,2 10,1
1に密着しており、両者の間にシリコングリス層を塗布、介在させてもよい。 Is in close contact to 1, the silicone grease layer therebetween coating may be interposed. 冷却部材21は、シリコングリス層24を介して冷却部材21、22の平坦な接触面に密着している。 Cooling member 21 is in close contact with the flat contact surface of the cooling member 21 through the silicone grease layer 24. 冷却部材21、22の外主面には多数の凹凸部すなわちフィンが形成されている。 Outside main surfaces of the cooling members 21 and 22 a number of uneven portions i.e. fins are formed.

【0051】冷却部材21、22の図2中、左右両端部には貫通孔が形成され、これら貫通孔にスル−ボルト3 [0051] In Figure 2 of the cooling member 21, through holes are formed in the right and left ends, to the through hole - bolt 3
1が嵌入され、ナット32がスル−ボルト31に螺着されて半導体スイッチングモジュ−ルはこれら一対の冷却部材21、22により挟圧されている。 1 is fitted, the nut 32 is - is screwed on the bolt 31 by a semiconductor switching module - le are pinched by the pair of cooling members 21 and 22. すなわち、この実施例によれば、冷却部材21、22は冷却部材としての役割と、冷却部材21、22を半導体スイッチングモジュ−ルに良好に密着させるためのボルト、ナットによる挟圧力を接触面に伝達する力伝達部材としての役割を果たしている。 That is, according to this embodiment, the cooling members 21 and 22 and serves as a cooling member, the cooling member 21 and 22 semiconductor switching module - bolt for causing favorably adhered to Le, the contact surface of the clamping force by the nut plays a role as a force transmitting member for transmitting. 放熱部材21、22を例えば冷媒チュ− The heat radiation members 21 and 22 for example refrigerant Ju -
ブなどに変更することも可能である。 It is also possible to change such as to drive.

【0052】なお、図2では、冷却部材21、22は一相分の半導体スイッチングモジュ−ル(単相インバ−タ回路)のみ挟圧しているように図示されているが、図2 [0052] In FIG. 2, the cooling members 21 and 22 one phase of the semiconductor switching module - Le (single phase inverter - capacitor circuit) Although only illustrated as nipped, 2
の紙面の奥側に他の2つの相の半導体スイッチングモジュ−ルを同時に挟圧することができる。 Two phases of the semiconductor switching module in the plane of the back side of the other - can be pressed at the same time clamping Le.

【0053】 [0053]

【実施例2】他の実施例の半導体スイッチングモジュ− Example 2 A semiconductor switching module according to another embodiment -
ル及びそれを用いた三相インバ−タ回路構成用の半導体装置を図6を参照して説明する。 Le and three-phase inverter using the same - be described with reference to FIG. 6 of the semiconductor device for data circuitry. 図6はこの半導体装置の要部平面図である。 6 is a fragmentary plan view of the semiconductor device.

【0054】この実施例は、図5の単相インバ−タ回路を3相分、封止樹脂部8内に集積した三相インバ−タ回路内蔵の半導体スイッチングモジュ−ル300の断面図を示す。 [0054] This example, single-phase inverter of Figure 5 - shows a cross-sectional view of the Le 300 - 3 phases the capacitor circuit, a three-phase inverter integrated in the sealing resin portion 8 - capacitor circuit built of the semiconductor switching module .

【0055】この実施例でも、半導体スイッチングモジュ−ル300は、図2に示す冷却部材21、22で両側から挟圧されて1モジュ−ル三相インバ−タ回路をなす半導体装置を実現している。 [0055] Also in this embodiment, the semiconductor switching module - Le 300, 1 module is clamped from both sides by the cooling member 21, 22 shown in FIG. 2 - to achieve a semiconductor device forming a capacitor circuit - Le three-phase inverter there.

【0056】なお、3UはU相のミドルサイド板、3V [0056] It should be noted, 3U the U-phase of the middle side plate, 3V
はU相のミドルサイド板、3WはW相のミドルサイド板であり、それぞれ平行に配置され、それらの一端は突出端子部30U、30V、30Wとなっている。 Middle side plate of the U-phase, 3W are middle side plate of the W phase, are disposed parallel to each one end thereof is made the protruding terminal portions 30 U, 30 V, and 30 W.

【0057】4a、4bはIGBTが形成された半導体チップ、4c、4dはフライホイルダイオ−ドが形成された半導体チップであり、前述の単相インバ−タ回路内蔵の半導体スイッチングモジュ−ルと同様に、各フライホイルダイオ−ドは各IGBTに個別に逆並列接続されている。 [0057] 4a, 4b is a semiconductor chip in which IGBT is formed, 4c, 4d is flywheel diode - de a semiconductor chip is formed, the above-mentioned single-phase inverter - similar to Le - capacitor circuit built of the semiconductor switching module , each flywheel diode - de is antiparallel connected individually to each IGBT.

【0058】なお、制御電極端子は図示されていないが、いわゆリ−ドフレ−ム製造プロセスにより形成できることは明らかである。 [0058] Incidentally, the control electrode terminals are not shown, Iwayuri - Dofure - will be obvious that the same may be formed by an manufacturing process.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】実施例1の半導体スイッチングモジュ−ルの一部破断断面図である。 [1] Semiconductor switching module of Example 1 - is a partially cutaway sectional view of a Le.

【図2】図1に示す半導体スイッチングモジュ−ルを用いた半導体装置の一部破断断面図である。 [2] The semiconductor switching module shown in FIG. 1 - is a partially cutaway sectional view of a semiconductor device using the Le.

【図3】図1に示す半導体スイッチングモジュ−ル製造におけるスペ−サと半導体チップとの接合前を示す分解図である。 [3] The semiconductor switching module shown in FIG. 1 - spelling in Le preparation - is an exploded view showing the front junction between the support and the semiconductor chip.

【図4】図1に示す半導体スイッチングモジュ−ル製造におけるスペ−サと半導体チップとの接合後を示す分解図である。 [4] The semiconductor switching module shown in FIG. 1 - spelling in Le preparation - is an exploded view of the post-bonding of the support and the semiconductor chip.

【図5】図1に示す半導体スイッチングモジュ−ルの変形態様を示す分解図である。 [5] The semiconductor switching module shown in FIG. 1 - is an exploded view showing a variant of Le.

【図6】実施例2の半導体装置の要部平面図である。 6 is a fragmentary plan view of a semiconductor device of Example 2.

【図7】従来の両面冷却型半導体カ−ドモジュ−ルを示す図である。 [7] Conventional sided cooling semiconductor Ca - Domoju - shows Le. (a)はその平面図、(b)はそのGーG (A) is its plan view, (b) the G over G
線矢視断面図、(c)はそのHーH線矢視断面図である。 Sectional view taken along line a (c) is a sectional view taken along line the H over H.

【符号の説明】 DESCRIPTION OF SYMBOLS

1:ハイサイド板 2:ローサイド板 2a:スペ−サ 3:ミドルサイド板 3a:スペ−サ 4a:半導体チップ 4b:半導体チップ 8:封止樹脂部 1: the high-side plate 2: low plate 2a: space - Sa 3: middle side plate 3a: space - Sa 4a: a semiconductor chip 4b: the semiconductor chip 8: encapsulation resin section

Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】ハイサイド側の半導体スイッチング素子が形成されたハイサイド側の半導体チップと、ロ−サイド側の半導体スイッチング素子が形成されたロ−サイド側の半導体チップとを有し、前記両半導体スイッチング素子を直列接続してなるインバ−タ回路を内蔵する半導体スイッチングモジュ−ルにおいて、 それぞれ金属板からなるハイサイド板、ミドルサイド板、ローサイド板を有し、 前記両半導体チップの出力側の主電極面は、互いに離れて前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、 前記ハイサイド側の半導体チップの高位電源側の主電極面は、前記ハイサイド板の内側主面に直接あるいは導電部材を介して接合され、 前記ロ−サイド側の半導体チップの低位電源側の主電極面は、前記ローサイ And 1. A high side of the semiconductor high-side switching element is formed a semiconductor chip, Russia - side of the semiconductor switching element is formed b - and a side of the semiconductor chip, the two semiconductor switching module incorporating capacitor circuit - - invar that the semiconductor switching element becomes connected in series in Le, a high-side plate of each metal plate, middle side plate, has a low-side plate, the output side of the both semiconductor chips the main electrode surfaces are bonded directly or via a conductive member inside the main surface of the middle side plate away from each other, the main electrode surface of the high potential power supply side of the high side of the semiconductor chip, the inside of the high-side plate is bonded directly or via a conductive member on the major surface, the b - main electrode surface of the low potential power supply side of the side of the semiconductor chip, the low-side ド板の内側主面に直接あるいは導電部材を介して接合され、 前記両半導体チップは、前記ミドルサイド板、ハイサイド板及びローサイド板の外主面を露出させてモ−ルドされる封止樹脂部により一体に被覆されていることを特徴とする半導体スイッチングモジュ−ル。 Is bonded directly or via a conductive member inside the main surface of the de-plate, wherein both the semiconductor chip, the middle side plate, to expose the outer main surface of the high-side plate and low-side plate mode - sealing is field resins semiconductor switching module, characterized in that it is integrally covered by the part - le.
  2. 【請求項2】請求項1記載の半導体スイッチングモジュ−ルにおいて、 前記ハイサイド板及びローサイド板の外主面は、略同一平面をなすことを特徴とする半導体スイッチングモジュ−ル。 In Le, an outer main surface of the high-side plate and low-side plate, a semiconductor switching module, characterized in that a substantially coplanar - - 2. A semiconductor switching module according to claim 1, wherein Le.
  3. 【請求項3】請求項2記載の半導体スイッチングモジュ−ルにおいて、 前記ローサイド板又はハイサイド板の一方と前記両半導体チップの一方との間、及び、前記ミドルサイド板と前記両半導体チップの他方との間に良熱伝導性かつ良電導性のスペ−サが介設され、 前記両スペ−サは、前記両半導体チップの厚さの差を吸収する厚さの差を有することを特徴とする半導体スイッチングモジュ−ル。 3. A semiconductor switching module according to claim 2, wherein - in Le, between one of the one and the two semiconductor chips of the low side plate or high-side plate, and the other of the two semiconductor chip and the middle side plate Sa is interposed, said both space - - good thermal conductivity and good electrical conductivity of the space between the support has a feature that it has a difference in thickness to absorb the difference in thickness of the two semiconductor chips semiconductor switching module to - le.
  4. 【請求項4】請求項3記載の半導体スイッチングモジュ−ルにおいて、 前記両半導体チップの制御電極は、前記半導体チップのスペ−サ側の主面に形成されていることを特徴とする半導体スイッチングモジュ−ル。 In Le, the control electrodes of both semiconductor chips, the semiconductor chips of the space - - 4. The semiconductor switching module according to claim 3, wherein the semiconductor switching module, characterized in that formed on the support side of the main surface - Le.
  5. 【請求項5】請求項1乃至4のいずれか記載の半導体スイッチングモジュ−ルにおいて、 前記ハイサイド板、ローサイド板及びミドルサイド板の外主面は、前記半導体チップに背向する部位にて電気絶縁膜を介してそれぞれ冷却部材に密着し、 前記ハイサイド板、ローサイド板及びミドルサイド板は、前記封止樹脂部から略面方向へ延設されて端子をなす突出端子部を有することを特徴とする半導体スイッチングモジュ−ル。 5. A semiconductor switching module according to any one of claims 1 to 4 - the Le, the high-side plate, an outer main surface of the low-side plate and the middle side plate, electric at sites facing away to the semiconductor chip respectively through an insulating film in close contact with the cooling member, the high-side plate, the low-side plate and the middle side plate, characterized in that it has a protruding terminal portions forming the said extending substantially toward plane direction terminals from the sealing resin portion semiconductor switching module and - le.
  6. 【請求項6】請求項3又は4記載の半導体スイッチングモジュ−ルにおいて、 前記スペ−サは、前記封止樹脂部から略面方向へ延設されて端子をなす突出端子部を有することを特徴とする半導体スイッチングモジュ−ル。 In Le, the space - - 6. The semiconductor switching module according to claim 3 or 4, wherein Sa is characterized by having a protruding terminal portions forming the said extending substantially toward plane direction terminals from the sealing resin portion semiconductor switching module and - le.
  7. 【請求項7】請求項1乃至6のいずれか記載の半導体スイッチングモジュ−ルにおいて、 前記スペ−サよりも幅広に形成された前記ハイサイド板、ローサイド板及びミドルサイド板の内側主面に接合されて面方向外側へ突出する主電極端子を有することを特徴とする半導体スイッチングモジュ−ル。 7. A semiconductor switching module according to any one of claims 1 to 6 - In Le, the space - the high-side plate which is wider than Sa, joined to the inner main surface of the low-side plate and the middle side plate semiconductor switching module and having a main electrode terminal which projects has been surface outward - le.
  8. 【請求項8】請求項4及び7記載の半導体スイッチングモジュ−ルにおいて、 前記両半導体チップの制御電極に電気的に接続されて面方向外部に突出する制御電極端子は、前記主電極端子と反対方向に突設されることを特徴とする半導体スイッチングモジュ−ル。 8. The method of claim 4 and 7 the semiconductor switching module according - in Le, the control electrode terminals protruding the both semiconductor chips are electrically connected to to the plane direction external to the control electrode of the opposite to the main electrode terminal semiconductor switching module, characterized in that it is projected in the direction - le.
  9. 【請求項9】請求項4及び7記載の半導体スイッチングモジュ−ルにおいて、 前記半導体チップは、前記ハイサイド板及びローサイド板の一方と前記ミドルサイド板との間に互いに離れて並列に介設されるスイッチングトランジスタチップ及びフライホイルダイオ−ドチップからなることを特徴とする半導体スイッチングモジュ−ル。 9. The semiconductor switching module according to claim 4 and 7, wherein - in Le, the semiconductor chip is interposed in parallel spaced from each other between one and the middle side plate of the high-side plate and low-side plate switching transistor chip and the flywheel diode that - the semiconductor switching module, characterized in that it consists Dochippu - le.
  10. 【請求項10】前記ハイサイド板、ローサイド板及びミドルサイド板の外主面は、前記半導体チップに背向する部位にて電気絶縁膜を介してそれぞれ冷却部材に密着し、 前記冷却部材は、前記半導体スイッチングモジュ−ルを挟んで厚さ方向に挟圧されることを特徴とする請求項1 Wherein said high-side plate, an outer main surface of the low-side plate and the middle side plate, wherein each close contact with the cooling member through the electrically insulating film at the site to be facing away from the semiconductor chip, the cooling member, the semiconductor switching module - claim characterized in that it is clamped in the thickness direction across Le 1
    乃至9のいずれか記載の半導体スイッチングモジュ−ルを用いる半導体装置。 To 9 semiconductor switching module according to any one of - a semiconductor device using the Le.
  11. 【請求項11】ハイサイド側の半導体スイッチング素子が形成されたハイサイド側の半導体チップと、ロ−サイド側の半導体スイッチング素子が形成されたロ−サイド側の半導体チップとを有し、前記両半導体スイッチング素子を直列接続してなる単相インバ−タ回路を三個並列接続してなる三相の半導体スイッチングモジュ−ルにおいて、 それぞれ金属板からなるハイサイド板及びローサイド板と、U相、V相、W相のミドルサイド板とを有し、 U相の前記両半導体チップの出力側の主電極面は、互いに離れてU相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、 V相の前記両半導体チップの出力側の主電極面は、互いに離れてV相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され 11. A high side of the semiconductor high-side switching element is formed a semiconductor chip, Russia - side of the semiconductor switching element is formed b - and a side of the semiconductor chip, the two semiconductor switching elements connected in series formed by a single-phase inverter - the semiconductor switching module of the three-phase the capacitor circuit formed by three parallel-connected - in Le, a high-side plate and low-side plate of each metal plate, U-phase, V phase, and a W-phase of the middle side plate, the main electrode surface of the output side of the both semiconductor chips U-phase, through direct or conductive member inner main surface of the middle side plate of the U-phase apart from each other joined Te, the main electrode surface of the output side of the both semiconductor chips of the V phase are joined directly or via a conductive member inside the main surface of the middle side plate of V-phase apart from each other W相の前記両半導体チップの出力側の主電極面は、互いに離れてW相の前記ミドルサイド板の内側主面に直接あるいは導電部材を介して接合され、 各相の前記ハイサイド側の半導体チップの高位電源側の主電極面は、前記ハイサイド板の内側主面に直接あるいは導電部材を介して接合され、 各相の前記ロ−サイド側の半導体チップの低位電源側の主電極面は、前記ローサイド板の内側主面に直接あるいは導電部材を介して接合され、 前記両半導体チップは、前記各相のミドルサイド板、ハイサイド板及びローサイド板の外主面を露出させてモ− The main electrode surface of the output side of the both semiconductor chips W-phase are joined directly or via a conductive member inside the main surface of the middle side plate of the W-phase apart from each other, of each phase of said high side semiconductor the main electrode surface of the high potential power supply side of the chip, the bonded directly or via a conductive member inside the main surface of the high-side plate, each phase of the b - main electrode surface of the low potential power supply side of the side of the semiconductor chip the bonded directly or via a conductive member inside the main surface of the low-side plate, wherein both the semiconductor chip, the phase of the middle side plate, to expose the outer main surface of the high-side plate and low-side plate mode -
    ルドされる封止樹脂部により一体に被覆されていることを特徴とする半導体スイッチングモジュ−ル。 Semiconductor switching module, characterized in that it is integrally covered with the sealing resin portion that is field - le.
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EP20100006258 EP2234154B1 (en) 2000-04-19 2001-04-18 Coolant cooled type semiconductor device
EP20010109620 EP1148547B8 (en) 2000-04-19 2001-04-18 Coolant cooled type semiconductor device
EP20060022504 EP1742265B1 (en) 2000-04-19 2001-04-18 Coolant cooled type semiconductor device
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US09837382 US6542365B2 (en) 2000-04-19 2001-04-19 Coolant cooled type semiconductor device
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US10756340 US7027302B2 (en) 2000-04-19 2004-01-14 Coolant cooled type semiconductor device
US10946210 US7106592B2 (en) 2000-04-19 2004-09-22 Coolant cooled type semiconductor device
US11325331 US7250674B2 (en) 2000-04-19 2006-01-05 Coolant cooled type semiconductor device
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