JPH11238962A - Manufacture of semiconductor device and the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device the occupied area and height of which are reduced, the loss is reduced, and the heat dissipating property, reliability and productivity are improved. SOLUTION: Solder pastes 25 to 27 are stuck to electrodes 24a to 24c on the surface of a lower metal insulating substrate 21. Semiconductor elements 31, 33, 34 in which solder bumps 32, 35, 36 are formed on electrodes 31a, 33a, 34a on the surface are mounted on the solder pastes 25 to 27. Then, an upper metal insulating substrate 40, in which solder pastes 44 to 48 are stuck to electrodes 43a to 43d on the rear surface respectively, is mounted on the solder bumps 32, 35, 36. They are heated, and both solder pastes 25 to 27 and 44 to 48 are melted. Electrodes 31b, 33b, 34b on the rear surface of the semiconductor elements 31, 33, 34 are bonded to the electrodes 24a to 24c on the surface. The electrodes 31a, 33a, 34a on the surface of the semiconductor elements 31, 33, 34 are bonded to the electrodes 43a to 43d on the rear surface of the upper metal insulating substrate 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which semiconductor elements having electrodes on both upper and lower surfaces are mounted on a substrate, and a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor device, as shown in FIG. 14, an insulator 2 such as glass epoxy resin or ceramic is provided on the upper surface of a metal base 1 and a conductive material such as copper is provided on the upper surface thereof. A metal insulating substrate 4 formed with a circuit wiring 3 made of a conductive metal is used.

The electrode 3a at the center of the circuit wiring 3 on the metal insulating substrate 4 in FIG.
A semiconductor element 5 (for example, a power element such as a power MOSFET or IGBT) 5 having the element 5b is mounted on the lower surface of the electrode 5b by using solder 6. This semiconductor element 5
There is one or more electrodes 5a on the upper surface, and the lower electrode 5b exists on the entire lower surface of the semiconductor element 5.
The electrode 3a has electrodes 7 on the upper and lower surfaces, respectively.
A semiconductor element 7 having a and 7b is mounted using solder 8 by an electrode 7b on the lower surface.

A connection is made between the electrode 5a on the upper surface of the semiconductor element 5 and the electrode 7a on the upper surface of another semiconductor element 7 by using a wire 9 made of a conductive metal, generally aluminum. The electrode 5 on the upper surface of the semiconductor element 5
a and the electrodes 7a on the upper surface of the semiconductor element 7 are connected to the other electrodes 3b and 3c of the circuit wiring 3 on the metal insulating substrate 4 using the same wires 10 and 11.

Further, an external input / output terminal 12 is joined to the electrode 3b by using a solder 13. In this state, a case 14 is adhered to the metal insulating substrate 4 so as to cover them, and the case 14 and the metal It has a structure in which an insulating resin, for example, a silicon gel 15 is filled between the insulating substrate 4 and the insulating substrate 4.
Note that a heat radiation fin 16 is provided on the lower surface of the metal insulating substrate 4.

[0006]

In the above-described semiconductor device, the semiconductor elements 5, 7 are provided on the circuit wiring 3 of the metal insulating substrate 4.
In addition to the electrodes 3a on which the electrodes 3a and 3b are mounted, the electrodes 3b and 3c for connecting the wires 10 and 11 are required.

The silicon gel 15 and the case 14
Since the structure covers not only the semiconductor elements 5 and 7 but also the wires 9 to 11 wired above them, the overall height is increased. In addition, when this semiconductor device is used in industrial equipment such as an inverter, a circuit wiring board (not shown) necessary for the semiconductor device is connected to the semiconductor device via the external input / output terminal 12, so that the circuit The wiring board was to be loaded above the case 14, thereby increasing the overall height.

Further, in the above-described semiconductor device, when the semiconductor elements 5 and 7 are transistors, the saturation voltage between the collector and the emitter is not "zero" but is generated as a loss. This loss usually generates heat and causes a rise in temperature during use, which affects the life and reliability of the semiconductor device.

Further, in response to such a temperature rise, the silicon gel 15 has a low thermal conductivity, and most of the heat generated by the semiconductor elements 5 and 7 is transmitted to the metal insulating substrate 4 below.
Thus, the transmitted heat is radiated through the radiation fins 16 provided on the lower surface of the metal insulating substrate 4, but is transmitted only in one direction, and the efficiency is very poor.

Further, when the temperature rises during use as described above, thermal fatigue occurs. In particular, when an excessive load is applied, the thermal fatigue increases, so that the wires 9, 10, 1
It is conceivable that the semiconductor device may break down due to peeling at the first bonding junctions 9a, 10a, 11a.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and accordingly, has as its object the ability to reduce the occupied area and height, reduce loss, and further improve heat dissipation and reliability. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device capable of improving the productivity and the productivity.

[0012]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises: attaching a solder paste to an electrode on an upper surface of a lower metal insulating substrate; A semiconductor element provided with solder bumps on the electrodes is mounted so as to be in contact with the lower electrode, and an upper metal insulating substrate having a solder paste adhered to the lower electrode is mounted on the solder bumps of the semiconductor element. The electrodes on the lower surface of the semiconductor element and the electrodes on the upper surface of the lower metal insulating substrate, and the electrodes on the upper surface of the semiconductor element and the electrodes on the lower surface of the upper metal insulating substrate were joined by heating and melting the two solder pastes. (Claim 1).

According to such a method of manufacturing a semiconductor device, the semiconductor element is applied to the electrode on the upper surface of the lower metal insulating substrate and the electrode on the lower surface of the upper metal insulating substrate by solder (solder) after melting the solder paste. Since they are joined, there is no need for an electrode for connecting a conventional wire to the upper and lower metal insulating substrates other than the electrode for mounting the semiconductor element.

In addition, the overall height does not need to be as high as the conventional wire. In addition, when an inverter or the like is constituted by both upper and lower metal insulating substrates, a semiconductor element can be directly mounted on them, and a conventional connection structure via external input / output terminals, and an upper circuit wiring substrate as a case. If it is unnecessary, a structure such as to be loaded above the vehicle may be unnecessary.

In addition, the bonding area of the solder after the above-mentioned solder paste is melted is larger than the bonding area of a conventional wire, and accordingly, the impedance of the bonding portion can be reduced and the loss as a semiconductor device can be reduced. . Further, the heat generated by the semiconductor element is transmitted to the lower metal insulating substrate and also to the upper metal insulating substrate, and can be radiated by both. And, since the heat can be radiated well, thermal fatigue can be reduced, and peeling of the joint portion can be prevented.

In addition, the electrode on the lower surface of the semiconductor element is joined to the electrode on the upper surface of the lower metal insulating substrate, and the electrode on the upper surface (solder bump) of the semiconductor element is joined to the electrode on the lower surface of the upper metal insulating substrate. Can be performed without the need for separate steps, and thus the productivity can be improved.

In this case, the heating and melting of both solder pastes may be performed by heat conduction from a hot plate in contact with each metal base of the lower metal insulating substrate and the upper metal insulating substrate. Further, it is preferable to use a double-sided substrate having electrodes on both upper and lower surfaces instead of at least one of the lower metal insulating substrate and the upper metal insulating substrate, and mount other electronic components on the electrodes on the outer surface thereof. Item 3).

The semiconductor device of the present invention has a lower metal insulating substrate having electrodes on the upper surface, and electrodes on the upper and lower surfaces, and the electrodes on the lower surface are soldered or conductively bonded to the electrodes on the upper surface of the lower metal insulating substrate. A semiconductor element mounted by bonding with an agent, a conductor disposed on an electrode on the upper surface of the semiconductor element, and electrodes on both upper and lower surfaces, and an electrode on the lower surface is formed via the conductor. An upper metal insulating substrate pressed against an electrode on an upper surface of the semiconductor element, and a silicon gel filled between the upper metal insulating substrate and the lower metal insulating substrate. Item 7).

According to such a semiconductor device, the same operation and effect as those of the semiconductor device manufactured by the above-described semiconductor device manufacturing method can be obtained, and in particular, the electrode on the upper surface of the semiconductor element and the lower surface of the upper metal insulating substrate can be obtained. Since the joint structure with the electrode is merely press-contacted through a conductor, there is no metallographic joint, thermal fatigue can be further reduced, and breakage of the joint portion does not occur further. obtain. in this case,
The electrodes on the lower surface of the semiconductor element may also be joined to the electrodes on the upper surface of the lower metal insulating substrate by pressure contact instead of being joined to the electrodes on the upper surface of the lower metal insulating substrate by soldering or a conductive adhesive ( Claim 8).

In addition, instead of filling silicon gel between the upper metal insulating substrate and the lower metal insulating substrate, an insulating gas may be filled (claim 10) to surround the semiconductor element. An insulating plate having a concave portion and a hole surrounding the conductor may be provided.
1) Further, a first insulating sheet having a recess at a position surrounding the semiconductor element and a second insulating sheet having a hole surrounding the conductor may be provided (claim 12). ,
A mold resin may be filled (claim 13). The silicon gel or the mold resin is preferably provided so as to individually seal the semiconductor elements, and a space is preferably provided between the respective sealing portions.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, in FIG.
1 shows an overall configuration of a semiconductor device, in which a lower metal insulating substrate 21 is formed on a metal base 22, an insulator 23 provided on the upper surface thereof, such as glass epoxy resin or ceramic, and an upper surface of the insulator 23. And a circuit wiring 24 made of a conductive metal such as copper, and the circuit wiring 24 has electrodes 24a, 24b and 24c.

The solder pastes 25, 26, 27, 28, 29, and 30 are applied to the electrodes 24a, 24b, and 24c, respectively, on the lower metal insulating substrate 21.
The attachment of the solder pastes 25 to 30 is performed by, for example, printing, and may be performed by a method such as application, drip, or dipping.

Next, the semiconductor element 31 is mounted on the upper surface of the solder paste 25 on the electrode 24a. The semiconductor element 31 is, for example, a power element such as a power MOSFET or an IGBT.
1a and 31b. Among them, the electrode 31 on the upper surface
a is present, for example, one or more (in this case, plural), and the electrode 31 b on the lower surface is present on the entire lower surface of the semiconductor element 31, for example. The electrode 31a on the upper surface of such a semiconductor element 31
On the solder paste 25, the semiconductor element 31 provided with the solder dump 32 is mounted so as to be in contact with the lower electrode 31b.

Also, a semiconductor element 33 is mounted on the upper surface of the solder paste 26 on the electrode 24a.
b, the solder paste 27 has a semiconductor element 3
4 is mounted. These semiconductor elements 33 and 34 are the same as or similar to the above-described semiconductor element 31, and a solder dump 3 is provided on the electrodes 33a and 34a on the respective upper surfaces thereof.
5 and 36, and the solder pastes 26 and 2 are provided.
7, the semiconductor elements 33 and 34 provided with the solder dumps 35 and 36 are respectively connected to the lower electrodes 33b and 33b.
34b.

In addition, a conductive spacer 37 is mounted on the upper surface of the solder paste 28 on the electrode 24b, and an IC 38 is mounted on the upper surface of the solder paste 29 on the electrode 24b and the solder paste 30 on the electrode 24c. . On the peripheral edge of the lower metal insulating substrate 21, a case 39 that covers the above-described mounting components is placed.

The semiconductor elements 31, 33, 34
Solder bumps 32, 35, 36 and conductive spacer 37
The upper metal insulating substrate 40 is mounted on the substrate. The upper metal insulating substrate 40 is the same as the lower metal insulating substrate 21 and is turned upside down.
And an insulator 42 provided on the lower surface of the insulator 41 such as glass epoxy resin or ceramic, and a circuit wiring 43 formed of a conductive metal such as copper formed on the lower surface of the insulator 41. Are the electrodes 43a, 43b, 43c,
43d and 43e.

The electrodes 43a to 43e of the upper metal insulating substrate 21 are respectively provided with solder paste 4
4, 45, 46, 47, 48, 49, 50 and 51 are adhered. The solder pastes 44 to 51 are attached by the same method as the solder pastes 25 to 30 described above. Further, a chip component 52 is mounted on the lower surface of the solder paste 50 under the electrode 43d and the solder paste 51 under the electrode 43e, and the solder paste 50, 51 is heated and melted. The component 52 is mounted by being joined to the electrodes 43d and 43e.

The attachment of the solder pastes 44 to 51 and the mounting of the chip component 52 are performed by the upper metal insulating substrate 40.
Are performed with the respective electrodes 43a to 43e facing upward.
Also, solder paste 25-30 and solder paste 4
For 4 to 51, those having a lower melting point than the solder bumps 32 to 36 are used.

The upper metal insulating substrate 40 on which the solder pastes 44 to 51 are attached and the chip components 52 are mounted is
The semiconductor chips 31, 33, 34 are mounted upside down on the solder bumps 32, 35, 36 and the conductive spacers 37 via solder pastes 44 to 49.

Then, using a heating furnace such as a reflow furnace,
At a temperature ranging from the melting point of the solder pastes 25 to 30, 44 to 51 to the melting point of the solder bumps 32 to 36,
By heating the whole, solder paste 25-3
0,44 to 49, and thus the semiconductor element 3
Electrodes 31b, 33b, 34 on the lower surfaces of 1, 33, 34
b, the lower end of the conductive spacer 37 and the IC 38 are joined to the electrodes 24a to 24c on the upper surface of the lower metal insulating substrate 21, and at the same time, the electrodes 31a, 33a, and 34a on the upper surfaces of the semiconductor elements 31, 33, and 34 (solder bumps). 32, 35, 3
6) The upper end of the conductive spacer 37 is joined to the electrodes 43a to 43d on the lower surface of the upper metal insulating substrate 40. Thereafter, the inside of the lower metal insulating substrate 21, the case 39, and the upper metal insulating substrate 40 are filled with an insulating synthetic resin, for example, a silicon gel 53, and cured.

In the semiconductor device manufactured as described above, the semiconductor elements 31, 33 and 34 are connected to the electrodes 24a and 24b on the upper surface of the lower metal insulating substrate 21 and the electrodes 43a to 43d on the lower surface of the upper metal insulating substrate 40. The electrodes 24a, on which the semiconductor elements 31, 33, 34 are mounted on the lower and upper metal insulating substrates 21, 40, respectively, are joined by the solder (solder) after melting the solder pastes 25-27, 44-48. Except for 24b and 43a to 43d, there is no need for an electrode for connecting conventional wires 9 to 11. Therefore, the areas of the lower metal insulating substrate 21 and the upper metal insulating substrate 40 can be reduced accordingly, and the overall occupied area can be reduced.

In addition, the entire height does not need to be high enough to cover the conventional wires 9 to 11. Further, when the lower and upper metal insulating substrates 21 and 40 constitute an inverter and the like, the semiconductor elements 31, 33 and 34
Can be directly mounted, and a conventional connection structure via the external input / output terminal 12 and a structure in which the upper circuit wiring board is stacked above the case 14 can be omitted. Can be reduced as desired.

Table 1 below shows a comparison between the size of a conventional inverter circuit combining a transistor module and a control board formed by wire bonding and the size of an inverter circuit according to the present invention.

[0034]

[Table 1]

As is apparent from Table 1, the inverter circuit according to the present invention has a base area of about １ ／ compared to the conventional inverter circuit in which a transistor formed by wire bonding and a control substrate are combined. About 1 height
/ 2, and the volume is about 1/4, which indicates that the size can be sufficiently reduced.

On the other hand, solder pastes 25 to 27, 44
The bonding area by the solder after melting of ~ 48 is larger than the bonding area by the conventional wires 9 to 11,
To that extent, the impedance at the junction can be reduced, and the loss as a semiconductor device can be reduced.

FIG. 2 shows a comparison of the saturation voltage and the forward voltage between the collector and the emitter of a semiconductor device of the same lot and a semiconductor device of the present invention, which is a semiconductor device of the same lot. Things. The greater the value of the saturation voltage and the forward voltage between the collector and the emitter, the greater the loss. As is apparent from FIG. 2, both the saturation voltage and the forward voltage between the collector and the emitter are smaller in the semiconductor device according to the configuration of the present invention, and the loss is reduced. Further, the heat generated by the semiconductor elements 31, 33 and 34 is transmitted to the lower metal insulating substrate 21 and the upper metal insulating substrate 40
Heat can be dissipated by both.

Table 2 below shows that the rated current of the semiconductor device of the same lot is 1 for the semiconductor device according to the conventional wire bonding and the semiconductor device according to the present invention.
When a load current of 20% is applied for 2 seconds and stopped for 18 seconds, the semiconductor elements 32, 3
The figure shows the results of measuring the temperature rise when a load current is applied to the lower metal insulating substrate 21 on which the substrates 3 and 34 are mounted.

[0039]

[Table 2]

As is clear from Table 2, the temperature rise of about 8 [° C.] was caused in the conventional semiconductor device using the wire bonding, whereas the semiconductor device according to the present invention was increased in temperature as described above. Since heat is also transmitted to the metal insulating substrate 40, there is only a temperature rise of about 4 [° C.], and it can be seen that heat dissipation is excellent.

The good heat dissipation makes it possible to reduce the thermal fatigue and prevent the joint from peeling off.

Table 3 below shows that a load current of 120 [%] of the rated current is applied for 2 seconds and stopped for 18 seconds between the conventional semiconductor device by wire bonding and the semiconductor device according to the present invention as described above. It shows the number of cycles until a failure occurs when the operation is repeatedly performed.

[0043]

[Table 3]

As is apparent from Table 3, the semiconductor device according to the present invention has a failure of about 4,000 times, while the semiconductor device according to the configuration of the present invention has a failure of about 8,000 times, whereas the conventional semiconductor device by the wire bonding bonding has a failure of about 8,000 times. Was confirmed to be high.

In addition, according to the above-described manufacturing method, the electrodes 31b, 33b,
34b and the electrodes 24a-2 on the upper surface of the lower metal insulating substrate 21.
4c and the semiconductor elements 31, 33, 3
4, the electrodes 31a, 33a, 34a (solder bumps 32, 35, 36) on the upper surface and the electrodes 43a to 43d on the lower surface of the upper metal insulating substrate 40 can be joined. Instead, productivity can be improved.

3 to 13 show the second to twelfth embodiments of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description will be made. Omitted, and only different parts will be described.

[Second Embodiment] In the second embodiment shown in FIG. 3, a lower heating plate 62 having a heater 61 provided therein and a lower heating plate 64 having a heater 63 provided therein are provided in place of the above-mentioned heating furnace. When the solder pastes 25 to 30, 44 to 49 are heated and melted, the lower hot plate 62 is brought into contact with the metal base 22 of the lower metal insulating substrate 21 and the upper hot plate 64 is It is brought into contact with the metal base 41.

Then, in this state, the heaters 61 and 63 are energized. Then, the heat generated from the heaters 61 and 63 is transmitted from the lower heating plate 62 to the solder pastes 25 to 30 through the lower metal insulating substrate 21 and from the upper heating plate 64 to the solder pastes 44 to 30 through the upper metal insulating substrate 40. Conduction to 49.

By these heat conductions, the solder pastes 25 to 30, 44 to 49 are melted, and thus the electrodes 31 on the lower surfaces of the semiconductor elements 31, 33, 34 are formed.
b, 33b, 34b, the lower end of the conductive spacer 37, and I
C38 and the electrodes 24 a to 2 on the upper surface of the lower metal insulating substrate 21.
4c and the semiconductor elements 31, 33, 3
4, the upper electrodes 31a, 33a, 34a (solder bumps 32, 35, 36) and the upper end of the conductive spacer 37 are joined to the electrodes 43a to 43d on the lower surface of the upper metal insulating substrate 40. In this case, solder paste 25-30,
For 44 to 49, those having a higher melting point than the solder bumps 32 to 36 or the same ones are used.

According to this method, since the heating is performed by heat conduction, the solder pastes 25 to 30, 44 to 49 are
A solder having a higher melting point than the solder bumps 32 to 36 or the same can be used. For example, a solder having a high conductivity such as a Sn-Ag solder can be used. 31, 33, 34
The impedance at the junction with the upper metal insulating substrate 40 can be further reduced, and the loss as a semiconductor device can be further reduced.

[Third Embodiment] In a third embodiment shown in FIG. 4, an upper metal insulating substrate 71 is used in place of the upper metal insulating substrate 40. The upper two-sided metal insulating substrate 71
Is formed by providing insulators 73, 74 on both upper and lower surfaces of a metal base 72, and further providing circuit wirings 75, 76 on the upper and lower surfaces thereof. The circuit wiring 75 has electrodes 75a to 75f, Has electrodes 76a to 76f.

The solder pastes 77 to 86 and 87 to 96 are applied to the electrodes 75a to 75f and 76a to 76f of the upper double-sided metal insulating substrate 71, respectively. Also, the solder pastes 93 and 94 on the lower surface of them
The chip component 97 is mounted on the lower surface, and the chip component 98 is also mounted on the lower surface of the solder pastes 95 and 96, and the solder pastes 93 to 96 are further mounted thereon.
Are heated and melted to join the chip components 97 and 98 to the electrodes 76d to 76f.

Further, the chip component 99 is mounted on the upper surface of the solder paste 77, 78 which is the outer surface in this case, and the chip component 1 is mounted on the solder paste 79, 80.
00 and the solder pastes 81 and 82 have the IC 101
And the chip parts 102 are added to the solder pastes 83 and 84.
And the solder paste 85 and 86 have chip components 103.
Are also mounted on the upper surface, respectively. In this case, the semiconductor elements 3 are added to the solder pastes 77 to 96.
Those having a lower melting point than the solder bumps 32 to 36 on 1, 33 and 34 are used.

The solder pastes 77 to 96 are adhered, the chip components 97 and 98 are mounted, and the upper and lower metal insulating substrate 71 on which the chip components 99, 100, 102 and 103 and the IC 101 are mounted is placed on the lower metal substrate 21. Solder bumps 32, 3 of the semiconductor elements 31, 33, 34
5 and 36 and the conductive spacer 37 are mounted via solder pastes 87 to 92.

Thereafter, using a heating furnace such as a reflow furnace,
At a temperature ranging from the melting point of the solder paste 25 to 30, 77 to 96 to the melting point of the solder bumps 32 to 36,
By heating the whole, solder paste 25-3
0,77-92 and thus the semiconductor element 3
Electrodes 31b, 33b, 34 on the lower surfaces of 1, 33, 34
b, the lower end of the conductive spacer 37 and the IC 38 are joined to the electrodes 24a to 24c on the upper surface of the lower metal insulating substrate 21, and at the same time, the electrodes 31a, 33a, and 34a on the upper surfaces of the semiconductor elements 31, 33, and 34 (solder bumps). 32, 35, 3
6) and joining the upper ends of the conductive spacers 37 and the electrodes 76a to 76d on the lower surface of the upper double-sided metal insulating substrate 71, and at the same time, joining the chip components 99, 100, 102, 103 and the IC 101 to the electrodes 75a to 75f. I do.

According to this method, to mount more electronic components than in the first embodiment, it is possible to realize the electronic components with a small size having the same occupation area as in the first embodiment. In this case, the upper double-sided metal insulating substrate 71 may be changed to a substrate based on a synthetic resin such as a glass epoxy resin substrate. Even in this case, although the heat radiation property is inferior, the same effect as in the first embodiment can be obtained with respect to miniaturization and reduction of loss.

The upper double-sided metal insulating substrate 71 may be used instead of the lower metal insulating substrate 21 instead of the upper metal insulating substrate 40. In this case, the upper metal insulating substrate 40
Of the chip components 99, 10
Other electronic components such as 0, 102, 103 and IC 101 are mounted on the electrodes on the lower surface of the upper metal insulating substrate 40. Further, the upper double-sided metal insulating substrate 71 may be used in place of both the upper metal insulating substrate 40 and the lower metal insulating substrate 21. In addition, in this case, solder paste 25-3
The heating and melting of 0.77 to 92 are performed by using both hot plates 6 of the second embodiment.
Alternatively, the heat transfer may be performed by heat conduction from the second and the second heat exchangers.

[Fourth Embodiment] In a fourth embodiment shown in FIG. 5, positioning holes 111 and 112 are formed at each corner of the lower and upper metal insulating substrates 21 and 40, and the positioning holes 111 and 112 are formed. By fitting the holes 111 of the lower metal insulating substrate 21, the spacers 115, and the holes 112 of the upper metal insulating substrate 40 into the pins 114 provided at the same corners of the jig 113 in this order, the lower and upper metal insulating substrates Positioning of 21 and 40 is performed, and in this state, heating for melting the solder pastes 25 to 30 and 44 to 49 is performed.

As a result, the semiconductor elements 31, 33, 3
4, the upper ends of the electrodes 31a, 33a, 34a (solder bumps 32, 35, 36) and the conductive spacers 37 and the electrodes 43a to 43d on the lower surface of the upper metal insulating substrate 40 can be joined with high positional accuracy. The accuracy of assembly can be improved.

In this case, the spacer 115 is located between the lower and upper metal insulating substrates 21 and 40. By changing the height of the spacer 115, the lower and upper metal insulating substrates 21 and 40 are arranged. , 40 can be adjusted. This makes it possible to adjust the overall height of the semiconductor device according to the dimensions of the equipment used, and to select solder bumps and solder pastes with dimensions required for the characteristics of the semiconductor device, and to improve reliability. Properties can be further improved.

In this case, too, the solder paste 25
The heating and melting of 30, 44４９49 may be performed in any of a heating furnace such as a reflow furnace and heat conduction from both heating plates 62 and 64 of the second embodiment. In addition, at least one of the lower and upper metal insulating substrates 21 and 40 may be replaced with a double-sided substrate.

[Fifth Embodiment] In a fifth embodiment shown in FIG. 6, the formation of the solder bumps 32, 35 and 36 of the semiconductor elements 31, 33 and 34 is performed by using carbon or the like whose dimensional change by heating is relatively small. A semiconductor element 31 and a semiconductor device 31 are provided in each recess 122 of a lower mold jig 121 made of a material such as ceramic.
33, 34 (represented by the semiconductor element 31) are arranged, and the electrodes 31 on the upper surfaces of the semiconductor elements 31, 33, 34 are arranged.
A soldering flux is applied to a, 33a, and 34a (also represented by the electrode 31a).

Thereafter, the positioning pin 1 of the lower jig 121 is
23, the positioning hole 125 of the upper jig 124 is fitted,
The electrodes 31a on the upper surfaces of the semiconductor elements 31, 33, 34,
33a and 34a are covered by the upper jig 124. Then, the solder 127 is disposed in each of the through holes 126 of the upper mold jig 124 using, for example, a ball mounter that supplies the solder 127 in the form of a ball. Is melted so that the solder 127 is joined to the electrodes 31a, 33a, 34a on the upper surfaces of the semiconductor elements 31, 33, 34, and solder bumps 32, 35, 36 (also represented by the solder bumps 32) are formed. Form.

According to this method, the semiconductor elements 31, 33, 34 are spread by wetting due to the melting of the solder 127.
Solder bumps 32, 35 and 36 having the same area as the electrodes 31a, 33a and 34a of the semiconductor elements 31, 33 and 34.
The impedance at the joints between the a, 33a, 34a and the solder bumps 32, 35, 36 can be further reduced, and the loss as a semiconductor device can be reduced.

In this case, the through hole 1 of the upper jig 124
The size of the solder bumps 32, 35, and 36 can be changed by changing the size of the solder 127 and the size of the solder 127 to be disposed thereon. Can be formed, and the reliability can be further improved. Moreover, in this case, it is possible to form many solder bumps at one time, and the productivity can be improved.

[Sixth Embodiment] In the sixth embodiment shown in FIG. 7, the formation of the solder bumps 32, 35 and 36 of the semiconductor elements 31, 33 and 34 is the same as that of the lower jig of the fifth embodiment. A heat sink 133 is arranged in each recess 132 of the lower jig 131 made of the same material 121, and a heat sink 134 is arranged thereon. Further, the semiconductor elements 31, 33, 34 (semiconductor element 3)
1), and the semiconductor elements 31, 3
A flux for soldering is applied to the electrodes 31a, 33a, 34a (also represented by the electrodes 31a) on the upper surfaces of the electrodes 3, 34.

Thereafter, the positioning pin 1 of the lower jig 131
35, the positioning hole 137 of the upper jig 136 is fitted.
The electrodes 31a on the upper surfaces of the semiconductor elements 31, 33, 34,
33a and 34a are covered with the upper jig 136. Then, the solder 139 is disposed in each of the through holes 138 of the upper jig 136 by using, for example, the above-described ball mounter, and then the whole is heated by a heating furnace or the like to melt the solders 134 and 139. Thereby, the electrodes 31b, 33b, 34 on the lower surfaces of the semiconductor elements 31, 33, 34
The heat radiating plate 133 is bonded to each of the solder bumps b, and solder bumps 32, 35, and 36 (also represented by the solder bumps 32) are formed.

According to this method, in addition to obtaining the same effects as in the fifth embodiment, the bonding of the heat sink 133 to the semiconductor elements 31, 33, 34 can be achieved by the solder bumps 32, 35, 3
6 can be formed at the same time as the formation, thereby improving the productivity. And the heat dissipation of the semiconductor elements 31, 33, and 34 can be more actively performed by the joined heat dissipation plate 133.

[Seventh Embodiment] In a seventh embodiment shown in FIG. 8, semiconductor elements 31, 33 and 34 are placed on electrodes 24a and 24b of lower metal insulating substrate 21 by solders 141 and 1 respectively.
42, 143, the electrodes 31b, 33b, 34 on the lower surface.
b is bonded and mounted. In this case, the solder 141
A conductive adhesive may be used in place of -143. or,
A conductive rubber connector 144 is mounted on the electrodes 24b and 24c.
45 are provided.

The conductors 146, 147, and 148 made of copper, silver, or the like are arranged on the electrodes 31a, 33a, and 34a on the upper surfaces of the semiconductor elements 31, 33, and 34, respectively. The upper two-sided metal insulating substrate 71 used in the third embodiment is arranged in contact with the lower electrodes 76a to 76d. In addition, the upper double-sided metal insulating substrate 71 has the lower electrodes 76 d and 76 e in contact with the upper surface of the conductive rubber connector 144.

In this state, the upper and lower metal insulating substrates 71 and 72
1 is fastened with a fixing member 149 such as a screw inserted between them with the case 39 interposed therebetween. With this fastening force, the electrodes 76 a to 76 d on the lower surface of the upper double-sided metal insulating substrate 71 are connected to the conductors 146 to 148. Via the semiconductor elements 31, 33, 34
Are in pressure contact with the electrodes 31a, 33a, 34a on the upper surface. Also, the electrodes 76d on the lower surface of the upper double-sided metal insulating substrate 71,
76e is pressed against the upper surface of the conductive rubber connector 144. These press-contacts are performed by the upper and lower metal insulating substrates 7.
Instead of connecting the components 1 and 21 with the fixing member 149, the components may be connected by using claws.

With this structure, the same operation and effect as those of the semiconductor device manufactured by the method of manufacturing the semiconductor device of the first embodiment can be obtained.
The joint structure between the electrodes 31a, 33a, 34a on the upper surfaces of the 1, 33, 34 and the electrodes 76a to 76d on the lower surface of the upper double-sided metal insulating substrate 71 is merely brought into pressure contact with the conductors 146 to 148. Therefore, there is no need to perform a step of bonding and mounting with solder or a conductive adhesive, and the productivity can be further improved.

Further, in the joining structure in which only the pressure contact is made,
Since there is no metallographic bonding and thermal fatigue can be further reduced, breakage or the like of the bonding portion can be prevented from occurring further, and reliability can be further improved. In addition, in this case, the chip components 99 and 100 and the IC 101 are mounted on the electrodes 75a to 75e on the upper surface of the upper double-sided metal insulating substrate 71, so that more electronic components than those of the first embodiment can be mounted. For mounting, it is also possible to obtain an effect that it can be realized with a small size having the same occupation area as the first embodiment.

[Eighth Embodiment] In the eighth embodiment shown in FIG. 9, the electrodes 76a to 76a on the lower surface of the upper double-sided metal insulating substrate 71 are formed.
76d is connected to the electrodes 31a, 33a, 34a on the upper surfaces of the semiconductor elements 31, 33, 34 via the conductors 146 to 148.
And the electrodes 31b, 33b, 34b on the lower surfaces of the semiconductor elements 31, 33, 34 are also
1 on the electrodes 24a, 24b on the upper surface
Instead of bonding by 3 or a conductive adhesive, bonding is performed by pressing.

In the above-described structure, the semiconductor elements 31, 33, and 34 are attached to the lower metal insulating substrate 21 by the solder 141.
143 or a step of mounting by bonding with a conductive adhesive is not required, and the pressure contact can be performed together with the electrodes 31a, 33a, 34a on the upper surfaces of the semiconductor elements 31, 33, 34, thereby improving the productivity. be able to.

Ninth Embodiment In the ninth embodiment shown in FIG. 10, the electrodes 75a to 75e, 7
In place of the upper metal insulating substrate 71 having the metal substrates 6a to 76e, an insulator 152 is provided only on the lower surface of the metal base 151, and a circuit wiring 153 is provided only on the lower surface. Electrode 153 of wiring 153
a to 153d are connected to the electrodes 31a, 33a, on the upper surface of the semiconductor elements 31, 33, 34 via the conductors 146 to 148.
34a and the electrodes 153d, 153e.
Is pressed against the upper surface of the conductive rubber connector 144.

The electrode 153 on the upper metal insulating substrate 154
e, a lead 156a of the external input terminal 156 is mounted using solder 155, and the external input terminal 15
6 is sandwiched between the lower metal insulating substrate 21 and the insulator 23. With this configuration, the same operation and effect as those of the semiconductor device of the seventh embodiment can be obtained except that an electronic component can be mounted in a smaller size than in the first embodiment. be able to.

Note that, also in this case, the semiconductor elements 31 and 3
The electrodes 31b, 33b, and 34b on the lower surfaces of the lower and upper metal substrates 3 and 34 are bonded to the electrodes 24a and 24b on the upper surface of the lower metal insulating substrate 21 by solders 141 to 143 or a conductive adhesive. As in the embodiment, the bonding may be performed by pressing.

In the seventh to ninth embodiments, the inside of the lower metal insulating substrate 21, the case 39, and the upper metal insulating substrate 71 (154) are filled with silicon gel 53, respectively. However, an insulating gas may be sealed instead. According to the insulating gas, the step of hardening the silicon gel 53 becomes unnecessary.
Productivity can be improved. In addition, silicone gel 5
The generation of voids considered when filling with No. 3 is not caused by the insulating gas, and the reliability can be improved.

Further, in this case, instead of the silicon gel 53, a mold resin such as an epoxy resin is filled into the lower metal insulating substrate 21, the case 39, and the inner portion of the upper metal insulating substrate 71 (154) and cured. May be. According to the resin filled and cured with a mold resin such as an epoxy resin, the distance between the lower metal insulating substrate 21 and the upper metal insulating substrate 71 (154) is reduced by the contraction force when the molding resin is cured. The pressure contact between them and the semiconductor elements 31, 33, 34 can be strengthened to improve the reliability.

[Tenth Embodiment] In the tenth embodiment shown in FIG. 11, a silicon gel 53 is filled between the lower metal insulating substrate 21 and the upper metal insulating substrate 71 (154). In addition, the semiconductor device has concave portions 161 to 163 surrounding the semiconductor elements 31, 33, and
Plate 16 made of an insulating material such as silicon rubber having holes 164 to 166 surrounding
7 are arranged.

In the above-described structure, the insulating plate 167 allows the lower metal insulating substrate 21 and the upper metal insulating substrate 7
1 (154) and the electrodes 31a, 33 on the upper surfaces of the semiconductor elements 31, 33, 34.
Positioning of the conductors 146 to 148 with respect to the a and 34a can be performed by the insulating plate 167, and the assembling accuracy can be improved.

[Eleventh Embodiment] In the eleventh embodiment shown in FIG. 12, the silicon gel 53 is replaced between the lower metal insulating substrate 21 and the upper metal insulating substrate 71 (154). A first insulating sheet 174 made of an insulating material such as silicon rubber having recesses 171 to 173 surrounding the semiconductor elements 31, 33 and 34, and holes 175 to 177 surrounding the conductors 146 to 148 And a second insulating sheet 178 also made of an insulating material such as silicon rubber.

Even with such a configuration, the tenth
The same effect as that of the embodiment can be obtained. In this case, the recess 171 surrounding the semiconductor elements 31, 33, 34
173 and holes 175 surrounding conductors 146-148
177 can be formed separately on the first insulating sheet 174 and the second insulating sheet 178, so that processing is easy and productivity can be improved.

[Twelfth Embodiment] In a twelfth embodiment shown in FIG. 13, a silicon gel 53 is filled between the lower metal insulating substrate 21 and the upper metal insulating substrate 71 (154). Thus, the semiconductor elements 31, 33, and 34 are individually sealed with the silicon gels 181 to 183, and spaces 184 and 185 are provided between the sealed portions.

In the above-described structure, the portions sealed by the silicon gels 181 to 183 are not covered by the semiconductor elements 31 and 3.
3 and 34, the silicon gels 181 to 183 are hardened and the semiconductor element 3
Silicon gel 181-
As the 183 expands, the upper and lower substrates 71 associated therewith
The lateral displacement of the (154), 21 can be kept small, and the semiconductor elements 31, 3 with respect to both substrates 71 (154), 21 can be reduced.
It is possible to suppress the relative displacement between 3, 34 and improve the assembling accuracy.

It should be noted that there is a sufficient space between the substrates 71 (154) and 21 to ensure the withstand voltage. For this reason,
It is not necessary to particularly provide an insulating material between the portions sealed by the silicon gels 181 to 183, but the substrate 71 (1
In the case where more excellent insulation is required, for example, when the gap between 54) and 21 is extremely narrow, it is preferable to fill an insulating gas between the sealing portions.

The sealing of each of the semiconductor elements 31, 33, 34 may be performed by using a molding resin such as an epoxy resin instead of the silicon gels 181 to 183. In particular, in such a case, the semiconductor element 3 of both substrates 71 (154) and 21 is formed by the contraction force when the mold resin is cured.
It is possible to increase the pressure contact with 1, 33, 34 to improve reliability.

Further, in this case, the conductive rubber connector 144
Alternatively, a conductor similar to the conductors 146 to 148 may be used, and this conductor may also be individually sealed with silicone rubber or mold resin. In addition, the present invention is not limited to the embodiment described above and shown in the drawings, and can be implemented with appropriate modifications without departing from the scope of the invention.

[0090]

The present invention is as described above.
The following effects are obtained. According to the method of manufacturing a semiconductor device of the first aspect, the occupation area and the height can be reduced, the loss can be reduced, and the heat dissipation, the reliability, and the productivity can be improved. Can be achieved.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to use a solder having a high conductivity for the solder paste, to further reduce the impedance at the junction of the semiconductor element, and to further reduce the loss. Can be. According to the method of manufacturing a semiconductor device according to the third aspect, it is possible to mount a large number of electronic components in a small size with a small occupation area.

According to the method of manufacturing a semiconductor device of the fourth aspect, the electrodes on the upper surface of the semiconductor element and the electrodes on the lower surface of the upper metal insulating substrate can be joined with good positional accuracy, and the assembly accuracy can be improved. Height can be adjusted according to the dimensions of the equipment used, and solder bumps and solder pastes with dimensions required for the characteristics of the semiconductor device can be selected, further improving reliability. Improvement can be achieved.

According to the method of manufacturing a semiconductor device of the fifth aspect, it is possible to form a solder bump having a small impedance at the junction, thereby reducing the loss of the semiconductor device, and also reduce the impedance required for the characteristics of the semiconductor device. Solder bumps having the same dimensions can be formed, and the reliability can be further improved. According to the method of manufacturing a semiconductor device of the sixth aspect, the same effect as that of the method of manufacturing the semiconductor device of the fifth aspect can be obtained, and in addition, the bonding of the heat sink to the semiconductor element can be performed simultaneously with the formation of the solder bumps. Performance can be improved.
The heat dissipation of the semiconductor element can be improved.

According to the semiconductor device of the seventh aspect, the first aspect
In addition to the same effects as those of the semiconductor device manufactured by the method of manufacturing a semiconductor device, the productivity can be further improved, and the thermal fatigue of the joint between the semiconductor element and the upper-side metal insulating substrate can be reduced. The size can be further reduced, and the reliability can be further improved. In addition, when many electronic components are mounted, it can be realized with a small size and a small occupation area. According to the semiconductor device of claim 8,
The bonding of the semiconductor element to the lower metal insulating substrate can be performed by the same pressing of the upper electrode of the semiconductor element to the upper metal insulating substrate, so that the productivity can be further improved. According to the semiconductor device of the ninth aspect, the same functions and effects as those of the semiconductor device of the seventh aspect can be obtained except for the miniaturization. According to the semiconductor device of the tenth aspect, the step of curing the insulating filler is not required, and the productivity can be improved. In addition, no void is generated in the insulating filler, and the reliability can be improved.

According to the semiconductor device of the eleventh aspect, the positioning of the conductor with respect to the electrode on the upper surface of the semiconductor element can be performed by the insulating plate, and the assembling accuracy can be improved. According to the semiconductor device of the twelfth aspect, the same effects as those of the semiconductor device of the eleventh aspect can be obtained, and the processing of the insulating sheet is easy, so that the productivity can be further improved.

According to the semiconductor device of the thirteenth aspect, the pressure contact between the lower metal insulating substrate and the upper metal insulating substrate with respect to the semiconductor element is increased by the contraction force at the time of curing of the mold resin.
Reliability can be improved. According to the semiconductor device of the fourteenth aspect, the relative displacement of the semiconductor element with respect to the lower metal insulating substrate and the upper metal insulating substrate can be suppressed, and assembling accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a completed state of an entire semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a characteristic diagram

FIG. 3 is a longitudinal sectional view showing a heating process state of the whole semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a view corresponding to FIG. 1, showing a third embodiment of the present invention;

FIG. 5 is a view corresponding to FIG. 3, showing a fourth embodiment of the present invention.

FIG. 6 is a longitudinal sectional view showing a solder bump manufacturing process state according to a fifth embodiment of the present invention.

FIG. 7 is a view corresponding to FIG. 6, showing a sixth embodiment of the present invention;

FIG. 8 is a view corresponding to FIG. 1, showing a seventh embodiment of the present invention.

FIG. 9 is a view corresponding to FIG. 1, showing an eighth embodiment of the present invention.

FIG. 10 is a view corresponding to FIG. 1, showing a ninth embodiment of the present invention;

FIG. 11 is a view corresponding to FIG. 1, showing a tenth embodiment of the present invention;

FIG. 12 is a view corresponding to FIG. 1, showing an eleventh embodiment of the present invention.

FIG. 13 is a view corresponding to FIG. 1, showing a twelfth embodiment of the present invention.

FIG. 14 is a diagram corresponding to FIG. 1 showing a conventional example.

[Explanation of symbols]

21 is a lower metal insulating substrate, 24a to 24c are electrodes, 25 to
27 is a solder paste, 31 is a semiconductor element, 31a,
31b is an electrode, 32 is a solder dump, 33 is a semiconductor element, 33a and 33b are electrodes, 34 is a semiconductor element, 34
a and 34b are electrodes, 35 and 36 are solder dumps, 40 is an upper metal insulating substrate, 43a to 43d are electrodes, 44 to 48 are solder pastes, 53 is a silicon gel, 62 is a lower heating plate, 64 is an upper heating plate, 71 is a metal insulating substrate on both upper surfaces, 75a
75f is an electrode, 76a to 76d are electrodes, 77 to 81 are solder pastes, 87 to 96 are solder pastes, 9
9, 100, 102 and 103 are chip components (other electronic components), 101 is an IC (other electronic components), 111, 112
Is a positioning hole, 113 is a positioning jig, 114 is a pin, 115 is a spacer, 121 is a lower jig, 122 is a recess, 124 is an upper jig, 126 is a through hole, 127 is solder, and 131 is solder. Lower mold jig, 132 is a concave portion, 133 is a heat sink, 134 is solder for heat sink, 136 is an upper mold, 13
8 is a through hole, 139, 141 to 143 are solder, 146
148 is a conductor, 149 is a fixing member, 153a to 153
3d is an electrode, 154 is an upper metal insulating substrate, 161-163
Is a recess, 164 to 166 are holes, 167 is an insulating plate, 171 to 173 are recesses, 174 is an insulating sheet, 1
75 to 177 are holes, 178 is an insulating sheet, 181-1
83 is a silicon gel, 184 and 185 are spaces.

Claims (14)

[Claims] A semiconductor element having an upper electrode provided with a solder bump is mounted on the lower metal insulating substrate so as to be in contact with the lower electrode; An upper metal insulating substrate having a solder paste adhered to a lower electrode is mounted on a solder bump of the element, and these are heated to melt both of the solder pastes. A method of manufacturing a semiconductor device, comprising joining an electrode on an upper surface of an insulating substrate, and an electrode on an upper surface of a semiconductor element and an electrode on a lower surface of an upper metal insulating substrate. 2. The semiconductor device according to claim 1, wherein the heat melting of both solder pastes is performed by heat conduction from a hot plate in contact with each metal base of the lower metal insulating substrate and the upper metal insulating substrate. Production method. 3. A double-sided substrate having electrodes on both upper and lower surfaces instead of at least one of the lower metal insulating substrate and the upper metal insulating substrate, and another electronic component is mounted on the electrode on the outer surface thereof. 3. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. A positioning hole is formed at each corner of the upper and lower substrates, the hole is fitted to a pin of a positioning jig and positioned, and a spacer is provided between the upper and lower substrates. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the dimension between the upper and lower substrates can be adjusted by changing the height of the spacer. 5. A semiconductor device is arranged in a recess of a lower jig,
The upper surface of the semiconductor element is covered with an upper jig, and the solder arranged in the through hole of the upper jig is heated and melted to form a solder bump, and the through hole of the upper jig is formed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the size of the solder bumps can be changed by changing the size of the solder disposed thereon. 6. A heat sink and a solder for the heat sink are sequentially arranged in the concave portion of the lower mold before the semiconductor element, and the solder arranged in the through hole of the upper mold is heated and melted. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the solder for the heat sink is heated and melted to form the solder bumps and to join the heat sink to the semiconductor element. 7. A lower metal insulating substrate having an electrode on an upper surface, and electrodes on upper and lower surfaces, and an electrode on a lower surface thereof is joined to an electrode on an upper surface of the lower metal insulating substrate by solder or a conductive adhesive. A mounted semiconductor element, a conductor disposed on an electrode on an upper surface of the semiconductor element, electrodes on both upper and lower surfaces, and an electrode on a lower surface thereof is connected to the upper surface of the semiconductor element via the conductor. And a silicon gel filled between the upper metal insulating substrate and the lower metal insulating substrate. 8. An electrode on the upper surface of the lower metal insulating substrate is bonded by pressing to an electrode on the upper surface of the lower metal insulating substrate instead of bonding the electrode on the lower surface of the semiconductor element to the electrode on the upper surface of the lower metal insulating substrate by solder or a conductive adhesive. The semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 7, wherein an upper metal insulating substrate having electrodes only on the lower surface is used instead of the upper metal insulating substrate having electrodes on both upper and lower surfaces. 10. The method according to claim 7, wherein an insulating gas is filled between the upper metal insulating substrate and the lower metal insulating substrate instead of filling the silicon gel. 13. The semiconductor device according to claim 1. 11. An insulating plate having a concave portion surrounding a semiconductor element and a hole surrounding a conductor, instead of filling a silicon gel between an upper metal insulating substrate and the lower metal insulating substrate. 10. The semiconductor device according to claim 7, wherein: 12. A first insulating sheet having a recess surrounding a semiconductor element between an upper metal insulating substrate and the lower metal insulating substrate instead of filling a silicon gel, and surrounding a conductor. 10. The semiconductor device according to claim 7, further comprising a second insulating sheet having holes formed therein. 13. The method according to claim 7, wherein a mold resin is filled between the upper metal insulating substrate and the lower metal insulating substrate instead of filling the silicon gel. Semiconductor device. 14. Instead of filling a silicon gel between the upper metal insulating substrate and the lower metal insulating substrate, the semiconductor elements are individually sealed with a silicon gel or a mold resin, and each of the sealed portions is sealed. 10. The semiconductor device according to claim 7, wherein a space is provided between the semiconductor devices.