JP2004152861A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having sufficient serge inhibitable capacity by adopting a simple C snubber circuit or the like. <P>SOLUTION: In the case that the semiconductor device has large capacity, a plurality of numbers of chips (1) are often connected in parallel, and large capacity is realized. In the semiconductor device, snubber connection terminals (4, 5) are arranged to each of the chips (1), and individual snubber circuits are arranged to the snubber connection terminals (4, 5). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a snubber circuit.
[0002]
[Prior art]
In a power semiconductor device, in order to suppress a surge voltage generated during switching,
(1) Increase the gate resistance to shorten the switching time,
(2) A method of absorbing a surge voltage with a snubber circuit is generally employed.
As the semiconductor device becomes larger in capacity, the surge voltage becomes higher. Therefore, it is necessary to further strengthen the methods (1) and (2).
[0003]
As input / output protection of an integrated circuit, a common input / output protection device is connected to a plurality of external terminals (for example, see Patent Document 1).
[0004]
As electrostatic protection of a semiconductor integrated circuit, two or more bonding pads share one electrostatic protection circuit (for example, see Patent Document 2).
[0005]
As a capacitor of a snubber circuit used for a switching element, a junction capacitance between a collector and a base of a MOSFET or a bipolar transistor is used (for example, see Patent Document 3).
[0006]
[Patent Document 1]
JP-A-5-75023 "I / O protection device for integrated circuit" (Claim 1, FIG. 1)
[0007]
[Patent Document 2]
Japanese Patent Application Laid-Open No. 2-151630, "Electrostatic protection circuit for semiconductor integrated circuit"
[0008]
[Patent Document 3]
JP-A-3-178214, "Snubber circuit of power semiconductor device" (Claim 1, FIG. 1)
[0009]
[Problems to be solved by the invention]
In the above method (1), in the case of a large capacity, switching loss increases and cooling capacity needs to be increased. According to the method (2) and Patent Documents 2 and 3, a snubber (C snubber) circuit using only a capacitor can sufficiently obtain an effect with a small capacitance element, whereas a capacitor, a resistor, and a diode can be obtained with a large capacitance element. The effect was not obtained unless complicated wiring such as a combined snubber (CRD snubber) circuit was taken.
[0010]
The present invention provides a semiconductor device having a sufficient surge suppression capability by employing a simple C snubber circuit or the like.
[0011]
[Means for Solving the Problems]
When a semiconductor device has a large capacity, a large capacity is often achieved by connecting a plurality of chips in parallel. According to the present invention, a snubber connection terminal is provided for each chip in such a semiconductor device, and an individual snubber circuit is provided for each of the snubber connection terminals.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows a large capacity element 21 according to the first embodiment of the present invention. As shown in the figure, this large-capacity element 21 connects four chips 1 provided on an insulating substrate in parallel, and the main terminals 2 and 3 are commonly used to constitute one large-capacity element. Snubber connection terminals 4 and 5 are provided for these chips 1, and snubber circuits are individually provided for each chip 1.
[0013]
A well-known snubber circuit is connected to the snubber connection terminals 4 and 5. When a snubber circuit is connected to each chip as described above, even if a simple C snubber circuit using only a capacitor is used, the surge voltage can be reduced. It can be suppressed sufficiently.
[0014]
Embodiment 2 FIG.
FIG. 2 shows a large-capacity element 22 according to the second embodiment of the present invention. The large-capacity element 22 is composed of a single chip 11 on an insulating substrate. The chip 11 is divided into a plurality of cells 11a, and snubber connection terminals 4 and 5 are provided in each cell 11a. Provide a circuit. In this case, similarly to the first embodiment, the surge voltage can be sufficiently suppressed only by the C snubber circuit.
[0015]
Embodiment 3 FIG.
FIG. 3 shows a configuration diagram (left diagram) of a transistor according to Embodiment 3 of the present invention and an equivalent circuit (right diagram) thereof. The wiring pattern 6 is divided into a pattern under the emitter electrode (6a) and a pattern under the emitter electrode (6b), and the wiring pattern 6b is used as a pattern of the entire surface. Then, the wiring pattern 6b is connected to the emitter E using the wire 7.
[0016]
Another wiring pattern 9 is located below the wiring patterns 6a and 6b with the insulator 8 interposed therebetween. In this case, a capacitor CAP1 is formed between the wiring pattern 6a and the wiring pattern 9 by the insulator 8, and a capacitor CAP2 is formed between the wiring pattern 6b and the wiring pattern 9 by the insulator 8. 3, the capacitors CAP1 and CAP2 are connected in series between the collector C and the emitter E.
[0017]
This capacitor functions as a capacitor of the C snubber circuit. In the third embodiment, a snubber circuit is formed at a location very close to the chip, and the unused substrate pattern 6b can be used.
[0018]
【The invention's effect】
According to the present invention, a snubber connection terminal is provided for each chip constituting the semiconductor device, and a snubber circuit is connected to each snubber connection terminal. The effect can be sufficiently obtained, and the connection of the snubber circuit is facilitated.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a perspective view of a semiconductor device according to a second embodiment of the present invention; FIG. Cross-sectional view and equivalent circuit diagram of the transistor shown.
DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 2 main terminals, 3 main terminals, 4 snubber connection terminals, 5 snubber connection terminals, 6 wiring patterns, 7 wires, 8 insulators, 9 board patterns, 21 large capacity elements, 22 large capacity elements

Claims (4)

A semiconductor device, wherein a snubber connection terminal is provided for each chip constituting the semiconductor device. A semiconductor device, wherein a single large-capacity chip is divided into several cell units, and a snubber connection terminal is provided for each of the divided cells. 3. The semiconductor device according to claim 1, wherein a C snubber circuit is connected to each of said snubber connection terminals. 4. The semiconductor device according to claim 1, wherein a stray capacitance on the substrate is used as a capacitor of the snubber circuit.

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