JPS5958853A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5958853A
JPS5958853A JP57169988A JP16998882A JPS5958853A JP S5958853 A JPS5958853 A JP S5958853A JP 57169988 A JP57169988 A JP 57169988A JP 16998882 A JP16998882 A JP 16998882A JP S5958853 A JPS5958853 A JP S5958853A
Authority
JP
Japan
Prior art keywords
transistor
capacitor
circuit
emitter
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57169988A
Other languages
Japanese (ja)
Inventor
Yasutaka Nakatani
中谷　安孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57169988A priority Critical patent/JPS5958853A/en
Publication of JPS5958853A publication Critical patent/JPS5958853A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a high speed switching seiconductor element by a method wherein a capacitor nearly the same or more with input transition capacity of the element is connected in parallel with the circuit of the emitter and the base of the semiconductor element. CONSTITUTION:When the capacitor of the extent of 0.8-3 times of input transition capacity of the power transistor 1 is connected in parallel with the circuit of the emitter and the base of the transistor thereof, a spike and ringing can be controlled without reducing efficiency to enable to suppress generation of noise, and moreover destruction of the transistor 1 itself also can be checked. When a switching electric power source is constructed using the transistor formed according to this construction, an outside circuit for shaping of a waveform is also made unnecessary, the device can be made in a small type and in light weight, and the high speed switching device of high efficiency and low noise can be obtained.

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 本発明は半導体装置に係り、特に高周波スイッチング電
源を低雑音・小型・軽量・高効率化し得る高速パワート
ランジスタの構成に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a structure of a high-speed power transistor that can make a high-frequency switching power supply low-noise, compact, lightweight, and highly efficient.

（ｂｌ　　従来技術と問題点 近年に至り各種電子機器が小型化、軽量化されるに伴い
、その電源としてスイッチング電源が多く使用されてい
る。このスイッチング電源は電源を小型化、軽量化、高
効率化することを目的として開発されたものであって、
在来の負荷に直列に接続したトランジスタに電力を消費
させる方式の、所謂シリーズ・レギュレータに比較して
、トランスが小型化されること及び余分な電力消費が減
少することから、電源全体が小型化、軽量化されるとと
もに、変換効率が高まるという長所を有する。(bl) Prior Art and Problems In recent years, as various electronic devices have become smaller and lighter, switching power supplies have been increasingly used as power sources.This switching power supply makes power supplies smaller, lighter, and more efficient. It was developed for the purpose of
Compared to a conventional series regulator, which consumes power through a transistor connected in series with the load, the transformer is smaller and excess power consumption is reduced, making the entire power supply smaller. , it has the advantage of being lightweight and increasing conversion efficiency.

しかしスイッチング電源は、スイッチング周波数が低い
場合は雑音は比較的少ないが、トランスやコンデンサ等
をそれ程小さく出来ないため、電源の小型化、軽量化に
限度がある。スイッチング周波数を高くすると、トラン
ス等は小さく出来るので電源を小型化、軽量化し得るが
、主スイツチング素子のパワートランジスタのオン・オ
フ時（特にオフ時）に発生するスパイクやリンギングに
よる雑音が大となる。この雑音の問題は単に可聴雑音の
発生という問題のみならず、周波数が１００（ｋ　Ｈ２
）あるいは２００　（ｋ　１１２）と高まると、電波障
害が発生する恐れがある。However, switching power supplies have relatively low noise when the switching frequency is low, but because transformers, capacitors, etc. cannot be made that small, there are limits to how much the power supply can be made smaller and lighter. If the switching frequency is increased, the transformer etc. can be made smaller, making the power supply smaller and lighter, but this increases noise due to spikes and ringing that occur when the power transistor, the main switching element, turns on and off (especially when it turns off). . The problem with this noise is not only the generation of audible noise, but also the frequency of 100 (k H2
) or 200 (k 112), there is a risk of radio interference.

このような問題があるため従来のパワー１−ランジスタ
を使用するスイッチング電源は、スイッチング周波数を
高くすることが困難であった。Due to these problems, it has been difficult to increase the switching frequency of conventional switching power supplies using power transistors.

−力率導体装置がＬＳ　１．超ＬＳＩとますます高築梢
化されるにつれて、電子機器の小型化、軽量化が急速に
進め、電子機器中に占める電源の寸法・重量の比率が相
対的に増大し、電源のより小型化、軽量化が急務となっ
ている。このため雑音発生の少ない高周波スイッチング
電源の出現が強く望まれている。- Power factor conductor device is LS 1. As ultra LSIs and architectures become increasingly sophisticated, electronic devices are rapidly becoming smaller and lighter, and the size and weight ratio of power supplies in electronic devices has increased relatively, leading to smaller power supplies. , weight reduction is an urgent need. For this reason, there is a strong desire for a high frequency switching power supply that generates less noise.

（Ｃ１発明の目的 本発明は上記問題点を解消し、オン・オフ時にスパイク
やリンギングの発生の少ない高速スイッチング・パワー
トランジスタを提供することにある。(C1 Object of the Invention The object of the present invention is to solve the above-mentioned problems and provide a high-speed switching power transistor that causes less spikes and ringing when turned on and off.

（ｄｉ　　発明の構成 本発明の特徴は、半導体素子と、該半導体素子の入力遷
移容量と略同等或いはそれ以上の容量を有し、該半導体
素子のエミッタ及びベース間に並列に接続されたコンデ
ンサとが、同一パンケージ内に収容されてなることにあ
る。(di) Structure of the Invention The present invention is characterized by a semiconductor element, a capacitor having a capacitance substantially equal to or greater than the input transition capacitance of the semiconductor element, and connected in parallel between the emitter and base of the semiconductor element. are housed in the same pan cage.

（ｅｌ　　発明の実施例 以下本発明の一実施例を、図面を参照しながら本発明の
発明者らは前述のスパイクとリンギングを抑制し得る高
速パワートランジスタを実現すべく種々検討の結果、第
１図に示す如くパワー１−ランジスタ素子１と、該パワ
ー１−ランジスタ素子１の入力遷移容量と略同等の容量
を有するコンデンサ２をパワートランジスタ素子ｌのベ
ース−エミッタ間に並列に接続し、この両者を同一バフ
ケージ３内に収容すれば良いことを見いだした。(el Embodiment of the Invention) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.The inventors of the present invention have conducted various studies to realize a high-speed power transistor capable of suppressing the spikes and ringing described above. As shown in the figure, a power 1 transistor element 1 and a capacitor 2 having a capacitance approximately equal to the input transition capacitance of the power 1 transistor element 1 are connected in parallel between the base and emitter of the power transistor element 1. It has been found that it is sufficient to house them in the same buff cage 3.

なお同図において、４はキャップであるが、パッケージ
３の内部を示すため、キャップ４は一部のみを図示しで
ある。また５は金属ステム、６はパワートランジスタ素
子ｌのエミッタ端子、７はそのベース端子、８及び９は
ステム５のエミッタ・リード及びベース・リード、１ｏ
は金属細線で例えばアルミニウム（Ａβ）線である。な
おリード８．９は、金属ステム５にガラス１１により絶
縁されて支持される。In the same figure, 4 is a cap, but in order to show the inside of the package 3, only a portion of the cap 4 is shown. Further, 5 is a metal stem, 6 is an emitter terminal of the power transistor element l, 7 is its base terminal, 8 and 9 are emitter leads and base leads of the stem 5, 1o
is a thin metal wire, for example, an aluminum (Aβ) wire. Note that the lead 8.9 is supported by the metal stem 5 while being insulated by the glass 11.

第２図は上記第１図に示した本実施例のパワートランジ
スタＴｒを用いたスイッチング回路の要部を示す回路図
で、Ｌは負荷のインダクタンス、Ｒはバイアス抵抗であ
る。FIG. 2 is a circuit diagram showing a main part of a switching circuit using the power transistor Tr of this embodiment shown in FIG. 1, where L is the inductance of the load and R is the bias resistance.

第３図は上記第２図の回路において、パワートランジス
タ素子内に具備せしめたコンデンサ２の容量を種々の値
に変えたときの、ベース−エミッタ間電圧ＶＩＩＦ及び
ベース電流ＩＢを示す曲線図である。なお本実施例のパ
ワートランジスタ素子１の入力遷移容量は約７　　（ｎ
Ｆ）である。FIG. 3 is a curve diagram showing the base-emitter voltage VIIF and base current IB when the capacitance of the capacitor 2 provided in the power transistor element is changed to various values in the circuit shown in FIG. 2 above. . Note that the input transition capacitance of the power transistor element 1 of this embodiment is approximately 7 (n
F).

同図（ａ＋〜（Ｃ１は、（＝Ｊ加したコンデンサ２の容
量Ｃをそれぞれ０．６．８．４４　（ｎ　Ｆ）とした場
合を示すものである。The figure (a+ to (C1) shows the case where the capacitance C of the capacitor 2 (=J plus) is respectively 0.6.8.44 (n F).

Ｃ−０の場合には、同図（ａｌの下側の曲線に見られる
如くベース電流ＩＢには大きなスパイ・り２１とリンギ
ング（細かい振動）２２が発生する。付加容量Ｃを約６
．８（ｎＦ）とすると、スパイク２１はかなり小さくな
りリンギングは大幅に減少する。更にＣ＝４４（ｎＦ）
とすると、スパイク、リンギングとも殆ど消滅する。し
かしフォールタイムを十が長くなり、スイッチング損失
が増大する。In the case of C-0, a large spike 21 and ringing (fine vibration) 22 occur in the base current IB as seen in the lower curve of the figure (al).
．． 8 (nF), the spike 21 becomes considerably smaller and ringing is significantly reduced. Furthermore, C=44 (nF)
If so, both spikes and ringing will almost disappear. However, the fall time becomes longer and switching loss increases.

以上の結果より主スイツチング素子のパワートランジス
タ素子工のエミッターベース間に適当な容量を並列に接
続することによって、効率を低下させることなくスパイ
ク及びリンギングを抑制し得る、即ち雑音の発生を押さ
えることが可能である。上記付加容量としては、パワー
トランジスタ素子１の入力遷移容量の０．８〜３倍程度
が望ましいようである。The above results show that by connecting an appropriate capacitor in parallel between the emitter and base of the power transistor element of the main switching element, it is possible to suppress spikes and ringing without reducing efficiency, that is, to suppress the generation of noise. It is possible. It seems desirable that the additional capacitance be about 0.8 to 3 times the input transition capacitance of the power transistor element 1.

上述のように大電流のスイッチング時に発生ずるスパイ
ク及びリンギングが抑制されると、外部に放射される雑
音が減少するのみでなく、パワートランジスタ素子１自
身の破壊も防止去れるという効果がある。更に本実施例
のパワートランジスタＴｒを用いてスイッチング電源を
作成すれば、通常コレクターエミッタ間にダイオード、
抵抗、コンデンサを用いて構成される波形を整形するた
めの外部回路（スナバ−回路）が不要となるという付加
的効果もある。As described above, suppressing the spikes and ringing that occur during switching of large currents not only reduces the noise radiated to the outside, but also prevents damage to the power transistor element 1 itself. Furthermore, if a switching power supply is created using the power transistor Tr of this embodiment, a diode,
An additional effect is that an external circuit (snubber circuit) for shaping a waveform configured using a resistor and a capacitor is not required.

なお上記一実施例では同一バラケージ３内にパワートラ
ンジスタ素子１と、これとは別に作成されたコンデンサ
２とを収容した例を示したが、本発明はこれを更に変形
して実施し得る。Although the above-mentioned embodiment shows an example in which the power transistor element 1 and the capacitor 2 manufactured separately from the power transistor element 1 are housed in the same barrier cage 3, the present invention can be implemented by further modifying this.

ｆｆ１ｌち、同一ヂツブ内にパワートランジスタ素子と
コンデンサとを一体的に形成し、両者をチップ」二に形
成した配線或いはアルミニウム（Ａβ）細線等で接続し
、これをパッケージに収容することによっても本発明を
実施し得る。ff1l, this can also be achieved by integrally forming a power transistor element and a capacitor in the same chip, connecting them with wires formed on a chip or thin aluminum (Aβ) wires, and accommodating this in a package. The invention can be put into practice.

（ｆｌ　　発明の詳細 な説明した如く、本発明により高効率、低雑音の高速ス
イッチング用パワートランジスタが提供され、スイッチ
ング電源のスイッチング周波数が高周波化され、小型化
、軽量化且つ高効率化される。(fl) As described in detail, the present invention provides a high-efficiency, low-noise, high-speed switching power transistor, which increases the switching frequency of a switching power supply, making it smaller, lighter, and more efficient.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す要部斜視図、第２図は
上記−実施例を用いたスイッチング回路の要部を示す回
路図、第３図は上記一実施例の効果を示す曲線図である
。 図において、Ｉはパワートランジスタ素子・　２はコン
デンサ、３はパッケージ、６及び７はパワートランジス
タ素子１のエミッタ端子及びベース端子、２１はスパイ
クを示す。 ｄご！１サヨ 第１図 第２団　　　　　　　　３ 第３図 （Ｖ）Fig. 1 is a perspective view of a main part showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a main part of a switching circuit using the above embodiment, and Fig. 3 shows the effect of the above embodiment. It is a curve diagram. In the figure, I is a power transistor element, 2 is a capacitor, 3 is a package, 6 and 7 are the emitter terminal and base terminal of the power transistor element 1, and 21 is a spike. d-go! 1 Sayo Figure 1 2nd Group 3 Figure 3 (V)

Claims (1)

【特許請求の範囲】[Claims] 半導体素子と、該半導体素子の入力遷移容量と略同等或
いはそれ以上の容量を有し、該半導体素子のエミッタ及
びベース間に並列に接続されたコンデンサとが、同一パ
ッケージ内に収容されてなることを特徴とする半導体装
置。A semiconductor element and a capacitor having a capacitance substantially equal to or greater than the input transition capacitance of the semiconductor element and connected in parallel between the emitter and base of the semiconductor element are housed in the same package. A semiconductor device characterized by:
JP57169988A 1982-09-28 1982-09-28 Semiconductor device Pending JPS5958853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57169988A JPS5958853A (en) 1982-09-28 1982-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57169988A JPS5958853A (en) 1982-09-28 1982-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5958853A true JPS5958853A (en) 1984-04-04

Family

ID=15896511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57169988A Pending JPS5958853A (en) 1982-09-28 1982-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5958853A (en)

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