JPS6033714Y2 - Thyristor surge suppressor - Google Patents

Description

[Detailed description of the invention] The present invention relates to a surge suppression device that suppresses surges that occur during commutation dry prevention of elements, and is intended to provide a surge suppression device that is particularly suitable for devices to which gate turn-off thyristors are applied. .

In general, gate turn-off thyristors (hereinafter abbreviated as GTO) are 0N-OFF at the gate compared to normal thyristors.
For example, it does not require much consideration in terms of commutation and has excellent characteristics such as being able to maintain a very high switching frequency. Inverter or AC type,
It is being applied to DC type non-commutator motors, etc.

However, GTO has a much higher switching frequency than normal thyrisk, so the rate of change in current is large, and the rate of increase in forward voltage (dv/dt '1 and its peak value, as well as the rate of increase in forward current) that occurs at the time of commutation is (dv/dt) etc., if not effectively suppressed, permanent destruction will occur.

In this way, dv/dt, its peak value and dv/dt
The effects of this are much more serious than those of ordinary thyristors.

As a circuit for suppressing dv/dt etc. applied to the GTO at the time of this kind of commutation, a circuit example as shown in FIG. 1 is generally applied.

That is, a surge suppression circuit consisting of a capacitor C, a resistor R, and a diode D is connected between the terminals of the GTO so that dv /dt and its peak value are suppressed by this surge suppression circuit, and a reactor L connected in series with the GTO is used. dedv7'
dt, is suppressed.

FIG. 2 shows an example in which the GTO and surge suppression circuit shown in FIG. 1 are arranged in an actual device.

In Fig. 2, F denotes a cooling fin, and the cooling fin and surge suppression circuit are connected to the cooling fin F by pulling out lead wires l from the upper and lower ends of the cooling fin F, for example, as shown in the figure. and the surge absorption circuit are connected.

The problem with such a configuration is that the dv/dt at turn-off of the GTO is large, and the switching loss also increases, so that in the worst case, the GTO may be destroyed.

To explain this specifically with reference to the waveform diagram in Figure 3,
Assume that the GTO is turned off by supplying an off-gate current to the on-state GTO.

When the GTO turns off, a current i flows from the positive side of the main circuit through the path from capacitor C to diode D.

flows, and the capacitor C is charged to approximately the power supply voltage with the polarity shown.

The charging voltage of this capacitor C becomes the voltage between the terminals of the GTO.

That is, in the waveform diagram of FIG. 3, when the GTO is turned off, the current iC flowing through the GTO rapidly becomes zero as time passes.

A current commensurate with the decrease in current ic flows through capacitor C, and the charging voltage of capacitor C, that is, the voltage between terminals of GTO VC increases with a time constant determined by capacitor C and resistor R, and finally approximately It becomes constant when the power supply voltage value Ed is reached.

What poses a threat to the GTO during this turn-off process is the dv/dt of the GTO terminal voltage Vc, as shown in the figure (dv/dt).
t indicates the peak value A at the beginning of charging of the capacitor C.

The reason why dv/dt exhibits the peak value A in this way is that the energy stored in the wiring inductance of the main circuit of reactor L1 and the inductance of the cooling fins shown in Fig. 1 is absorbed by the capacitor C. On the other hand, the current ic flowing through the GTO and the voltage applied to the GTO ■
.

As shown in FIG. 3, the switching loss WC due to this has a very large value.

Conventionally known methods for reducing this type of switching loss include twisting the lead wires l to offset changes in magnetic flux, or minimizing stray capacitance on the wires to reduce the inductance of the wires alone. There are ways to reduce it.

This type of method can suppress dv/dt to some extent, but since the lead wire 1 is drawn out from the upper and lower surfaces of the cooling fin, dv/dt becomes extremely large due to the inductance present in the cooling fin itself. .

In other words, the attenuation rate of the current j c flowing through the GTO is 100OA/
If the inductance of μS1 cooling fin F is 0.1μH, then in the conventional circuit example shown in Fig. 2, o, iμHx 100O
This will induce a dv/dt of A/μs = 1oov, and this dv/dt will pose a great threat to the GTO.

The present invention has been devised in view of this point, and will be described in detail below based on the embodiments shown in FIGS. 4 to 6.

The feature of this embodiment is that the lead wire 1 of the surge absorption circuit is drawn out as close to the GTO as possible, and in the embodiment shown in Fig. 4, the lead wire 1 is first twisted. As shown in the figure, this lead wire 1 is drawn out from the inside of the cooling fin F and placed as close to the GTO as possible.

By pulling out the lead wire 1 inside the cooling fin in this way, it is possible to completely eliminate the influence of the inductance present in the cooling fin, thereby making it possible to effectively suppress dv/dt.

The embodiment shown in FIG. 5 is designed to simplify the structure by using the cooling fins of the diode D of the surge suppression circuit as the cooling fins F of the main GTO. As shown in the figure, the diode D is installed at the side end of the lower cooling fin F so as to be taken out from the side end of the cooling fin F and placed as close to the GTO as possible.

If the cooling fin of diode D is also used as the cooling fin of GTO to simplify the structure, the lower cooling fin F is placed in parallel with the GTO as shown in Fig. 6, and the lead wire 1 of capacitor C is As shown in the figure, if one is drawn out near the GTO of the upper cooling fin F and the other is drawn out directly from the diode D, and the lead wires 1 are twisted, the dv/dt is further increased.
The effect of suppression appears.

Note that the resistor R has no relation to dv/dt, so it can be attached to any part of the cooling fin F, and the embodiments shown in Figs. 5 and 6 show examples in which it is attached to the side of the cooling fin F. There is.

In this way, in this application, if the lead wire 1 of the surge absorption circuit is drawn out from inside the cooling fin F, and moreover from a point as close to the GTO as possible, not only the inductance on the wiring but also the interference between the cooling fins is eliminated. Since the influence of inductance can also be completely removed, effective suppression of dv/dt can be realized, and this is specifically shown in the voltage-current waveform diagram shown in FIG. 7.

In other words, if the configuration is as shown in the embodiment shown in FIG. 6, it is possible to completely eliminate the influence of inductance of cooling fins, lead wires, etc. Therefore, the charging voltage of capacitor C, that is, the rising waveform of dv/dt applied to GTO is as follows. As shown in FIG. 7, the dv/dt peak value is very gradual, and the peak value of dv/dt caused by reactance etc. has been sufficiently attenuated, so that the i flowing through the GTO.

and the switching loss W due to the voltage Vc applied to the GTO.

As shown in FIG. 7, it becomes extremely small, and as a result, permanent destruction of the GTO can be completely prevented.

As described above, in the present invention, the dv/
In order to take out the lead wire of the surge absorption circuit that suppresses dt and its peak value, etc. from a place as close to the GTO as possible, for example, the structure is such that it is taken out from inside the cooling fin of the GTO, so various effects can be achieved as shown below. It is something to play.

■ Since the structure is designed to completely eliminate the influence of the inductance of the cooling fins, which is the main cause of dv/dt, the most ideal method of suppressing dv/dt can be realized, and permanent damage to elements due to dv/dt etc. can be prevented. It can definitely be prevented.

■ GTO cooling fins for diodes in surge absorption circuits
Since it is designed to be used also as a cooling fin, the structure is simplified and it becomes more advantageous in terms of cost.

■ It can effectively suppress surges even in unstable circuits such as vibration loads, and is especially effective when applied to high-frequency inverters with extremely high switching frequencies.

[Brief explanation of the drawing]

Fig. 1 shows an example of a circuit showing a typical surge suppressor, Fig. 2 shows an example of a conventional arrangement embodying the surge suppressor, and Fig. 3 shows a GTO voltage, current, and switching loss W at turn-off using the conventional device. 4 is a specific arrangement example showing one embodiment of the present invention, FIGS. 5 and 6 are specific arrangement examples showing other embodiments of the present invention, FIG. 7 shows the GTO voltage (■) at turn-off according to this embodiment. . Current i C and switching loss W. A voltage-current waveform diagram showing the relationship between. GTO is a gate turn-off thyristor, C is a capacitor, R is a resistor, D is a diode, F is a cooling fin, and 1 is a lead wire.

Claims (3)

[Scope of utility model registration request] (1) A thyristor element is press-fitted between the upper and lower cooling fins, and a surge suppression circuit consisting of a capacitor resistor and a diode is disposed near the cooling fins via a lead wire to suppress the surge. In a circuit that suppresses the dv/dt or peak value applied to the thyristor element, the lead wire is connected to the inside of the upper cooling fin and the lower cooling fin, and to the thyristor element. A thyristor surge suppression circuit characterized in that the circuit is drawn out as close as possible. (2) The thyristor surge suppression device according to claim 1, wherein the lead wires drawn out from the inside of the upper cooling fin and the inside of the lower cooling fin are twisted together. (3) A utility model registration request in which a cooling fin for cooling a diode of a surge suppression circuit is used as an upper cooling fin or a lower cooling fin of a thyristor element, and a diode is arranged inside the fin. A surge suppression device for a thyristor according to item 1 or 2.