JP2894402B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2894402B2
JP2894402B2 JP4191190A JP19119092A JP2894402B2 JP 2894402 B2 JP2894402 B2 JP 2894402B2 JP 4191190 A JP4191190 A JP 4191190A JP 19119092 A JP19119092 A JP 19119092A JP 2894402 B2 JP2894402 B2 JP 2894402B2
Authority
JP
Japan
Prior art keywords
terminal
semiconductor device
lead wire
conductor
main terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4191190A
Other languages
Japanese (ja)
Other versions
JPH0637222A (en
Inventor
信司 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4191190A priority Critical patent/JP2894402B2/en
Publication of JPH0637222A publication Critical patent/JPH0637222A/en
Application granted granted Critical
Publication of JP2894402B2 publication Critical patent/JP2894402B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Electronic Switches (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、絶縁ゲート形バイポー
ラトランジスタ(IGBT),電界効果形トランジスタ
(MOSFET)などで代表されるMOSゲート形半導
体デバイス,あるいはバイポーラトランジスタなどのパ
ワースイッチング素子を対象とした半導体装置、特にそ
の内部配線構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS gate type semiconductor device represented by an insulated gate type bipolar transistor (IGBT), a field effect type transistor (MOSFET) or the like, or a power switching element such as a bipolar transistor. The present invention relates to a semiconductor device, particularly to an internal wiring structure thereof.

【0002】[0002]

【従来の技術】昨今では、汎用インバータなどに採用す
るパワースイッチング素子として頭記したMOSゲート
形半導体デバイスが多用されている。ところで、前記パ
ワースイッチング素子は、高電圧,大電流を高いスイッ
チング周波数で通電制御する素子であることから、スイ
ッチングタイム,スイッチング損失が小さいことが望ま
れる。そのために、例えば従来の絶縁ゲート形バイポー
ラトランジスタでは、ゲート端子のリード線を主端子か
ら引き離して内部配線するなどしてリード線のインダク
タンス成分を低く抑え、主電流の影響がゲート信号にで
きる限り加わらないなどの対策を講じている。
2. Description of the Related Art Recently, MOS gate type semiconductor devices mentioned above have been frequently used as power switching elements employed in general-purpose inverters and the like. By the way, since the power switching element is an element that controls the conduction of a high voltage and a large current at a high switching frequency, it is desired that the switching time and the switching loss are small. For this reason, for example, in a conventional insulated gate bipolar transistor, the lead wire of the gate terminal is separated from the main terminal and internally wired to reduce the inductance component of the lead wire, and the influence of the main current is applied to the gate signal as much as possible. No countermeasures are taken.

【0003】[0003]

【発明が解決しようとする課題】ところで、前記スイッ
チング素子の高速化を進めると、反面次記のような弊害
が派生する。すなわち、ターンオン,ターンオフ応答速
度の早いスイッチング素子では、ターンオン,ターンオ
フ時の電流変化di/dtが増大し、これが基で発生す
るサージ電圧により素子破壊が生じたり、次のように誤
動作することがある。すなわち、インバータ回路におい
て直列に接続された2個のスイッチング素子(IGB
T)が交互にオン,オフ動作する場合に、オフ側の素子
のコレクタ−エミッタ間にはスイッチング素子に並列接
続したフライホイールダイオード(FWD)の逆回復時
に非常に高いdv/dt電圧が印加され、このdv/d
t電圧でコレクタ−ゲート間の接合容量を充電するよう
に流れる電流がゲート−エミッタ間の電圧をゲートしき
い値以上に高まって誤点弧し、スイッチング素子の直列
短絡に至る場合がある。
By the way, when the speed of the switching element is increased, the following adverse effects are caused. That is, in a switching element having a fast turn-on / turn-off response speed, a current change di / dt at the time of turn-on / turn-off increases, and a surge voltage generated based on the change may cause element destruction or malfunction as follows. . That is, in the inverter circuit, two switching elements (IGB
When T) alternately turns on and off, a very high dv / dt voltage is applied between the collector and the emitter of the off-side element at the time of reverse recovery of a flywheel diode (FWD) connected in parallel with the switching element. , This dv / d
A current flowing to charge the junction capacitance between the collector and the gate with the t voltage may cause the voltage between the gate and the emitter to rise above the gate threshold and cause a false ignition, leading to a series short circuit of the switching elements.

【0004】また、別な問題として、スイッチング素子
を各種装置に組み込んで使用する場合には、素子の動作
特性,特にターンオン速度(ターンオン時間)を適用装
置の動作条件に適合させる必要があり、この観点からタ
ーンオン速度の調整可能なスイッチング素子の出現が要
望されている。本発明は上記の点にかんがみなされたも
のであり、その目的は、内部配線構造を改良することに
より前記課題を解決し、スイッチング動作時に過大なサ
ージ電圧が発生するのを抑えて素子破壊,誤動作を防止
し、併せて用途先の要求に応じてスイッチング動作の速
度を調節できるようにした半導体装置を提供することに
ある。
As another problem, when a switching element is incorporated in various devices for use, it is necessary to adapt the operating characteristics of the device, particularly the turn-on speed (turn-on time), to the operating conditions of the applied device. From the viewpoint, there is a demand for a switching element whose turn-on speed can be adjusted. The present invention has been made in view of the above points, and has as its object to improve the internal wiring structure to solve the above-described problem, suppress generation of an excessive surge voltage at the time of switching operation, and prevent element destruction and malfunction. It is another object of the present invention to provide a semiconductor device capable of preventing the above and adjusting the speed of the switching operation according to the demand of the application.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置においては、補助端子のリード
線の一部を主端子の導体に沿わせて内部配線し、主端子
電流の変化によりリード線に誘起する相互誘導起電力で
制御信号の変化率を低めるように相互誘導結合させるも
のとする。
In order to achieve the above object, in the semiconductor device of the present invention, a part of the lead wire of the auxiliary terminal is internally wired along the conductor of the main terminal, and the current of the main terminal is reduced. Mutually induced coupling is assumed to reduce the rate of change of the control signal by the mutually induced electromotive force induced in the lead wire by the change.

【0006】また、前記構成の実施態様として、補助端
子のリード線をコイル状に巻回して主端子導体に沿わせ
た構成がある。そして、スイッチングタイムの設定を、
主端子導体と補助端子リード線との間の相互誘導結合度
の調整により行うものとする。
Further, as an embodiment of the above-mentioned structure, there is a structure in which a lead wire of an auxiliary terminal is wound in a coil shape so as to follow the main terminal conductor. And the setting of the switching time,
The adjustment is performed by adjusting the mutual inductive coupling between the main terminal conductor and the auxiliary terminal lead wire.

【0007】[0007]

【作用】上記の構成により、半導体装置のスイッチング
動作開始に伴って主端子に流れる電流が変化すると、そ
の電流変化により主端子導体に沿わせた補助端子のリー
ド線には相互誘導起電力が誘起し、この起電力が制御信
号の上昇,下降率を低めて信号波形の立ち上がり,立ち
下がりを緩やかにする。これにより、主端子電流の変化
率di/dtが緩和され、これに起因する過大なサージ
電圧の発生が抑制される。
According to the above arrangement, when the current flowing through the main terminal changes with the start of the switching operation of the semiconductor device, a mutual induced electromotive force is induced on the lead wire of the auxiliary terminal along the main terminal conductor due to the change in current. This electromotive force lowers the rising and falling rates of the control signal, and makes the rising and falling of the signal waveform gentle. As a result, the rate of change di / dt of the main terminal current is reduced, and the occurrence of an excessive surge voltage due to this is suppressed.

【0008】また、この場合に主端子導体に沿わせる補
助端子リード線の長さ,コイル状の巻回数を調節するこ
とにより両者間の相互誘導結合度(相互インダクタン
ス)が変わり、これによりスイッチング動作の速度,つ
まりスイッチングタイムが変化する。したがって、この
機能を利用することで半導体装置のターンオン特性を用
途先の要求に合わせて調節することが可能となる。
In this case, by adjusting the length of the auxiliary terminal lead wire along the main terminal conductor and the number of turns of the coil, the degree of mutual inductive coupling (mutual inductance) between the two is changed, whereby the switching operation is performed. , The switching time changes. Therefore, by using this function, the turn-on characteristics of the semiconductor device can be adjusted according to the requirements of the application.

【0009】[0009]

【実施例】以下本発明の実施例を図面に基づいて説明す
る。まず図1,図2において、1は上面に導体パターン
1a〜1cを形成した絶縁基板、2は基板1の導体パタ
ーン1aにコレクタの電極面を向けてマウントした半導
体素子(IGBT)、3は半導体素子2のコレクタ,ゲ
ート電極と導体パターン1b,1cとの間に配線したボ
ンディングワイヤ、4,5は導体パッケージ1a,1c
に半田付けして上方に立ち上がる銅板製のコレクタ端
子,エミッタ端子(主端子)、6はゲート端子(制御信
号用の補助端子)、7はエミッタ補助端子、8はゲート
端子6と導体パターン1bの端子金具9との間に配線し
たリード線(可撓線)、10はエミッタ補助端子7と導
体パターン1cの端子金具11との間に配線したリード
線(可撓線)であり、これらの各部品は図示されてない
パッケージに組み込まれ、前記の各端子4〜7がパッケ
ージより外部に引出してある。
Embodiments of the present invention will be described below with reference to the drawings. 1 and 2, reference numeral 1 denotes an insulating substrate having conductor patterns 1a to 1c formed on the upper surface, 2 denotes a semiconductor element (IGBT) mounted on the conductor pattern 1a of the substrate 1 with the electrode surface of the collector facing, and 3 denotes a semiconductor. Bonding wires wired between the collector and gate electrodes of the element 2 and the conductor patterns 1b and 1c, and 4 and 5 are conductor packages 1a and 1c.
Collector terminal, emitter terminal (main terminal), 6 is a gate terminal (auxiliary terminal for control signal), 7 is an emitter auxiliary terminal, 8 is a gate terminal 6 and a conductor pattern 1b. The lead wires (flexible wires) wired between the terminal fitting 9 and the lead wires (flexible wires) 10 are wired between the emitter auxiliary terminal 7 and the terminal fitting 11 of the conductor pattern 1c. The components are incorporated in a package (not shown), and the terminals 4 to 7 are drawn out of the package.

【0010】また、前記リード線8,10は配線の途中
箇所がそれぞれコレクタ端子4,エミッタ端子5の導体
に沿わせて相互誘導結合するように配線されている。そ
して、図1の実施例ではリード線8,10がコレクタ端
子4,エミッタ端子5の端子導体に流れる電流と平行な
向きに配線され、図2の実施例ではリード線8,10が
コイル状に巻回してあり、かつリード線8は左ねじ系,
リード線10は右ねじ系に定めてある。
Further, the lead wires 8 and 10 are wired so that the middle portions of the wires are inductively coupled along the conductors of the collector terminal 4 and the emitter terminal 5, respectively. In the embodiment of FIG. 1, the lead wires 8, 10 are wired in a direction parallel to the current flowing through the terminal conductors of the collector terminal 4 and the emitter terminal 5, and in the embodiment of FIG. 2, the lead wires 8, 10 are coiled. Wound, and the lead wire 8 is a left-hand thread system,
The lead wire 10 is defined as a right-hand thread system.

【0011】かかる構成により、半導体素子のスイッチ
ング動作時に主端子(コレクタ端子4,エミッタ端子
5)に流れる電流が変化すると、補助端子(ゲート端子
6,エミッタ補助端子7)のリード線8,10には相互
誘導起電力が誘起し、この起電力が補助端子に入力する
制御信号の急峻な立ち上がり,立ち下がり勾配を低める
ように作用する。
With this configuration, when the current flowing through the main terminals (collector terminal 4 and emitter terminal 5) changes during the switching operation of the semiconductor element, the lead wires 8 and 10 of the auxiliary terminals (gate terminal 6 and emitter auxiliary terminal 7) are connected. Induces a mutual induction electromotive force, and this electromotive force acts to reduce the steep rising and falling gradients of the control signal input to the auxiliary terminal.

【0012】次に、前記構成による半導体装置のターン
オン特性を図3により具体的に説明する。なお、図3
(a)は半導体装置の等価回路図,図3(b)は電圧,
電流の波形図を表しており、図中でCはコレクタ端子,
Eはエミッタ端子,eはエミッタ補助端子,Gはゲート
端子を表し、またvs は制御信号として ゲート端子G
とエミッタ補助端子eとの間に外部から印加したステッ
プ状のドライブ電圧、iはコレクタ電流、vm は相互誘
導起電力(vm =M・di/dt,M:相互インダクタ
ンス)、vg は素子のゲート電極に加わる電圧である。
Next, the turn-on characteristics of the semiconductor device having the above configuration will be described in detail with reference to FIG. Note that FIG.
3A is an equivalent circuit diagram of the semiconductor device, FIG.
It shows the current waveform diagram, where C is the collector terminal,
E is an emitter terminal, e is the emitter auxiliary terminal, G represents a gate terminal, and v s is the gate terminal G as a control signal
Induced electromotive force mutually collector current, v m stepped drive voltage, i is the externally applied between the emitter auxiliary terminal e and (v m = M · di / dt, M: mutual inductance), v g is This is the voltage applied to the gate electrode of the device.

【0013】すなわち、ターンオン時にG端子とe端子
との間に急峻に立ち上がるステップ状のドライブ電圧v
s を印加してコレクタ電流iが流れ始めると、相互誘導
起電力vm が誘起して電圧vs に対して逆向きに作用す
る。これにより、素子のゲート電極に加わる電圧vg
実線で表すように立ち上がり勾配が緩やかになり、これ
に比例してコレクタ電流iの上昇率di/dtが実線の
ように低く抑えられる。なお、ターンオフ時には前記と
逆の作用によりコレクタ電流の急激な立ち下がりを緩和
する。これにより、先述した素子内での過大なサージ電
圧の発生を抑えて素子破壊,誤動作を防止できる。な
お、(b)図に点線で表したコレクタ電流i,ゲート電
圧vg の波形は従来構造の半導体装置における波形を示
したものであり、その立ち上がり勾配は実線に比べて急
峻である。
That is, a step-like drive voltage v that rises sharply between the G terminal and the e terminal at turn-on.
the collector current i starts to flow by applying s, acts in the opposite direction to the voltage v s are mutually induced electromotive force v m is induced. Thus, the voltage v g applied to the gate electrode of the element becomes gentle rises gradient as represented by a solid line, increase rate di / dt of the collector current i is suppressed as indicated by a solid line low in proportion thereto. At the time of turn-off, a sharp fall of the collector current is mitigated by the reverse operation. Thus, generation of an excessive surge voltage in the element described above can be suppressed, and element destruction and malfunction can be prevented. Incidentally, (b) a collector current i expressed by a dotted line in the figure, the waveform of the gate voltage v g is shows the waveforms in the semiconductor device of the conventional structure, the rising gradient that is steeper than the solid line.

【0014】また、図1,図2の構成において、コレク
タ端子4,エミッタ端子5の端子導体に沿わせたリード
8,10の長さ寸法,コイルの巻回数を変えることによ
り主端子との間の相互誘導結合度が変わり、これにより
スイッチング特性も変化する。したがって、半導体装置
の組立工程で補助端子のリード線を内部配線する際に、
主端子と補助端子リード線との間の相互誘導結合度を調
整することにより、半導体装置のターンオン速度を用途
先の要求に合わせて設定することができる。
1 and 2, the length of the leads 8, 10 along the terminal conductors of the collector terminal 4 and the emitter terminal 5 and the number of turns of the coil are changed to change the length between the main terminals. Changes the degree of mutual inductive coupling, thereby changing the switching characteristics. Therefore, when the lead wire of the auxiliary terminal is internally wired in the process of assembling the semiconductor device,
By adjusting the degree of mutual induction coupling between the main terminal and the auxiliary terminal lead wire, the turn-on speed of the semiconductor device can be set according to the requirements of the application.

【0015】[0015]

【発明の効果】以上述べたように本発明の構成によれ
ば、半導体装置の内部配線構造の上で、補助端子のリー
ド線の一部を主端子の導体に沿わせて両者間を相互誘導
結合させる簡単な手段を施すことにより、半導体素子の
スイッチング動作時に生じる過大なサージ電圧を抑制し
て素子破壊,誤動作を防止することができる他、前記の
相互誘導結合度を調節することにより、用途先の要求に
応じて半導体装置のスイッチングタイム,つまりターン
オン速度を容易に調整できるなどの効果が得られる。
As described above, according to the structure of the present invention, on the internal wiring structure of the semiconductor device, a part of the lead wire of the auxiliary terminal is arranged along the conductor of the main terminal to mutually guide the two. By providing a simple means for coupling, it is possible to suppress an excessive surge voltage generated at the time of a switching operation of the semiconductor element to prevent element destruction and malfunction, and to adjust the degree of mutual inductive coupling to achieve a purpose. The switching time of the semiconductor device, that is, the turn-on speed of the semiconductor device can be easily adjusted in accordance with the above-mentioned requirements.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例による半導体装置の組立構成図FIG. 1 is an assembly configuration diagram of a semiconductor device according to an embodiment of the present invention.

【図2】図1と異なる実施例の組立構成図FIG. 2 is an assembly configuration diagram of an embodiment different from FIG.

【図3】図1,図2の実施例によるスイッチング動作特
性の説明図であり、(a)は半導体装置の等価回路図、
(b)はターンオン動作時の電圧,電流波形を表す図
3A and 3B are explanatory diagrams of switching operation characteristics according to the embodiment of FIGS. 1 and 2; FIG. 3A is an equivalent circuit diagram of a semiconductor device;
(B) is a diagram showing voltage and current waveforms at the time of turn-on operation.

【符号の説明】[Explanation of symbols]

1 基板 2 半導体素子(絶縁ゲート形バイポーラトランジス
タ) 4 コレクタ端子 5 エミッタ端子 6 ゲート端子 7 エミッタ補助端子 8 リード線(ゲート) 10 リード線(エミッタ)
DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor element (insulated gate bipolar transistor) 4 Collector terminal 5 Emitter terminal 6 Gate terminal 7 Emitter auxiliary terminal 8 Lead wire (gate) 10 Lead wire (emitter)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板に半導体素子を搭載して主端子, およ
び制御用の補助端子を引出した半導体装置において、補
助端子のリード線の一部を主端子の導体に沿わせて内部
配線し、主端子電流の変化によりリード線に誘起する相
互誘導起電力で制御信号の変化率を低めるように相互誘
導結合させたことを特徴とする半導体装置。
In a semiconductor device having a semiconductor element mounted on a substrate and leading a main terminal and a control auxiliary terminal, a part of a lead wire of the auxiliary terminal is internally wired along a conductor of the main terminal, A semiconductor device characterized in that mutual inductive coupling is performed such that a rate of change of a control signal is reduced by a mutual induced electromotive force induced in a lead wire by a change in a main terminal current.
【請求項2】請求項1記載の半導体装置において、補助
端子のリード線をコイル状に巻回して主端子導体に沿わ
せたことを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein a lead wire of the auxiliary terminal is wound in a coil shape and extends along the main terminal conductor.
【請求項3】請求項1記載の半導体装置において、スイ
ッチングタイムの設定を、主端子導体と補助端子リード
線との間の相互誘導結合度の調整により行うようにした
ことを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the switching time is set by adjusting the mutual inductive coupling between the main terminal conductor and the auxiliary terminal lead. .
JP4191190A 1992-07-20 1992-07-20 Semiconductor device Expired - Fee Related JP2894402B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4191190A JP2894402B2 (en) 1992-07-20 1992-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4191190A JP2894402B2 (en) 1992-07-20 1992-07-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0637222A JPH0637222A (en) 1994-02-10
JP2894402B2 true JP2894402B2 (en) 1999-05-24

Family

ID=16270403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4191190A Expired - Fee Related JP2894402B2 (en) 1992-07-20 1992-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2894402B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6325740B1 (en) 2000-07-14 2001-12-04 Nsk Ltd. Toroidal-type continuously variable transmission
JP3714226B2 (en) 2001-10-19 2005-11-09 日本精工株式会社 Toroidal continuously variable transmission
JP6288769B2 (en) * 2014-05-07 2018-03-07 株式会社日立製作所 Semiconductor power module, power conversion device, and moving body using the same

Also Published As

Publication number Publication date
JPH0637222A (en) 1994-02-10

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