JPS627783B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter that suppresses heat loss when switching elements are turned on, and suppresses voltage generation when switching elements are turned off.

FIG. 1 shows an embodiment of an inverter using transistors. In the figure, 1 is the power supply, 2, 3,
4, 5 are transistors, 6, 7, 8, 9 are diodes, 10, 11, 12, 13 are transistors 2
Base control circuit for driving and controlling ~5, 14,1
5, 16, and 17 are saturable reactors, and 18 is a load. The operation of the inverter itself is well-documented in the literature as a device that creates alternating current from direct current, so a detailed explanation will be omitted, but the purpose of the saturable reactors 14 to 17 will be specifically explained. FIG. 2 shows the state when the transistor is turned on.

In FIG. 2-A, 1 is a power supply, 2 and 5 are transistors, 10 and 13 are base control circuits that control the bases of the transistors, and 18 is a load. Now, when the base control circuits 10 and 13 output signals to turn on the transistors 2 and 5, current begins to flow from the power supply 1 in the path indicated by arrow a. This current increases as the transistors 2 and 5 turn on, and if we view this as a short-time phenomenon, it becomes as shown in Figure 2-B. That is, when the transistor base current rises at to as shown in 1 in Figure 2-B, the voltage between the collector and emitter of the transistor gradually shifts from the power supply voltage Ec to Ov as shown in 2. This is because the collector portion of the transistor cannot completely follow the base current and turns on with a certain time delay.

On the other hand, the collector current increases in response to the power supply voltage even if the voltage between the collector and emitter of the transistor remains. Therefore, the heat loss generated in the transistor during this period is large. If this heat generation becomes excessive, the inside of the transistor may melt and the transistor may lose its function.

As a countermeasure for this, saturable reactors 14 to 17 are inserted as shown in FIG. This acts as a reactor with large inductance in an unsaturated state until the transistor is turned on, suppressing the current and reducing the amount of heat generated. Inserting the saturable reactor in this way suppresses the amount of heat generated when the switch element is turned on, allowing it to work stably.

However, inserting a saturable reactor causes an overvoltage condition in the switching element for the following reasons. That is, a current of I _L is currently flowing in the ON state of the switching element, and if the inductance of the saturable reactor is lsat, the energy possessed by the saturable reactor has the following value.

1/2lsat・I _L ² ...(1) If this energy has no place to go, an excessive voltage may be applied to the transistor and the transistor may be destroyed. For this purpose, there is a method of connecting a capacitor in parallel with the transistor arm as shown in FIG. Items 1 to 18 in the figure are the same as those shown in FIG. 1, so their explanation will be omitted. 19,20
is a capacitor, and for example, when transistor 2 is turned off from an on state, the current path changes as follows. In other words, as shown by the solid line indicated by arrow a in FIG. Then, saturable reactor 1
The energy of No. 4 flows along the path indicated by the dashed-dotted line of arrow b. That is, the path is as follows: power supply 1 → saturable reactor 14 → capacitor 19 → saturable reactor 15 → power supply 1. The energy stored in the saturable reactor 14 is transferred to the capacitor 1 by the capacitor 19.
9 to suppress the voltage surge of the transistor 2.

In the circuit configuration shown in FIG. 3, for example, when PWM control is adopted, when transistor 3 and transistor 5 are on and in the freewheeling mode, that is, load 18 → transistor 5 → saturable reactor 17 → saturable reactor Assume that current is flowing along the path 15→diode 7→load 18.
Here, when an off signal is given to transistor 3 to turn on transistor 2, the charge accumulated in capacitor 19 is transferred to the first path of capacitor 19→transistor 2→transistor 3→capacitor 19, and from capacitor 19→transistor 2. Flows through the second path of → diode 7 → capacitor 19. The first path is a "commutation overlap" in which both transistors 2 and 3 are in the on state, and the current flowing in the second path is due to the reverse recovery charge when the diode 7 recovers from the conductive state to the reverse blocking state. It is something. (Please note that there are many documents regarding the current caused by the reverse recovery charge, so the explanation will be omitted.) In this way, when the transistor 2 is turned on, the current in the capacitor 19 causes the current to flow as explained in FIG. Switching loss occurs. Also,
If there is a "commutation overlap", a switching loss as explained in FIG. 2 occurs when the transistor 3 is off.

The present invention has been made to solve the above-mentioned drawbacks, and provides an inverter that suppresses the generation of heat loss when the switching elements are turned on, and suppresses the generation of voltage when the switching elements are turned off. This will be explained below based on FIG.

In the figure, ~18 is basically the same as each element shown in Figure 3, but saturable reactors 14~
17 as the end terminal format. That is, it is the same as connecting a positive or negative power source and a saturable reactor in series with the switching element, but one terminal is brought out from the middle of the saturable reactors 14 to 17,
A capacitor is connected to this.

In the above configuration, in the "freewheeling mode", that is, when transistors 3 and 5 are in the on state, when transistor 3 is turned off and transistor 2 is turned on,
The current from capacitor 19 flows through saturable reactor 1
Saturable reactor 1 via intermediate terminals 4, 15
4 and 15 are included in the current path, the current is suppressed. Therefore, switching loss of the transistor can be suppressed.

In this case, the energy dissipation of the saturable reactor when transitioning from on to off follows the following progression:

A detailed explanation will be given with reference to FIG. In the figure, 2 is a transistor, 14 is a saturable reactor, and 19 is a capacitor. When the transistor 2 is in the on state, the current flows along the solid line path indicated by the arrow a, and the saturable reactor 14 has the energy shown by the above equation (1). This energy is divided into energy stored in the iron core of the saturable reactor and energy stored in the air-core inductance of the winding. The energy stored in the iron core is transferred to the capacitor 19 through the intermediate terminal of the saturable reactor 14 by transformer action. Furthermore, the energy possessed by the air-core inductance is very small compared to the energy stored in the iron core and does not pose a problem.

Therefore, when the transistor 2 is turned off, the energy of the core stored in the saturable reactor 14 and the power supply of the air core inductance and the capacitor 19 are
The energy stored in the coil connected to is transferred to the capacitor 19 along the path indicated by arrow b. As a result, the voltage of the transistor 2 does not increase due to the saturable reactor 14.

Further, when ON, the capacitor current is suppressed by the portion of the saturable reactor between the capacitor 19 and the transistor 2, so that the original purpose is not lost.

In terms of the actual device configuration, if the distance between the saturable reactor and the transistor is shortened,
The distance between other parts is absorbed by the capacitor shown in FIG. 4 and does not become a problem.

Furthermore, although the present invention has been described using transistors, it is of course applicable to inverter circuits using GTCs, thyristors, and the like.

According to this invention, the first and second switching arms are connected in series, the first switching arm is connected to the positive side of the power supply via the first saturable reactor, and the second switching arm is connected to the positive side of the power supply via the first saturable reactor. 2nd arm
By connecting a capacitor with a predetermined capacitance between the intermediate taps of each saturable reactor to the negative pole side of the power supply through a saturable reactor, heat loss when the switching element is turned on can be reduced. to prevent voltage generation when turning off.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional inverter, Figure 2 -
Figure A is an explanatory diagram of the circulating mode of the inverter circuit.
3 is an explanatory diagram of an inverter circuit, FIG. 4 is a circuit diagram showing an embodiment of the invention, and FIG. 5 is a partial explanatory diagram of FIG. 4. In the figure, 1 is a power supply, 2, 3, 8, and 9 are switching arms, 14 and 16 are first saturable reactors, 15 and 17 are second saturable reactors, and 18 and 19 are capacitors. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A first and a second switching arm are connected in series, and the first switching arm is connected to the positive side of a power supply via a first saturable reactor,
An inverter characterized in that the second switching arm is connected to the negative electrode side of the power source via a second saturable reactor, and a capacitor having a predetermined capacity is connected between the intermediate taps of the saturable reactor. .