JPS6395733A - Snubber circuit for gto thyristor - Google Patents

Abstract

PURPOSE:To reduce a turn-on switching loss by connecting a saturable reactor in series with a resistor connected in parallel with a rectifier diode to discharge the charging voltage of a snubber capacitor so as to suppress the leading of a discharge current from the snubber capacitor when a GTO thyristor is turned on. CONSTITUTION:The saturable reactor 5 is inserted in series with a snubber resistor 4. In order to discharge the charging voltage of the snubber capacitor 3, the saturable reactor 5 is connected in series with the resistor 4 connected in parallel with a rectifier diode 2 to suppress the leading of the discharge current from the snubber capacitor 3 when the GTO thyristor is turned on. Thus, the discharge current from the snubber 3 is retarded by the period when the saturable reactor 5 is saturated to reduce the di/dt stress exerted onto the GTO thyristor 1, thereby reducing the turn-on switching loss.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a snubber circuit of a GTO (Gate Turn 0ff) thyristor, and particularly to suppressing the rise rate of current discharged from the snubber circuit when the GTO thyristor is turned on. The present invention relates to a GTO thyristor snubber circuit that can reduce switching loss when the GTO thyristor is turned on.

[Conventional technology]

An example of a conventional snubber circuit for a GTO thyristor is shown in FIG. 3. FIG. 3 shows an example of a circuit generally used as a snubber circuit for a 0-0 thyristor.

In the figure, 1 is a GTO thyristor, which is a circuit in which a series connection body of a rectifier diode 2 and a snubber capacitor 3 is connected in parallel with the GTO thyristor 1, and a snubber resistor 4 is connected in parallel with the rectifier diode 2. be.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG. 4.

Figure 4 is a time chart for explaining the operation of Figure 3.
It is expressed with time t plotted on the horizontal axis. In the figure, (a) shows the voltage waveform of the GTO thyristor 1, (b) shows the discharge current of the snubber capacitor 3, and (e
) shows the current waveform of the GTO thyristor 1.

First, the operation when the GTO thyristor 1 shifts from the on state to the off state is as follows.

That is, GTO thyristor 1 starts turning off,
When the current flowing until now begins to decrease, the rectifier diode 2 becomes conductive and the snubber capacitor 3 begins to be charged. Then, when the on-current of the GTO thyristor 1 is completely cut off, all the current that has been flowing through the GTO thyristor 1 flows through the rectifier diode 2 and the snubber capacitor 3. This current starts to attenuate from the time when the charging voltage of the snubber capacitor 3 is charged to a value equal to the circuit voltage, and the current is cut off when the energy accumulated in the circuit wiring is absorbed. Subsequently, this overcharge voltage is discharged through the power supply circuit until it reaches a voltage equal to the power supply voltage, and the turn-off is completed when the constant voltage Vc (the charging voltage of the snubber capacitor 3) is reached.

When GTO thyristor 1 is turned on in this state,
Load current flows through GTO thyristor 1 and 1 snubber capacitor at the same time? A charging voltage of 3 flows to the GTO thyristor 1 through the snubber resistor 4.

Discharge current of snubber capacitor 3 at this time 1. If the charging voltage of the snubber capacitor 3 is VCs, its value is C8%, and the value of the snubber resistor 4 is R, then the peak current X is 15=vC/R6 (Fig. 4(b)) reference).

Further, the rise rate di/dt of this current is limited only by the wiring inductance of the snubber, and has an extremely high value.

For example, if VC = 1250V, Rs = 5Ω, snubber wiring inductance L, = 0.5μH, l5 = 125015-25OA, ”/g =
125010.5=250OA/μS, an extremely high d1/dt stress was applied, which caused an increase in turn-on switching loss. Here, if the value Rs of the snubber resistor 4 is increased, the peak current KXsO value can be suppressed to a small value, but since the value of the charging voltage value Cs is relatively large, the discharge time constant C,,US Since it becomes long, there is a limit to how small it can be made. Here, if the discharge time constant CBRs is long, the minimum turn-on time of the GTO thyristor 1 is limited, so
It is desirable that it be as short as possible. Also, if the value of the wiring inductance LB of the snubber is increased, K 1) djl
Although it is possible to suppress the dt value, the actual situation is that if the wiring is made long, it may cause malfunctions and vibrations, so it is impossible to increase the value. FIG. 4 is a diagram for explaining this turn-on operation.

[Problem that the invention seeks to solve]

In the conventional GTO thyristor snubber circuit as described above, the rise rate of the current discharged from the snubber circuit when the GTO thyristor is turned on is limited only by the wiring inductance of the snubber, and cannot be extremely high, resulting in turn-on switching. There was a problem in that it increased losses.

This invention was made to solve this problem, and suppresses the discharge current from the snubber capacitor and
It is an object of the present invention to provide a snubber circuit for a GTO thyristor that can reduce di/dt stress during turn-on of an O thyristor and reduce turn-on switching loss.

[Means for solving problems]

The snubber circuit of the GTO thyristor according to this invention is
A series connection body of a rectifier diode and a snubber capacitor is connected in parallel with the O thyristor, and a saturable reactor is connected in series with a resistor connected in parallel with the rectifier diode in order to discharge the charging voltage of the snubber capacitor.
The rise of the discharge current from the snubber capacitor is suppressed when the GTO thyristor is turned on.

[Effect]

In this invention, the discharge current from the snubber capacitor is delayed by the period until the saturable reactor is saturated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a snubber circuit for a GTO thyristor according to the present invention.

In FIG. 1, the same reference numerals as in FIG. 3 indicate corresponding parts, and 5 is a saturable reactor connected in series with a snubber resistor 4 connected in parallel with the rectifier diode 2. Thus, the basic configuration of the embodiment shown in FIG. 1 is similar to the conventional snubber circuit shown in FIG. 3, except that a saturable reactor 5 is inserted in series with the snubber resistor 4.

In order to discharge the charging voltage of the snubber capacitor 3, a saturable reactor is connected in series with a resistor connected in parallel with the rectifier diode to suppress the rise of the discharge current of the snubber capacitor when the GTO thyristor is turned on. It is configured as follows.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

Figure 2 is a time chart used to explain the operation of Figure 1.
It is expressed with time t plotted on the horizontal axis. In the figure, (&) shows the voltage waveform of the GTO thyristor 1, and (b) shows the discharge current of the snubber capacitor 3, (
C) shows the voltage of the saturable reactor 5, and (d) shows the current waveform of the GTO thyristor 1.

First, since the turn-off operation is the same as that of the conventional circuit shown in FIG. 3, the explanation thereof will be omitted, and since the turn-on operation is different, only the turn-on operation will be explained.

FIG. 2 is a diagram for explaining this turn-on operation.

.

Next, when the GTO thyristor 1 is turned on, a load current flows through the GTO thyristor 1, but at the same time, the charge in the snubber capacitor 3 attempts to be discharged through the snubber resistor 4 and the saturable reactor 5. At this time,
Since the saturable reactor 5 is still in an unsaturated state, its inductance is extremely large, and the current rise rate dl/dt is determined by Lsat being the unsaturated inductance of the saturable reactor 5 and Va being the charging voltage of the snubber capacitor 3.
Then, ``/at = ve/x, aaA.Next, when the saturable reactor 5 is saturated, this inductance becomes almost zero (0), so the charge in the snubber capacitor 3 is discharged through the snubber resistor 4. This electric current i1g changes the value of the snubber capacitor 3 to c5.
When the value of the snubber resistor 4 is RB, it becomes as follows.

That is, compared to the conventional circuit shown in FIG. 3, the discharge current from the snubber capacitor 3 can be delayed by the period until the saturable reactor 5 is saturated, and the di/dt stress applied to the GTO thyristor 1 can be reduced. The turn-on switching loss can be reduced.

The delay time td (see Fig. 2(e)) due to the saturable reactor 5 can be adjusted by the material of the saturable reactor, and the magnetic flux density of the material can be adjusted to Bm (gllull
) When the y cross-sectional area is Sm', tawBmxs/v
0(sa:).

Above, we have explained the application to GTO thyristor.
Of course, it is possible to apply the present invention to transistors and thyristors using similar circuits.

〔Effect of the invention〕

As explained above, according to the present invention, the rise of the discharge current from the snubber capacitor is suppressed when the GTO thyristor is turned on. The practical effects are extremely large because the discharge current from the capacitor can be delayed, the dl/dt stress applied to the GTO thyristor can be reduced, and the turn-on switching loss can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the snubber circuit of the GTO thyristor according to the present invention, Fig. 2 is a time chart for explaining the operation of Fig. 1, and Fig. 3 is an example of the snubber circuit of the conventional GTO thyristor. The circuit diagram shown in FIG. 4 is a time chart for explaining the operation of FIG. 3. 1, ψ, ΦGTO thyristor, 2, rectifier diode, 3, snubber capacitor, 4, snubber resistor (resistor), 5, saturable reactor.

Claims (1)

[Claims] In a snubber circuit formed by connecting a series connection body of a rectifier diode and a snubber capacitor in parallel with a GTO thyristor, a saturable reactor is connected in series with a resistor connected in parallel with the rectifier diode in order to discharge the charging voltage of the snubber capacitor. A snubber circuit for a GTO thyristor, characterized in that the snubber circuit is connected to suppress a rise in discharge current from the snubber capacitor when the GTO thyristor is turned on.