JPS5979630A - 論理回路 - Google Patents

論理回路

Info

Publication number
JPS5979630A
JPS5979630A JP57189006A JP18900682A JPS5979630A JP S5979630 A JPS5979630 A JP S5979630A JP 57189006 A JP57189006 A JP 57189006A JP 18900682 A JP18900682 A JP 18900682A JP S5979630 A JPS5979630 A JP S5979630A
Authority
JP
Japan
Prior art keywords
circuit
input
signal
clock
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57189006A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0256852B2 (Direct
Inventor
Kazutaka Mori
和孝 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57189006A priority Critical patent/JPS5979630A/ja
Publication of JPS5979630A publication Critical patent/JPS5979630A/ja
Publication of JPH0256852B2 publication Critical patent/JPH0256852B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Logic Circuits (AREA)
JP57189006A 1982-10-29 1982-10-29 論理回路 Granted JPS5979630A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57189006A JPS5979630A (ja) 1982-10-29 1982-10-29 論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57189006A JPS5979630A (ja) 1982-10-29 1982-10-29 論理回路

Publications (2)

Publication Number Publication Date
JPS5979630A true JPS5979630A (ja) 1984-05-08
JPH0256852B2 JPH0256852B2 (Direct) 1990-12-03

Family

ID=16233717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57189006A Granted JPS5979630A (ja) 1982-10-29 1982-10-29 論理回路

Country Status (1)

Country Link
JP (1) JPS5979630A (Direct)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0800719A4 (en) * 1994-12-30 1999-12-22 Intel Corp PULSE FLIPFLOP

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0800719A4 (en) * 1994-12-30 1999-12-22 Intel Corp PULSE FLIPFLOP

Also Published As

Publication number Publication date
JPH0256852B2 (Direct) 1990-12-03

Similar Documents

Publication Publication Date Title
US5036221A (en) Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal
US20040246810A1 (en) Apparatus and method for reducing power consumption by a data synchronizer
US5128970A (en) Non-return to zero synchronizer
US5025414A (en) Serial bus interface capable of transferring data in different formats
US4975593A (en) Microcomputer with synchronized data transfer
US4409671A (en) Data processor having single clock pin
US5522048A (en) Low-power area-efficient and robust asynchronous-to-synchronous interface
CN103873031A (zh) 非时钟触发寄存器
US6584536B1 (en) Bus transaction accelerator for multi-clock systems
KR940003611B1 (ko) 클럭 및 제어 신호 발생 회로
JPS5979630A (ja) 論理回路
US4547684A (en) Clock generator
JPS6248846B2 (Direct)
JPH0636054A (ja) ワンチップマイクロコンピュータ
JPH06196997A (ja) データ出力装置とその方法および記憶装置
KR950008661B1 (ko) 버스 다중화 회로
US6255869B1 (en) Method and apparatus for system resource negotiation
US5097158A (en) Digital noise feedthrough reducer and synchronizer for mixed-signal integrated circuit
CN118535515B (zh) 一种usb通信方法及装置
JP2701544B2 (ja) シフトクロック生成回路
KR960011280B1 (ko) 캐쉬메모리 억세스 타임조정회로
KR900005452B1 (ko) 마이크로 프로세서의 데이터 처리속도를 개선한 회로
US7296176B1 (en) Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle
JPH03276218A (ja) 電子回路制御装置
KR950014374B1 (ko) 원-칩 콘트롤러를 채용한 장치를 위한 직접 메모리 액세스(dma) 인식신호 발생회로