JPS5957346A - Data processor - Google Patents

Abstract

PURPOSE:To improve the versalility and the flexibility, by constituting that a microprogram field value of two microprogram processing sections are switched so as to provide excellent processing ability with a simple hardware. CONSTITUTION:The 1st microprogram field value is stored in a register 21 and the 2nd microprogram field value is stored in a register 22. Bits 32-63 of the register 21 and the register 22 are connected to a microprogram switching section 23, and an output of the switching section 23 is inputted to a decoder section 24. The switching section 23 selects an output of the register 21 based on the indication of a selecting signal gate 25 when the switching designation bit is ''1''. When the designation bit is ''0'', the output of the register 22 is selected. The versatility and the flexibility of the device is improved by switching the microprogram field values in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having two microprogram processing units 1111. In a system composed of processing units, each microprogram field operates independently even though each unit interacts with the other.In other words, each unit has an independent control memory unit, and reads data from it. Microprogram control has been performed using stored control information.Furthermore, not all steps in each routine 1 of a microprogram are necessarily different from routine to routine, but there is a tendency for slight differences to result in different routines. These problems can sometimes be dealt with by changing the subroutine ratio, but due to the advantage of data processing equipment where each step is related to throughput, subroutines that are not necessarily optimal for throughput,
In other words, a method that takes extra time when connecting from one routine to another has disadvantages.

On the other hand, from the hardware perspective, the capacity of control storage information hj
This was determined physically at the time of design, and subsequent changes in size and history were difficult, and there was no flexibility or flexibility.

<Object of the Invention> The present invention focuses on these points and provides a data processing device equipped with a microprogram processing section that has the same throughput and expandability on one simple node.

<Invention (ready-made)> According to the present invention, in a data processing device composed of two microprogram processing units, a part of the microprogram field of the first microprogram processing unit and a part of the microprogram field of the second microprogram processing unit are The microprogram field value of the Jll! section is configured to be switchable, and the first/second microprogram field is switched and selected by specifying the switching specification field value in the microprogram field of the first microprogram processing section. Use the microprogram field value of 2.

<Example> Next, this invention will be explained in detail using an example. 1. FIG. 1 shows an example of this invention. . . . 2 shows the field system of the microprogram field of the microprogram processing section. In FIG. 1, the M1 microprogram field 11 consists of 64 bits, bit 31 is a switching designation bit, and bits 32 to 630
The 32 bits correspond to the 32 bits of the second microprogram field 12, and the designation of the switching designation bit of bit 31 (either "O" or °°1" can be determined by the hardware configuration. In this case, when it is 61" This field system replaces the second microprogram field value 12 by selecting the first microprogram field value. Bit 31 is °'O''', ``1''
', bits 32 to 63 are used for the operation of the first microprogram processing section, and the second microprogram processing section performs the operations corresponding to the designation of the second microprogram field value 12. This will be further explained below using the hardware configuration example shown in FIG. In FIG. 1, a first microprogram field value 11 is stored in register 21, and a second microprogram field value 12, also in FIG.

Bits 32-63 of register 21 and register 22
is connected to a microprogram field switching unit (consisting of a 1/2 multiplexer) 23, and the output of the field switching unit 23 is input to a decoder unit 24.
Bit 31 of register 21 is run over by selection signal gate 25 to microprogram field switching unit 23.

As mentioned earlier, in this embodiment, when the switching designation bit in bit 31 of the first microprogram field 11 is "1", the output of the first microprogram field register 21 is switched to the microprogram field switching unit 23. Long selection.

The output of the number gate 25 is also selected as the output instruction. .

On the other hand, when the handwriting switching designation bit is "0''', the negation (inversion) side output of the selection signal gate 25 is turned on, so that the output of the second microprogram field register 22 is selected by the switching unit 23. Micro program field entry, 1 change section 23 (1/2
The effective microprogram field value selected by the multiplexer is used as various decoder circuits 24 and other control information to execute the operation of the second microprogram processing section.1, then refer to the microprogram flow diagram in FIG. and explain it functionally. This shows the microprogram flow of the second microprogram processing section, and shows the three routines A, H, 'C, and step 1σ! It is expressed in 1rl1 work. B routine (
(represented by a solid line) does not indicate in this flow that there is no intervention from the 1' microprogram field3, on the other hand,
Routines A and C show cases where there is some intervention of the first microprogram field. 13 routine k
l. Steps B-1, B-2, from start to end.
B-3, B-4, B-5, B-6°B-7, H-8 and the end. On the other hand, the A and C routines also use the same steps as the B routine, but some of the steps are modified to create d+I+. Routine A executes the steps indicated by dotted lines in steps B-1 and B.
-2, and then steps A-3, A-4, and A-5 from the first microprogram field. As described above, the switching designation bit 31 is set to "1'' at these steps A-3, A-4, and A-5. Next, Steps B-6 and B-7 execute the second microprogram field value, and finally Step A-8 executes the first microprogram field value. Same as step B-1, B-2.

1, steps C-3, C-4, which indicate that they are executed as C-3, C-4, B-5, B-6, C-7, and C-8.
, C-5, C-7, C-8+2, the designation bit becomes It I II, and the field value of the first microproger is used.

Effect> As described above, the second microprogram processing section does not have all the steps for routines 1-7 for A and C routines, and executes the B routine according to instructions from the first microprogram processing section. This allows it to be created as a standalone routine while using .

If the steps used in common 111 are converted into a subroutine and executed in the second microprogram processing section itself, the flow will still work, but the step for connecting to each routine will be required, and the throughput will need to be executed. This is disadvantageous in a data processing device that requires a lot of data processing, and also makes it possible to suddenly change the second microprogram routine by using the first microprogram field to modify the first microprogram. 3) This also means that it provides flexibility and 1/L flexibility for the device.

[Brief explanation of drawings]

Is diagram 1q-1 used in this invention? i'J 11th 2nd
FIG. 2 is a block diagram showing an example of the essential parts of the data processing apparatus according to the present invention, and FIG. 3 is a flowchart showing an example of the operation of the microprogram. it: w: 1 microprogram field,
12: 2 micro program field, 21:
1st microprogram register, 22: 2nd microprogram register, 23: Microprogram field cutout section, 24: Decoder section, 25: Selection signal gate. Patent applicant: NEC Corporation

Claims (1)

[Claims] (1) In a data processing device equipped with two microprogram processing sections, a part of the microprogram field (hereinafter referred to as 21) 1 microprogram field of the first microprogram processing section is provided with a second microprogram processing section. microprogram field (
(hereinafter referred to as a second microprogram field), and a switching designation field that designates switching between the second microprogram field and the corresponding first microprogram field, and a circuit that decodes the contents of the switching designation field. , the first microprogram field (
++↓ and a microprogram field switching unit that switches and selects the second microprogram field value and creates an effective microprogram field value,
As the effective microprogram field value used in the second microprogram processing section, either the d31 microprogram field or the second microfield is selected by the microprogram field switching section according to the specification of the switching specification field of the first microprogram processing section. A data processing device that attempts to perform Ill″f1°.