JPS6376020A - Virtual computer system - Google Patents

Virtual computer system

Info

Publication number
JPS6376020A
JPS6376020A JP22237486A JP22237486A JPS6376020A JP S6376020 A JPS6376020 A JP S6376020A JP 22237486 A JP22237486 A JP 22237486A JP 22237486 A JP22237486 A JP 22237486A JP S6376020 A JPS6376020 A JP S6376020A
Authority
JP
Japan
Prior art keywords
information
computer
data
register
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22237486A
Other languages
Japanese (ja)
Inventor
Kazuhiro Iio
飯尾 和弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22237486A priority Critical patent/JPS6376020A/en
Publication of JPS6376020A publication Critical patent/JPS6376020A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To improve the processing speed of a computer by adding the specifying information of a computer to be selected to input information and constituting and driving the computer based on the information. CONSTITUTION:Inputted information is separated into computer specifying information and instruction data information by an information separating circuit 5 and the separated data are respectively stored in a storage circuit 6 and a main storage circuit 7. Respective information is transmitted to specifying registers 10, 11, an instruction register 12 and a data register 13 respectively through buffer memories 8, 9. Specifying decoders 14, 15, 21, 22 select control circuits 16-19 and data processing circuits 23-26 specified by the information to constitute a specific computer. On the other hand, control signals are sent to the specified data processing circuits 23-26 together with prescribed data information outputted from the data register 13 to execute prescribed processing and to obtain the specified computer function. Consequently, much computing processing can be rapidly attained.

Description

【発明の詳細な説明】 〔4!E費〕 本発明は、仮想計算機システムを作動させるときに必要
であった計算機の選択、指定操作の煩わしさを解消する
ため、入力情報に1選択すべき計算機の指定情報を付加
し、その情報に基づいて計算機を構成、作動できるよう
にするものである。
[Detailed description of the invention] [4! E cost] In order to eliminate the troublesome operation of selecting and specifying a computer that was necessary when operating a virtual computer system, the present invention adds specifying information of the computer to be selected to the input information, and stores that information. It enables computers to be configured and operated based on the .

〔産業上の利用分野〕[Industrial application field]

本発明は、一台の電子計算機で多数モードの計算処理が
可使な仮想計算機システムに関する。
The present invention relates to a virtual computer system in which a single electronic computer can perform calculation processing in multiple modes.

〔従来の技術〕[Conventional technology]

電子−計算機において種々の計算処理を実行するには、
各々特有な形のハード構成が必要であるが1種々の計算
処理に対応できるハード構成を備えた電子計算機におい
て、ある特定の計算処理モードから他の計算処理モード
に移る場合、従来は、手動操作によってモード設定を切
換える必要があった。
To perform various calculation processes on an electronic computer,
Each type of computer requires a unique hardware configuration, but in electronic computers equipped with hardware configurations that can handle various types of calculation processing, when moving from one specific calculation processing mode to another, conventionally manual operation was required. It was necessary to change the mode setting depending on the situation.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、新たな計算処理を実行する場合に、その都度
、手動操作によってモード設定を切換え、計算機の系を
構成しなおすというのは煩わしい、特に、計算機の処理
速度が向ヒした今【1では、その煩わしさは一層増大し
た。
By the way, it is troublesome to manually switch the mode settings and reconfigure the computer system every time you want to perform a new calculation process, especially now that the processing speed of computers has increased. The annoyance grew even more.

そこで、本発明の目的は計算処理モードの切換えの煩わ
しさを解消し、より迅速に多数の計算処理を可撤とする
点にある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the troublesome switching of calculation processing modes and to more quickly perform a large number of calculation processes.

〔問題点を解決するための手段〕[Means for solving problems]

前記従来技術の問題点を解決するとともにその目的を達
成した本発明に係る仮想計算機システムは、第1図に示
すように入力情報に含まれる計算機指定情報と命令・デ
ータ情報とを分離する情報分子a′f一段1と、分離し
た計算機指定情報を主記憶手段3に格納した命令φデー
タ情報と対応させつつ格納する計算機指定情報格納手段
2とを備え計算機指定情報により指定された計算機を構
成する。
A virtual computer system according to the present invention that solves the problems of the prior art and achieves its purpose uses an information molecule that separates computer specification information and instruction/data information contained in input information, as shown in FIG. a'f one stage 1 and computer specification information storage means 2 for storing the separated computer specification information in correspondence with the instruction φ data information stored in the main storage means 3, and constitutes a computer specified by the computer specification information. .

〔作用〕[Effect]

本発明によれば、情報分離手段lで抽出された計算機指
定情報は、命令・データ情報と対応づけされて計算機指
定情報格納手段2に格納される。
According to the present invention, the computer designation information extracted by the information separation means 1 is stored in the computer designation information storage means 2 in association with instruction/data information.

そして、当該格納手段2に格納された計算機指定情報に
基づき、新たな計算機の系が構成され、そこに主記憶手
段3から命令−データ情報が送られて、所定の計算処理
が実行される。
Then, based on the computer designation information stored in the storage means 2, a new computer system is constructed, and command-data information is sent there from the main storage means 3 to execute a predetermined calculation process.

〔実施例〕〔Example〕

第2図は、本発明に係る仮想計算機システムの実施例を
示す図である。同図において、5は入力情報を計算機の
指定情報と命令・データ情報とに分離する情報分離回路
、6は計算機の指定情報を格納する格納回路、7は命令
・データ情報を格納する主記憶回路、8,9はそれぞれ
計算機指定情報、命令ψデータ情報を後段へ送出するバ
ッファメモリ、10.11はバッファメモリ8から入力
した計算機指定情報を一時的に記憶する指定レジスタ、
12はバッファメモリ9から入力した命令情報を一時的
に蓄える命令レジスタ、13はバッファメモリ9から入
力したデータ情報を一時的に蓄えるデータレジスタ、1
4.15は指定レジスタ10から送られた情報を解読し
て制御回路16〜19の中から該当する回路を抽出する
指定デコーダ、20は命令レジスタ12から送られた命
令情報を解読して指定デコーダ14又は15抽出された
制御回路に送出するデコーダ、21゜22は指定レジス
タ11から送られた指定情報を解読してデータ処理回路
23〜26の中から該当する回路を抽出する指定デコー
ダ、27は抽出されたデータ処理回路において演算処理
された結果を一時的に記憶しておくレジスタ、28は当
該レジスタ27に記憶されている処理結果と計算機指定
情報とを対応づけるための識別レジスタである。
FIG. 2 is a diagram showing an embodiment of a virtual computer system according to the present invention. In the figure, 5 is an information separation circuit that separates input information into computer specification information and instruction/data information, 6 is a storage circuit that stores computer specification information, and 7 is a main memory circuit that stores instruction/data information. , 8 and 9 are buffer memories that respectively send computer specification information and instruction ψ data information to subsequent stages; 10.11 is a specification register that temporarily stores computer specification information input from the buffer memory 8;
12 is an instruction register that temporarily stores instruction information input from the buffer memory 9; 13 is a data register that temporarily stores data information input from the buffer memory 9;
4.15 is a designated decoder that decodes the information sent from the designated register 10 and extracts a corresponding circuit from among the control circuits 16 to 19; 20 is a designated decoder that decodes the instruction information sent from the instruction register 12; 14 or 15 is a decoder that sends the data to the extracted control circuit; 21 and 22 are designation decoders that decode the designation information sent from the designation register 11 and extract the corresponding circuit from among the data processing circuits 23 to 26; A register 28 that temporarily stores the result of arithmetic processing in the extracted data processing circuit is an identification register for associating the processing result stored in the register 27 with computer designation information.

次に作動を説明する。入力された情報は、情報分離回路
5にて計算機指定情報と命令・データ情報とに分離され
、それぞれ格納回路6.主記憶回路7に格納される0次
に、それぞれの情報はバッファメモリ8.9を通って指
定レジスタ10゜11および命令レジスタ12.データ
レジスタ13に送られる0次に、指定レジスタ10.1
1に蓄えられた情報に基づき、指定デコーダ14゜15
および21.22が当該情報にて指定されている制御回
路16〜19およびデータ処理回路23〜26を選択し
、特定して特定通りの計算機を構成する。そして特定さ
れた。制御回路に対して命令レジスタ12から命令情報
が送られ、当該回路からデータ処理回路23〜26へ制
御信号が送出される。一方、特定されたデータ処理回路
にはデータレジスタ13から所定のデータ情報とともに
制御信号が送られてくるので、当該データ処理回路が所
定の処理を行なって指定通りの計算機機能を実現し、そ
の結果をレジスタ27に蓄える。蓄えられた処理結果は
、識別レジスタ28内の計算機指定情報によって特定さ
れ、バッファメモリに送られてその処理結果が外部に出
力される。これによって、一台の計算機で任意の多数の
処理モードが実現できることになる。
Next, the operation will be explained. The input information is separated into computer specification information and instruction/data information by an information separation circuit 5, and each is sent to a storage circuit 6. Each piece of information stored in the main memory circuit 7 passes through a buffer memory 8.9 to a designated register 10.11 and an instruction register 12.9. 0th order sent to data register 13, designated register 10.1
Based on the information stored in 1, the designated decoder 14°15
and 21.22 selects and specifies the control circuits 16 to 19 and data processing circuits 23 to 26 specified by the information to configure the specified computer. and was identified. Command information is sent from the command register 12 to the control circuit, and control signals are sent from the circuit to the data processing circuits 23-26. On the other hand, since a control signal is sent from the data register 13 to the specified data processing circuit along with predetermined data information, the data processing circuit performs the predetermined processing to realize the specified computer function, and as a result, is stored in the register 27. The stored processing results are specified by the computer designation information in the identification register 28, sent to the buffer memory, and the processing results are output to the outside. This allows a single computer to implement any number of processing modes.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明に係る仮想計算機システムに
よれば、入力情報に含まれる計算機指定情報を分離して
、主記憶手段に格納した命令・データ情報と対応させて
格納する手段を設けたから、種々の計算処理モードを実
行するに際し、計算機本体内部で自動的にモードの選択
、切換えを行なうことができる。従って、モード切換え
の煩わしさを解消できるとともに、連続的な計算処理が
可能となって仮想計算機の処理悌率を向上することがで
きる。
As explained above, according to the virtual computer system according to the present invention, there is provided a means for separating the computer specification information included in the input information and storing it in correspondence with the instruction/data information stored in the main storage means. When executing various calculation processing modes, mode selection and switching can be performed automatically within the computer main body. Therefore, the troublesomeness of mode switching can be eliminated, and continuous calculation processing can be performed, thereby improving the processing rate of the virtual machine.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の基本的構成を示すクレーム対応図、第
2図は本発明に係る仮想計算機システムの一実施例を示
すブロック図である。 5・・・情報分離回路 6・・・格納回路(計算機指定情報格納手段)7・・・
主記憶回路 16〜19・・・制御回路
FIG. 1 is a claim correspondence diagram showing the basic configuration of the present invention, and FIG. 2 is a block diagram showing an embodiment of a virtual computer system according to the present invention. 5... Information separation circuit 6... Storage circuit (computer specified information storage means) 7...
Main memory circuits 16 to 19...control circuit

Claims (1)

【特許請求の範囲】[Claims] 入力情報に含まれる計算機指定情報と命令・データ情報
とを分離する情報分離手段と、分離した計算機指定情報
を主記憶手段に格納した命令・データ情報と対応させつ
つ格納する計算機指定情報格納手段とを備え計算機指定
情報により指定された計算機を構成することを特徴とす
る仮想計算機システム。
Information separation means for separating computer specification information and instruction/data information included in the input information; and computer specification information storage means for storing the separated computer specification information in correspondence with the instruction/data information stored in the main storage means. A virtual computer system comprising: a computer specified by computer specification information.
JP22237486A 1986-09-19 1986-09-19 Virtual computer system Pending JPS6376020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22237486A JPS6376020A (en) 1986-09-19 1986-09-19 Virtual computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22237486A JPS6376020A (en) 1986-09-19 1986-09-19 Virtual computer system

Publications (1)

Publication Number Publication Date
JPS6376020A true JPS6376020A (en) 1988-04-06

Family

ID=16781351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22237486A Pending JPS6376020A (en) 1986-09-19 1986-09-19 Virtual computer system

Country Status (1)

Country Link
JP (1) JPS6376020A (en)

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