JPS62150431A - Rounding designation system - Google Patents

Rounding designation system

Info

Publication number
JPS62150431A
JPS62150431A JP60291140A JP29114085A JPS62150431A JP S62150431 A JPS62150431 A JP S62150431A JP 60291140 A JP60291140 A JP 60291140A JP 29114085 A JP29114085 A JP 29114085A JP S62150431 A JPS62150431 A JP S62150431A
Authority
JP
Japan
Prior art keywords
rounding
instruction
bit
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60291140A
Other languages
Japanese (ja)
Other versions
JPH0625965B2 (en
Inventor
Misayo Sasahara
笹原 美小夜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60291140A priority Critical patent/JPH0625965B2/en
Publication of JPS62150431A publication Critical patent/JPS62150431A/en
Publication of JPH0625965B2 publication Critical patent/JPH0625965B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent overhead by selecting any of the 1st designation means designating the kind of rounding and the 2nd designation means designating the kind of rounding through the identification of a prescribed instruction specifically so as to execute the rounding. CONSTITUTION:Each bit of a 4-bit FF 1 set by a write instruction or the like of a CPU corresponds to a round mode, only one bit in the 4-bit is set to have a logical 1 and its value is outputted to a rounding execution circuit 6 according to a priority circuit 5 when the value of a 1-bit FF 4 is 0. Further, when the value of the FF 4 is logical 1, the special instruction is decoded by the instruction decoder 2 and when a line corresponding to signal lines inputted to a PLA 3 is logical 1, the programmed output line is brought into logical 1 and its output is inputted from the PLA 3 to the circuit 6 according to the circuit 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、数値演算を実行するシステムに於ける型変換
及び異なるデータタイプとの演算時に生ずる丸めの制御
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to type conversion in a system that performs numerical operations and control of rounding that occurs when operating with different data types.

〔従来の技術〕[Conventional technology]

数値演9.に於る丸めの種類としては1例えばIEEE
では4柚類の丸めモード(toward 十as。
Numerical performance 9. The types of rounding are 1, for example, IEEE
Now, the rounding mode of the 4 citrons (toward 10 as).

toward −as、 toward Q、 nea
rest )が規定されている。従来の数値演舞−シス
テムに於てはこれら4?11の丸めの一つを指示するこ
とによシ演数のNI類に拘らず一神類の丸めを実行する
形式となっていた。例えば文献(1)によると、丸めの
種類は、コントロール・ワードのRC(Round −
Control)フィールドによって選択できる様にな
っており、ユーザーがいずれかを指定すると。
toward -as, toward Q, nea
rest ) is defined. In the conventional numerical performance system, by instructing one of these 4 to 11 rounding types, rounding of one type is executed regardless of the NI class of the number. For example, according to literature (1), the type of rounding is RC (Round -
Control) field allows selection, and when the user specifies one of them.

指定を変更しない限夛その一棹ル1の丸めがあらゆる演
算に対し適用、実行される。
As long as you do not change the specification, rounding to 1 will be applied to all operations.

文−:(1)  r IAPX 86フアミリ・ユーザ
ーズマユユアル」第3章 インテルジャパン(1981) 〔発明が触決しようとする問題点〕 上述し7た従来の丸め指定方式は一寸丸めの種類を指定
すると、一種類のみが、丸めが実行されない。このため
C、FORTRAN言飴等の様に言語入文の実行による
。自動型変換とそれに伴う丸めがしばしば行なわれ、し
かも、型変換のタイプと対応する丸め方式が何種類かあ
る様な場合には、指定が−Pk類のみであると異った型
変換が生じる毎に丸めのWtmを、指定し直さなければ
ならずオーバーヘッドが生じるという欠点がある。
Sentence: (1) r IAPX 86 Family User's Manual Chapter 3 Intel Japan (1981) [Issues to be resolved by the invention] The above-mentioned 7 conventional rounding specification methods specify the type of one-inch rounding. Then, only one kind of rounding is not performed. For this reason, it is necessary to execute language input such as C, FORTRAN language, etc. In cases where automatic type conversion and associated rounding are often performed, and where there are several types of rounding methods that correspond to the type of type conversion, different type conversions will occur if only the -Pk class is specified. There is a drawback that the rounding Wtm must be respecified each time, resulting in overhead.

たとえば、C言語での型変換をM3図のプログラム例と
演算結果を用いて説明することにする。
For example, type conversion in C language will be explained using a program example shown in the M3 diagram and calculation results.

グログラム例の1ine  10.17,24.31は
実数から整数への型変換、1ine 11. 18.2
5゜32は実数の倍精度から単精度への型変換、演算結
果の1ine2. 5. 8. 11は実数から整数へ
の型変換の演算結果、1ine3,6,9.12は実数
の倍精度から単精度への型変換の演算結果である。これ
らに示される様に実数から整数への変換鴫の丸めは切り
拾てであり、実数の倍精度から単精度への変換時の丸め
は四捨五入で行なわれる。
1ine 10.17 and 24.31 in the glogram example are type conversions from real numbers to integers, 1ine 11. 18.2
5゜32 is the type conversion of real number from double precision to single precision, and the operation result 1ine2. 5. 8. 11 is the result of a type conversion from a real number to an integer, and 1ine3, 6, 9.12 are the results of a type conversion from double precision to single precision of a real number. As shown in these figures, rounding when converting a real number to an integer is done by rounding, and rounding when converting a real number from double precision to single precision is done by rounding.

従って、他の演算時に、他の丸めモードを指定した場合
、型変換が生じる毎に丸めのf11!類を指定し直さな
ければならないのである。
Therefore, if you specify another rounding mode during another operation, each time a type conversion occurs, the rounding f11! The class must be respecified.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の丸め指示方式は、丸めのね類を指定する第一の
手段と、%定の命令を識別する識別手段と、識別手段の
指示によシ丸めの種類を指示する第二の指定手段と、第
一、又は第二〇指示手段のいづれかの選択を指示する指
示手段と、指示手段の指示に従い丸めを実行する丸め手
段を有し、指示手段による指示のない場合には、第一の
指定手段の指定に従い丸めを実行し、指示手段による指
示があり、かつ、命令の識別手段により特定の命令が識
別された場合には、第二〇指示手段の指定を優先して、
丸めを実行し、その他の場合には、第一の指定手段の指
定を優先して丸めを実行することが可能な丸め指定方式
である。
The rounding instruction method of the present invention includes a first means for specifying the type of rounding, an identification means for identifying a percentage command, and a second specifying means for specifying the type of rounding according to the instruction of the identification means. , an instruction means for instructing the selection of either the first or the 20th instruction means, and a rounding means for executing rounding according to the instructions of the instruction means, and if there is no instruction by the instruction means, the first one is selected. Rounding is performed according to the specification of the specifying means, and when there is an instruction by the specifying means and a specific instruction is identified by the instruction identifying means, the specification of the 20th specifying means is given priority,
This is a rounding designation method in which rounding is performed, and in other cases, rounding can be performed with priority given to the designation by the first designation means.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

;爪1図は、不発明の詩求範囲の一実施例の構成概要図
、第2図は優先回路の説明図、第4図は命令と丸めの抱
類による対応表である。
; Figure 1 is a schematic diagram of the configuration of an embodiment of the scope of uninvented poetry, Figure 2 is an explanatory diagram of a priority circuit, and Figure 4 is a correspondence table based on the inclusion of commands and rounding.

第1図に於て、1は4ビツトのフリップフロッグ、2は
命令デコーダ、3ばPLA、4は1ビツトのフリップフ
ロッグ、5は優先回路、6は丸め実行回路でろる。
In FIG. 1, 1 is a 4-bit flip-flop, 2 is an instruction decoder, 3 is a PLA, 4 is a 1-bit flip-flop, 5 is a priority circuit, and 6 is a rounding execution circuit.

lの情報はCPUの特つ沓さ込み命令等によりセットさ
れる。各ピットは、それぞれの丸めモードに対応し% 
4ビツト中の1ビツトのみが1の値を持つように値をセ
ットする。この値は4の値がOの場合は、5の優先回路
に従い、6へ出力される。又、4の1直が1の場合は2
により特定の命令がデコードされて、3のP L Aに
入力されている信号線の内、対応するものが1になると
第1表に従い、PLAでプログラムされた出力線が1と
なり、5の優先回路に従い3から6へ出力される。
The information of 1 is set by a special insert command of the CPU. Each pit corresponds to a respective rounding mode%
Set the value so that only 1 bit out of 4 bits has a value of 1. If the value of 4 is O, this value is output to 6 according to the priority circuit of 5. Also, if 4's 1st shift is 1, 2
When a specific command is decoded and the corresponding one among the signal lines input to PLA in 3 becomes 1, the output line programmed in PLA becomes 1 according to Table 1, and the priority of 5 becomes 1. It is output from 3 to 6 according to the circuit.

5は優先回路であシ、4の出力が0の時は1からの出力
を優先し、6へ供給し、4の出力が1の時には、3の出
力のいずれかが1であれば、その出力を、そうでなけれ
ば、1からの出力を優先し。
5 is a priority circuit. When the output of 4 is 0, it gives priority to the output from 1 and supplies it to 6. When the output of 4 is 1, if any of the outputs of 3 is 1, output, otherwise give priority to output from 1.

6へ供給する。Supply to 6.

次に音光回路5の具体例を、第2[Qを用いて。Next, a specific example of the sound-light circuit 5 will be explained using the second [Q].

説明する。第2図に於て11〜16はアンド回路。explain. In Fig. 2, 11 to 16 are AND circuits.

17〜19はオア回路%20はナンド回路、21〜24
は1からの出力信号、25.26は3からの出力信号、
27は1ビツトの7リツプ70ツグ28〜31は6への
出力信号である。たとえば、1からの信号24が1であ
ったとする。
17-19 are OR circuits %20 is NAND circuits, 21-24
is the output signal from 1, 25.26 is the output signal from 3,
27 is a 1-bit 7-rip 70g. 28-31 are output signals to 6. For example, assume that the signal 24 from 1 is 1.

この時27からの信号が0であれば、1からの信号24
が夕先され、30が6へ出力される。
If the signal from 27 is 0 at this time, the signal 24 from 1
is output in the evening, and 30 is output to 6.

次に1からの信号24が1でかつ27の信号が1であっ
たとする。この時、3からの信号25が1の時には3か
らの信号が蔓先され% 28が6へ出力される。又、3
からの信号25.21?共に0の場合1からの信号がツ
先されて、30が6へ出力される。
Next, assume that the signal 24 from 1 is 1 and the signal 27 is 1. At this time, when the signal 25 from 3 is 1, the signal from 3 is taken over and %28 is output to 6. Also, 3
Signal from 25.21? If both are 0, the signal from 1 is skipped and 30 is output to 6.

以上説明した様に4からの出力によシ1で指定した信号
か3で指示した信号のいずれかが、優先され、丸めを実
行する。
As explained above, either the signal specified by 1 or the signal specified by 3 is given priority in the output from 4, and rounding is executed.

〔発明の効果〕〔Effect of the invention〕

以上N’2明したように1本発明は、丸めの種類を指示
する第一の指定手段以外に、命令を識別する。
As explained above, the present invention identifies an instruction in addition to the first designation means that designates the type of rounding.

識別手段により丸めのf4類を指定する第二〇指足手段
、第一の指定手段又は第二の指定手段のいずれかを指示
する指示手段を設け、指示手段の指示に従い、丸めを実
行させることにより、丸めの種類があらかじめ決まって
いるある特定の命令に対しては、含分が変わる毎に改め
て丸めを指定し直す必要がなく、オーバーヘッドが生じ
なくてすむという効果がある。
Providing an instruction means for instructing either the 20th finger/toe means, the first specifying means, or the second specifying means for specifying class f4 rounding by the identification means, and causing rounding to be executed according to the instruction of the instruction means. Therefore, for a specific instruction in which the type of rounding is predetermined, there is no need to respecify rounding every time the inclusion changes, and there is no need for overhead to occur.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一笑施f11の構成位要因、第2図は
号先回路の説明図、第3図はグログラム例と。 演(:結果を示す図、第4図は命令と丸めのm知の対応
の図である。 1・・・・・・4ビツトの7リツプクロツプ、2・・・
・・・命令デコーダ、3・・・・・・PLA、4・・・
・・・1ビツトの7リツプフロツプ、5・・・・・・優
先回路、6・・・・・・丸め回路% 11〜16・・団
・アンド回路、17〜19・・団・オア回路、20・・
団・ナンド回路、21〜24・・印・1からの出力信号
、25〜26・・・・・・3からの出力信号% 27・
・・・・・1ピツトの7リツプフロツグ、28〜31・
・・・・・6への出力信号。 第7図 見3図 +    1Hnclude  (StdiO,hン3
    ma+nH 6float   fi 7           ir+t     i;9 
         d  mI I  0OOQOOO
OOOOOIiIQ           f  思 
d+16          d  =  O,’?Q
QQ9q9’?’?Qf9’hZ 23          (1=  −l  0000
000000001124             
   F  = d書lシ ”          d  =  −OQQQQ9Q
’?QQ’?QQ9r第3区 (剖 演 算綿入 2  イ名稍1°5 $I’f!r L 〜n * M
 16 、弧rKf1人でhb。
FIG. 1 shows the constituent factors of the implementation f11 of the present invention, FIG. 2 shows an explanatory diagram of the target circuit, and FIG. 3 shows an example of the program. Figure 4 shows the correspondence between commands and rounding. 1...7 rip crops of 4 bits, 2...
...Instruction decoder, 3...PLA, 4...
...7 lip-flops of 1 bit, 5...Priority circuit, 6...Rounding circuit% 11-16...Group/AND circuit, 17-19...Group/OR circuit, 20・・・
Group/Nand circuit, 21-24...output signal from mark 1, 25-26...output signal from 3% 27.
...1 pit 7 lip frog, 28-31.
...Output signal to 6. Figure 7, Figure 3 + 1Hnclude (StdiO,hn3
ma+nH 6float fi 7 ir+t i;9
d mI I 0OOQOOOO
OOOOOOIiIQ f Thoughts
d+16 d=O,'? Q
QQ9q9'? '? Qf9'hZ 23 (1= -l 0000
000000001124
F = d d = -OQQQQ9Q
'? QQ'? QQ9r 3rd ward (anatomy operation cotton inclusion 2 name name 1°5 $I'f!r L ~ n * M
16, Arc rKf1 person hb.

Claims (1)

【特許請求の範囲】[Claims] 複数のデータタイプを扱い数値演算を実行するシステム
に於て丸めの種類を指示する第一の指定手段と、特定の
命令を識別する識別手段と、識別手段の指示により丸め
の種類を指定する。第二の手段と、第一あるいは第二の
指定手段のいずれかの選択を指示する指示手段と、指示
手段の指定に従い、丸めを実行する丸め手段とを備え、
指示手段による指示のない場合には、第一の指示手段の
指示に従い丸め手段を活性化し、丸めを実行するが指示
手段による指示があり、かつ命令の識別手段により特定
の命令が識別された場合には、第二の指示手段の指示を
優先して丸めを実行し、その他の場合には、第一の指示
手段の指定を、優先して、丸めを実行することを特徴と
する丸め指示方式。
In a system that handles a plurality of data types and performs numerical operations, a first designation means for designating the type of rounding, an identification means for identifying a specific command, and a type of rounding is designated by the instruction from the identification means. a second means, an instruction means for instructing selection of either the first or second specifying means, and a rounding means for executing rounding according to the specification of the instruction means,
If there is no instruction from the instruction means, the rounding means is activated and rounding is performed according to the instruction from the first instruction means, but if there is an instruction from the instruction means and a specific instruction is identified by the instruction identification means. In other cases, the rounding is performed by giving priority to the instruction from the second instruction means, and in other cases, the rounding is performed by giving priority to the instruction from the first instruction means. .
JP60291140A 1985-12-23 1985-12-23 Rounding specification method Expired - Lifetime JPH0625965B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60291140A JPH0625965B2 (en) 1985-12-23 1985-12-23 Rounding specification method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60291140A JPH0625965B2 (en) 1985-12-23 1985-12-23 Rounding specification method

Publications (2)

Publication Number Publication Date
JPS62150431A true JPS62150431A (en) 1987-07-04
JPH0625965B2 JPH0625965B2 (en) 1994-04-06

Family

ID=17764963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60291140A Expired - Lifetime JPH0625965B2 (en) 1985-12-23 1985-12-23 Rounding specification method

Country Status (1)

Country Link
JP (1) JPH0625965B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593872U (en) * 1991-08-21 1993-12-21 建治 大朏 Heading label

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116033A (en) * 1976-03-25 1977-09-29 Casio Comput Co Ltd Operational control system for electronic computer with program
JPS60164247U (en) * 1984-03-30 1985-10-31 カシオ計算機株式会社 Rounding calculation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116033A (en) * 1976-03-25 1977-09-29 Casio Comput Co Ltd Operational control system for electronic computer with program
JPS60164247U (en) * 1984-03-30 1985-10-31 カシオ計算機株式会社 Rounding calculation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593872U (en) * 1991-08-21 1993-12-21 建治 大朏 Heading label

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Publication number Publication date
JPH0625965B2 (en) 1994-04-06

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