JPS5954260A - 半導体記憶装置およびその製造方法 - Google Patents

半導体記憶装置およびその製造方法

Info

Publication number
JPS5954260A
JPS5954260A JP57163889A JP16388982A JPS5954260A JP S5954260 A JPS5954260 A JP S5954260A JP 57163889 A JP57163889 A JP 57163889A JP 16388982 A JP16388982 A JP 16388982A JP S5954260 A JPS5954260 A JP S5954260A
Authority
JP
Japan
Prior art keywords
region
film
type
layer
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57163889A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0340955B2 (enExample
Inventor
Hisao Katsuto
甲藤　久郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57163889A priority Critical patent/JPS5954260A/ja
Publication of JPS5954260A publication Critical patent/JPS5954260A/ja
Publication of JPH0340955B2 publication Critical patent/JPH0340955B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP57163889A 1982-09-22 1982-09-22 半導体記憶装置およびその製造方法 Granted JPS5954260A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57163889A JPS5954260A (ja) 1982-09-22 1982-09-22 半導体記憶装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57163889A JPS5954260A (ja) 1982-09-22 1982-09-22 半導体記憶装置およびその製造方法

Publications (2)

Publication Number Publication Date
JPS5954260A true JPS5954260A (ja) 1984-03-29
JPH0340955B2 JPH0340955B2 (enExample) 1991-06-20

Family

ID=15782722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57163889A Granted JPS5954260A (ja) 1982-09-22 1982-09-22 半導体記憶装置およびその製造方法

Country Status (1)

Country Link
JP (1) JPS5954260A (enExample)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197961A (ja) * 1984-10-19 1986-05-16 Hitachi Ltd 半導体集積回路装置の製造方法
JPS61100958A (ja) * 1984-10-22 1986-05-19 Nec Corp 半導体メモリ集積回路装置
JPS61156864A (ja) * 1984-12-28 1986-07-16 Nec Corp 半導体メモリ
JPS62249474A (ja) * 1986-04-23 1987-10-30 Hitachi Ltd 半導体集積回路装置
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US5148255A (en) * 1985-09-25 1992-09-15 Hitachi, Ltd. Semiconductor memory device
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
US5264385A (en) * 1991-12-09 1993-11-23 Texas Instruments Incorporated SRAM design with no moat-to-moat spacing
US5369046A (en) * 1991-04-08 1994-11-29 Texas Instruments Incorporated Method for forming a gate array base cell
USRE38296E1 (en) * 1987-04-24 2003-11-04 Hitachi, Ltd. Semiconductor memory device with recessed array region

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197961A (ja) * 1984-10-19 1986-05-16 Hitachi Ltd 半導体集積回路装置の製造方法
JPS61100958A (ja) * 1984-10-22 1986-05-19 Nec Corp 半導体メモリ集積回路装置
JPS61156864A (ja) * 1984-12-28 1986-07-16 Nec Corp 半導体メモリ
US5148255A (en) * 1985-09-25 1992-09-15 Hitachi, Ltd. Semiconductor memory device
JPS62249474A (ja) * 1986-04-23 1987-10-30 Hitachi Ltd 半導体集積回路装置
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
USRE38296E1 (en) * 1987-04-24 2003-11-04 Hitachi, Ltd. Semiconductor memory device with recessed array region
US5369046A (en) * 1991-04-08 1994-11-29 Texas Instruments Incorporated Method for forming a gate array base cell
US5652441A (en) * 1991-04-08 1997-07-29 Texas Instruments Incorporated Gate array base cell with novel gate structure
US5264385A (en) * 1991-12-09 1993-11-23 Texas Instruments Incorporated SRAM design with no moat-to-moat spacing

Also Published As

Publication number Publication date
JPH0340955B2 (enExample) 1991-06-20

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