JPS5954239A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS5954239A
JPS5954239A JP57165404A JP16540482A JPS5954239A JP S5954239 A JPS5954239 A JP S5954239A JP 57165404 A JP57165404 A JP 57165404A JP 16540482 A JP16540482 A JP 16540482A JP S5954239 A JPS5954239 A JP S5954239A
Authority
JP
Japan
Prior art keywords
wiring
unit cells
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57165404A
Other languages
English (en)
Japanese (ja)
Other versions
JPH023549B2 (enrdf_load_stackoverflow
Inventor
Akiji Hirabayashi
平林　莞爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57165404A priority Critical patent/JPS5954239A/ja
Publication of JPS5954239A publication Critical patent/JPS5954239A/ja
Publication of JPH023549B2 publication Critical patent/JPH023549B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP57165404A 1982-09-22 1982-09-22 半導体集積回路装置 Granted JPS5954239A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165404A JPS5954239A (ja) 1982-09-22 1982-09-22 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165404A JPS5954239A (ja) 1982-09-22 1982-09-22 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS5954239A true JPS5954239A (ja) 1984-03-29
JPH023549B2 JPH023549B2 (enrdf_load_stackoverflow) 1990-01-24

Family

ID=15811761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165404A Granted JPS5954239A (ja) 1982-09-22 1982-09-22 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS5954239A (enrdf_load_stackoverflow)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591856A (en) * 1978-12-29 1980-07-11 Ibm Semiconductor integrated circuit chip structure
JPS57112062A (en) * 1980-12-05 1982-07-12 Cii High density integrated circuit device
JPS57192061A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591856A (en) * 1978-12-29 1980-07-11 Ibm Semiconductor integrated circuit chip structure
JPS57112062A (en) * 1980-12-05 1982-07-12 Cii High density integrated circuit device
JPS57192061A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH023549B2 (enrdf_load_stackoverflow) 1990-01-24

Similar Documents

Publication Publication Date Title
KR100676980B1 (ko) 집적 회로 및 집적 회로의 도전체 레이아웃 설계 방법
US10503859B2 (en) Integrated circuit design and/or fabrication
US6590289B2 (en) Hexadecagonal routing
EP0295410B1 (en) Macro structural arrangement and method for generating macros for vlsi semiconductor circuit devices
US10777505B2 (en) Method of fabricating integrated circuit having staggered conductive features
US3654615A (en) Element placement system
EP0296697A2 (en) A method of operating a digital computer to set routing paths
US20140115554A1 (en) Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance
US11675949B2 (en) Space optimization between SRAM cells and standard cells
US11748546B2 (en) System and method for back side signal routing
US20230267263A1 (en) Space Optimization Between SRAM Cells and Standard Cells
KR100293021B1 (ko) 집적회로장치의제조방법및집적회로장치
US20060123373A1 (en) Density driven layout for RRAM configuration module
JPS5954239A (ja) 半導体集積回路装置
JPS5911670A (ja) 半導体集積回路装置
JP2003142583A (ja) 半導体装置及びその設計方法
CN114005829A (zh) 用于四个堆叠层三维交叉点存储器的阵列和接触架构
JPS59117132A (ja) マスタスライスｌｓｉ基板
Tanaka et al. An integrated computer aided design system for gate array masterslices: Part 2 The layout design system Mars-M3
JPS62273751A (ja) 集積回路
JPS605059B2 (ja) 大規模半導体集積回路
JPS5936942A (ja) 半導体集積回路
JP2505039B2 (ja) 機能ブロック上を通過する配線の配線方法
JP2803800B2 (ja) 半導体集積回路装置の配線方法
JPS59161046A (ja) 半導体装置における配線方法